arch/arm/mach-rockchip/rk312x.c

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/clocksource.h>
  17 #include <linux/cpuidle.h>
  18 #include <linux/delay.h>
  19 #include <linux/init.h>
  20 #include <linux/irqchip.h>
  21 #include <linux/kernel.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/rockchip/common.h>
  25 #include <linux/rockchip/cpu.h>
  26 #include <linux/rockchip/cpu_axi.h>
  27 #include <linux/rockchip/cru.h>
  28 #include <linux/rockchip/dvfs.h>
  29 #include <linux/rockchip/grf.h>
  30 #include <linux/rockchip/iomap.h>
  31 #include <linux/rockchip/pmu.h>
  32 /*#include <asm/cpuidle.h>*/
  33 #include <asm/cputype.h>
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/map.h>
  36 #include "loader.h"
  37 #include "rk3126b.h"
  38 #define CPU 312x
  39 #include "sram.h"
  40 #include "pm.h"
  41 #include "pm-rk312x.c"
  42 #include <linux/rockchip/cpu.h>
  43 #define RK312X_DEVICE(name) \
  44         { \
  45                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  46                 .pfn            = __phys_to_pfn(RK312X_##name##_PHYS), \
  47                 .length         = RK312X_##name##_SIZE, \
  48                 .type           = MT_DEVICE, \
  49         }
  50
  51 static const char * const rk3126_dt_compat[] __initconst = {
  52         "rockchip,rk3126",
  53         NULL,
  54 };
  55
  56 static const char * const rk3128_dt_compat[] __initconst = {
  57         "rockchip,rk3128",
  58         NULL,
  59 };
  60
  61 #define RK312X_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  62 #define RK312X_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  63
  64 static struct map_desc rk312x_io_desc[] __initdata = {
  65         RK312X_DEVICE(CRU),
  66         RK312X_DEVICE(GRF),
  67         RK312X_DEVICE(ROM),
  68         RK312X_DEVICE(PMU),
  69         RK312X_DEVICE(EFUSE),
  70         RK312X_DEVICE(TIMER),
  71         RK312X_DEVICE(CPU_AXI_BUS),
  72         RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE),
  73         RK_DEVICE(RK_DDR_VIRT, RK312X_DDR_PCTL_PHYS, RK312X_DDR_PCTL_SIZE),
  74         RK_DEVICE(RK_DDR_VIRT + RK312X_DDR_PCTL_SIZE, RK312X_DDR_PHY_PHYS, RK312X_DDR_PHY_SIZE),
  75         RK_DEVICE(RK_GPIO_VIRT(0), RK312X_GPIO0_PHYS, RK312X_GPIO_SIZE),
  76         RK_DEVICE(RK_GPIO_VIRT(1), RK312X_GPIO1_PHYS, RK312X_GPIO_SIZE),
  77         RK_DEVICE(RK_GPIO_VIRT(2), RK312X_GPIO2_PHYS, RK312X_GPIO_SIZE),
  78         RK_DEVICE(RK_GPIO_VIRT(3), RK312X_GPIO3_PHYS, RK312X_GPIO_SIZE),
  79         RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
  80         RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
  81         RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
  82         RK_DEVICE(RK_PWM_VIRT, RK312X_PWM_PHYS, RK312X_PWM_SIZE),
  83 };
  84
  85 static void __init rk312x_boot_mode_init(void)
  86 {
  87         u32 flag = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
  88         u32 mode = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
  89         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_RST_ST);
  90
  91         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
  92                 mode = BOOT_MODE_RECOVERY;
  93         if (rst_st & ((1 << 2) | (1 << 3)))
  94                 mode = BOOT_MODE_WATCHDOG;
  95
  96         rockchip_boot_mode_init(flag, mode);
  97 }
  98
  99 static void usb_uart_init(void)
 100 {
 101 #ifdef CONFIG_RK_USB_UART
 102         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_STATUS0);
 103 #endif
 104         writel_relaxed(0x34000000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 105 #ifdef CONFIG_RK_USB_UART
 106         if (!(soc_status0 & (1 << 5)) && (soc_status0 & (1 << 8))) {
 107                 /* software control usb phy enable */
 108                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK312X_GRF_UOC0_CON0);
 109                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 110         }
 111 #endif
 112
 113         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
 114         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 115         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 116         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 117         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 118         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 119 }
 120
 121 static void __init rk312x_dt_map_io(void)
 122 {
 123         u32 v;
 124
 125         iotable_init(rk312x_io_desc, ARRAY_SIZE(rk312x_io_desc));
 126         debug_ll_io_init();
 127         usb_uart_init();
 128
 129         /* pmu reset by second global soft reset */
 130         v = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 131         v &= ~(3 << 12);
 132         v |= 1 << 12;
 133         writel_relaxed(v, RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 134
 135         /* enable timer5 for core */
 136         writel_relaxed(0, RK312X_TIMER5_VIRT + 0x10);
 137         dsb();
 138         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x00);
 139         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x04);
 140         dsb();
 141         writel_relaxed(1, RK312X_TIMER5_VIRT + 0x10);
 142         dsb();
 143         writel_relaxed(0x80000000, RK_CRU_VIRT + RK312X_CRU_MISC_CON);
 144         dsb();
 145
 146         rk312x_boot_mode_init();
 147         rockchip_efuse_init();
 148 }
 149
 150 static void __init rk3126_dt_map_io(void)
 151 {
 152         rockchip_soc_id = ROCKCHIP_SOC_RK3126;
 153
 154         rk312x_dt_map_io();
 155
 156         if (readl_relaxed(RK_GRF_VIRT + RK312X_GRF_CHIP_TAG) == 0x3136)
 157                 rockchip_soc_id = ROCKCHIP_SOC_RK3126B;
 158 }
 159
 160 static void __init rk3128_dt_map_io(void)
 161 {
 162         rockchip_soc_id = ROCKCHIP_SOC_RK3128;
 163
 164         rk312x_dt_map_io();
 165 }
 166 static DEFINE_SPINLOCK(pmu_idle_lock);
 167 static const u8 pmu_idle_map[] = {
 168         [IDLE_REQ_PERI] = 0,
 169         [IDLE_REQ_VIDEO] = 1,
 170         [IDLE_REQ_VIO] = 2,
 171         [IDLE_REQ_GPU] = 3,
 172         [IDLE_REQ_CORE] = 4,
 173         [IDLE_REQ_SYS] = 5,
 174         [IDLE_REQ_MSCH] = 6,
 175         [IDLE_REQ_CRYPTO] = 7,
 176
 177 };
 178 static int rk312x_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 179 {
 180         u32 val;
 181         unsigned long flags;
 182         u32 bit = pmu_idle_map[req];
 183         u32 idle_mask = BIT(bit) | BIT(bit + 16);
 184         u32 idle_target = (idle << bit) | (idle << (bit + 16));
 185         u32 mask = BIT(bit);
 186
 187         spin_lock_irqsave(&pmu_idle_lock, flags);
 188         val = pmu_readl(RK312X_PMU_IDLE_REQ);
 189         if (idle)
 190                 val |= mask;
 191         else
 192                 val &= ~mask;
 193         pmu_writel(val, RK312X_PMU_IDLE_REQ);
 194         dsb();
 195
 196         while (((pmu_readl(RK312X_PMU_IDLE_ST) & idle_mask) != idle_target))
 197                 ;
 198         spin_unlock_irqrestore(&pmu_idle_lock, flags);
 199         return 0;
 200 }
 201 static const u8 pmu_pd_map[] = {
 202         [PD_GPU] = 1,
 203         [PD_VIDEO] = 2,
 204         [PD_VIO] = 3,
 205 };
 206
 207 static const u8 pmu_st_map[] = {
 208         [PD_GPU] = 1,
 209         [PD_VIDEO] = 2,
 210         [PD_VIO] = 3,
 211 };
 212
 213 static noinline void rk312x_do_pmu_set_power_domain(enum pmu_power_domain domain
 214         , bool on)
 215 {
 216         u8 pd = pmu_pd_map[domain];
 217         u32 val = pmu_readl(RK312X_PMU_PWRDN_CON);
 218
 219         if (on)
 220                 val &= ~BIT(pd);
 221         else
 222                 val |=  BIT(pd);
 223         pmu_writel(val, RK312X_PMU_PWRDN_CON);
 224         dsb();
 225
 226         while ((pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
 227                 ;
 228 }
 229
 230 static bool rk312x_pmu_power_domain_is_on(enum pmu_power_domain pd)
 231 {
 232         /*1"b0: power on, 1'b1: power off*/
 233         return !(pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
 234 }
 235 static DEFINE_SPINLOCK(pmu_pd_lock);
 236 static u32 rga_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 237 static u32 ebc_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 238 static u32 iep_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 239 static u32 lcdc0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 240 static u32 vip0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 241 static u32 gpu_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 242 static u32 video_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 243
 244 #define SAVE_QOS(array, NAME) RK312X_CPU_AXI_SAVE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 245 #define RESTORE_QOS(array, NAME) RK312X_CPU_AXI_RESTORE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 246
 247 static int rk312x_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 248 {
 249         unsigned long flags;
 250
 251         spin_lock_irqsave(&pmu_pd_lock, flags);
 252         if (rk312x_pmu_power_domain_is_on(pd) == on)
 253                 goto out;
 254         if (!on) {
 255                 if (pd == PD_GPU) {
 256                         SAVE_QOS(gpu_qos, GPU);
 257                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, true);
 258                 } else if (pd == PD_VIO) {
 259                         SAVE_QOS(rga_qos, VIO_RGA);
 260                         if (!soc_is_rk3126b())
 261                                 SAVE_QOS(ebc_qos, VIO_EBC);
 262                         SAVE_QOS(iep_qos, VIO_IEP);
 263                         SAVE_QOS(lcdc0_qos, VIO_LCDC0);
 264                         SAVE_QOS(vip0_qos, VIO_VIP0);
 265                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, true);
 266                 } else if (pd == PD_VIDEO) {
 267                         SAVE_QOS(video_qos, VIDEO);
 268                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 269                 }
 270         }
 271
 272         rk312x_do_pmu_set_power_domain(pd, on);
 273
 274         if (on) {
 275                 if (pd == PD_GPU) {
 276                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, false);
 277                         RESTORE_QOS(gpu_qos, GPU);
 278                 } else if (pd == PD_VIO) {
 279                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, false);
 280                         RESTORE_QOS(rga_qos, VIO_RGA);
 281                         if (!soc_is_rk3126b())
 282                                 RESTORE_QOS(ebc_qos, VIO_EBC);
 283                         RESTORE_QOS(iep_qos, VIO_IEP);
 284                         RESTORE_QOS(lcdc0_qos, VIO_LCDC0);
 285                         RESTORE_QOS(vip0_qos, VIO_VIP0);
 286                 } else if (pd == PD_VIDEO) {
 287                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 288                         RESTORE_QOS(video_qos, VIDEO);
 289                 }
 290         }
 291 out:
 292         spin_unlock_irqrestore(&pmu_pd_lock, flags);
 293
 294         return 0;
 295 }
 296 extern void secondary_startup(void);
 297 static int rk312x_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 298 {
 299         u32 clks_save[RK312X_CRU_CLKGATES_CON_CNT];
 300         u32 clks_ungating[RK312X_CRU_CLKGATES_CON_CNT];
 301         u32 i, ret = 0;
 302
 303         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 304                 clks_save[i] = cru_readl(RK312X_CRU_CLKGATES_CON(i));
 305                 clks_ungating[i] = 0;
 306         }
 307         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++)
 308                 cru_writel(0xffff0000, RK312X_CRU_CLKGATES_CON(i));
 309
 310         if (on) {
 311 #ifdef CONFIG_SMP
 312                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 313                         writel_relaxed(0x20000 << (pd - PD_CPU_1),
 314                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 315                         dsb();
 316                         udelay(10);
 317                         writel_relaxed(virt_to_phys(secondary_startup),
 318                                        RK312X_IMEM_VIRT + 8);
 319                         writel_relaxed(0xDEADBEAF, RK312X_IMEM_VIRT + 4);
 320                         dsb_sev();
 321                 }
 322 #endif
 323         } else {
 324 #ifdef CONFIG_SMP
 325                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 326                         writel_relaxed(0x20002 << (pd - PD_CPU_1),
 327                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 328                         dsb();
 329                 }
 330 #endif
 331         }
 332
 333         if (((pd == PD_GPU) || (pd == PD_VIO) || (pd == PD_VIDEO)))
 334                 ret = rk312x_pmu_set_power_domain(pd, on);
 335
 336         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 337                 cru_writel(clks_save[i] | 0xffff0000
 338                         , RK312X_CRU_CLKGATES_CON(i));
 339         }
 340
 341         return ret;
 342 }
 343
 344 static void __init rk312x_dt_init_timer(void)
 345 {
 346         rockchip_pmu_ops.set_power_domain = rk312x_sys_set_power_domain;
 347         rockchip_pmu_ops.power_domain_is_on = rk312x_pmu_power_domain_is_on;
 348         rockchip_pmu_ops.set_idle_request = rk312x_pmu_set_idle_request;
 349         of_clk_init(NULL);
 350         clocksource_of_init();
 351         of_dvfs_init();
 352 }
 353
 354 static void __init rk312x_reserve(void)
 355 {
 356         /* reserve memory for uboot */
 357         rockchip_uboot_mem_reserve();
 358
 359         /* reserve memory for ION */
 360         rockchip_ion_reserve();
 361 }
 362
 363 #ifdef CONFIG_PM
 364 static u32 rk_pmu_pwrdn_st;
 365
 366 static void rk_pm_soc_pd_suspend(void)
 367 {
 368         rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST);
 369         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 370                 rk312x_sys_set_power_domain(PD_GPU, false);
 371
 372         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 373                 rk312x_sys_set_power_domain(PD_VIO, false);
 374
 375         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 376                 rk312x_sys_set_power_domain(PD_VIDEO, false);
 377 }
 378
 379 static void rk_pm_soc_pd_resume(void)
 380 {
 381         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 382                 rk312x_sys_set_power_domain(PD_VIDEO, true);
 383
 384         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 385                 rk312x_sys_set_power_domain(PD_VIO, true);
 386
 387         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 388                 rk312x_sys_set_power_domain(PD_GPU, true);
 389 }
 390
 391 static void __init rk312x_init_suspend(void)
 392 {
 393         pr_info("%s\n", __func__);
 394         rkpm_pie_init();
 395         rk312x_suspend_init();
 396 }
 397 #endif
 398
 399 static void __init rk312x_init_late(void)
 400 {
 401 #ifdef CONFIG_PM
 402         rockchip_suspend_init();
 403         if (soc_is_rk3126b())
 404                 rk3126b_init_suspend();
 405         else
 406                 rk312x_init_suspend();
 407         rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume);
 408 #endif
 409         if (rockchip_jtag_enabled)
 410                 clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
 411 }
 412
 413 static void rk312x_restart(char mode, const char *cmd)
 414 {
 415         u32 boot_flag, boot_mode;
 416
 417         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 418
 419         /* for loader */
 420         writel_relaxed(boot_flag, RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
 421         /* for linux */
 422         writel_relaxed(boot_mode, RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
 423
 424         dsb();
 425
 426         /* pll enter slow mode */
 427         writel_relaxed(0x11010000, RK_CRU_VIRT + RK312X_CRU_MODE_CON);
 428         dsb();
 429         writel_relaxed(0xeca8, RK_CRU_VIRT + RK312X_CRU_GLB_SRST_SND_VALUE);
 430         dsb();
 431 }
 432
 433 DT_MACHINE_START(RK3126_DT, "Rockchip RK3126")
 434         .smp            = smp_ops(rockchip_smp_ops),
 435         .map_io         = rk3126_dt_map_io,
 436         .init_time      = rk312x_dt_init_timer,
 437         .dt_compat      = rk3126_dt_compat,
 438         .init_late      = rk312x_init_late,
 439         .reserve        = rk312x_reserve,
 440         .restart        = rk312x_restart,
 441 MACHINE_END
 442
 443 DT_MACHINE_START(RK3128_DT, "Rockchip RK3128")
 444         .smp            = smp_ops(rockchip_smp_ops),
 445         .map_io         = rk3128_dt_map_io,
 446         .init_time      = rk312x_dt_init_timer,
 447         .dt_compat      = rk3128_dt_compat,
 448         .init_late      = rk312x_init_late,
 449         .reserve        = rk312x_reserve,
 450         .restart        = rk312x_restart,
 451 MACHINE_END
 452
 453
 454 char PIE_DATA(sram_stack)[1024];
 455 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 456
 457 static int __init rk312x_pie_init(void)
 458 {
 459         int err;
 460
 461         if (!cpu_is_rk312x())
 462                 return 0;
 463         if (soc_is_rk3126b())
 464                 return 0;
 465
 466         err = rockchip_pie_init();
 467         if (err)
 468                 return err;
 469
 470         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk312x);
 471         if (IS_ERR(rockchip_pie_chunk)) {
 472                 err = PTR_ERR(rockchip_pie_chunk);
 473                 pr_err("%s: failed to load section %d\n", __func__, err);
 474                 rockchip_pie_chunk = NULL;
 475                 return err;
 476         }
 477
 478         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 479         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 480
 481         return 0;
 482 }
 483 arch_initcall(rk312x_pie_init);
 484
 485 #include "ddr_rk3126.c"
 486 static int __init rk312x_ddr_init(void)
 487 {
 488         if (soc_is_rk3128() || soc_is_rk3126()) {
 489                 ddr_change_freq = _ddr_change_freq;
 490                 ddr_round_rate = _ddr_round_rate;
 491                 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 492                 ddr_bandwidth_get = _ddr_bandwidth_get;
 493                 ddr_init(DDR3_DEFAULT, 0);
 494         }
 495
 496         return 0;
 497 }
 498 arch_initcall_sync(rk312x_ddr_init);