arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/soc/rockchip,boot-mode.h>
  47 #include "skeleton.dtsi"
  48
  49 / {
  50         interrupt-parent = <&gic>;
  51
  52         aliases {
  53                 i2c0 = &i2c0;
  54                 i2c1 = &i2c1;
  55                 i2c2 = &i2c2;
  56                 i2c3 = &i2c3;
  57                 i2c4 = &i2c4;
  58                 mshc0 = &emmc;
  59                 mshc1 = &mmc0;
  60                 mshc2 = &mmc1;
  61                 serial0 = &uart0;
  62                 serial1 = &uart1;
  63                 serial2 = &uart2;
  64                 serial3 = &uart3;
  65                 spi0 = &spi0;
  66                 spi1 = &spi1;
  67         };
  68
  69         amba {
  70                 compatible = "arm,amba-bus";
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 ranges;
  74
  75                 dmac1_s: dma-controller@20018000 {
  76                         compatible = "arm,pl330", "arm,primecell";
  77                         reg = <0x20018000 0x4000>;
  78                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  80                         #dma-cells = <1>;
  81                         arm,pl330-broken-no-flushp;
  82                         clocks = <&cru ACLK_DMA1>;
  83                         clock-names = "apb_pclk";
  84                 };
  85
  86                 dmac1_ns: dma-controller@2001c000 {
  87                         compatible = "arm,pl330", "arm,primecell";
  88                         reg = <0x2001c000 0x4000>;
  89                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  90                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  91                         #dma-cells = <1>;
  92                         arm,pl330-broken-no-flushp;
  93                         clocks = <&cru ACLK_DMA1>;
  94                         clock-names = "apb_pclk";
  95                         status = "disabled";
  96                 };
  97
  98                 dmac2: dma-controller@20078000 {
  99                         compatible = "arm,pl330", "arm,primecell";
 100                         reg = <0x20078000 0x4000>;
 101                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 103                         #dma-cells = <1>;
 104                         arm,pl330-broken-no-flushp;
 105                         clocks = <&cru ACLK_DMA2>;
 106                         clock-names = "apb_pclk";
 107                 };
 108         };
 109
 110         xin24m: oscillator {
 111                 compatible = "fixed-clock";
 112                 clock-frequency = <24000000>;
 113                 #clock-cells = <0>;
 114                 clock-output-names = "xin24m";
 115         };
 116
 117         L2: l2-cache-controller@10138000 {
 118                 compatible = "arm,pl310-cache";
 119                 reg = <0x10138000 0x1000>;
 120                 cache-unified;
 121                 cache-level = <2>;
 122         };
 123
 124         scu@1013c000 {
 125                 compatible = "arm,cortex-a9-scu";
 126                 reg = <0x1013c000 0x100>;
 127         };
 128
 129         global_timer: global-timer@1013c200 {
 130                 compatible = "arm,cortex-a9-global-timer";
 131                 reg = <0x1013c200 0x20>;
 132                 interrupts = <GIC_PPI 11 0x304>;
 133                 clocks = <&cru CORE_PERI>;
 134         };
 135
 136         local_timer: local-timer@1013c600 {
 137                 compatible = "arm,cortex-a9-twd-timer";
 138                 reg = <0x1013c600 0x20>;
 139                 interrupts = <GIC_PPI 13 0x304>;
 140                 clocks = <&cru CORE_PERI>;
 141         };
 142
 143         gic: interrupt-controller@1013d000 {
 144                 compatible = "arm,cortex-a9-gic";
 145                 interrupt-controller;
 146                 #interrupt-cells = <3>;
 147                 reg = <0x1013d000 0x1000>,
 148                       <0x1013c100 0x0100>;
 149         };
 150
 151         uart0: serial@10124000 {
 152                 compatible = "snps,dw-apb-uart";
 153                 reg = <0x10124000 0x400>;
 154                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 155                 reg-shift = <2>;
 156                 reg-io-width = <1>;
 157                 clock-names = "baudclk", "apb_pclk";
 158                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 159                 status = "disabled";
 160         };
 161
 162         uart1: serial@10126000 {
 163                 compatible = "snps,dw-apb-uart";
 164                 reg = <0x10126000 0x400>;
 165                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 166                 reg-shift = <2>;
 167                 reg-io-width = <1>;
 168                 clock-names = "baudclk", "apb_pclk";
 169                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 170                 status = "disabled";
 171         };
 172
 173         usb_otg: usb@10180000 {
 174                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 175                 reg = <0x10180000 0x40000>;
 176                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 177                 clocks = <&cru HCLK_OTG0>;
 178                 clock-names = "otg";
 179                 dr_mode = "otg";
 180                 g-np-tx-fifo-size = <16>;
 181                 g-rx-fifo-size = <275>;
 182                 g-tx-fifo-size = <256 128 128 64 64 32>;
 183                 g-use-dma;
 184                 phys = <&usbphy0>;
 185                 phy-names = "usb2-phy";
 186                 status = "disabled";
 187         };
 188
 189         usb_host: usb@101c0000 {
 190                 compatible = "snps,dwc2";
 191                 reg = <0x101c0000 0x40000>;
 192                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 193                 clocks = <&cru HCLK_OTG1>;
 194                 clock-names = "otg";
 195                 dr_mode = "host";
 196                 phys = <&usbphy1>;
 197                 phy-names = "usb2-phy";
 198                 status = "disabled";
 199         };
 200
 201         emac: ethernet@10204000 {
 202                 compatible = "snps,arc-emac";
 203                 reg = <0x10204000 0x3c>;
 204                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 205                 #address-cells = <1>;
 206                 #size-cells = <0>;
 207
 208                 rockchip,grf = <&grf>;
 209
 210                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 211                 clock-names = "hclk", "macref";
 212                 max-speed = <100>;
 213                 phy-mode = "rmii";
 214
 215                 status = "disabled";
 216         };
 217
 218         mmc0: dwmmc@10214000 {
 219                 compatible = "rockchip,rk2928-dw-mshc";
 220                 reg = <0x10214000 0x1000>;
 221                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 223                 clock-names = "biu", "ciu";
 224                 fifo-depth = <256>;
 225                 status = "disabled";
 226         };
 227
 228         mmc1: dwmmc@10218000 {
 229                 compatible = "rockchip,rk2928-dw-mshc";
 230                 reg = <0x10218000 0x1000>;
 231                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 233                 clock-names = "biu", "ciu";
 234                 fifo-depth = <256>;
 235                 status = "disabled";
 236         };
 237
 238         emmc: dwmmc@1021c000 {
 239                 compatible = "rockchip,rk2928-dw-mshc";
 240                 reg = <0x1021c000 0x1000>;
 241                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 242                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 243                 clock-names = "biu", "ciu";
 244                 fifo-depth = <256>;
 245                 status = "disabled";
 246         };
 247
 248         pmu: pmu@20004000 {
 249                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 250                 reg = <0x20004000 0x100>;
 251
 252                 reboot-mode {
 253                         compatible = "syscon-reboot-mode";
 254                         offset = <0x40>;
 255                         mode-normal = <BOOT_NORMAL>;
 256                         mode-recovery = <BOOT_RECOVERY>;
 257                         mode-bootloader = <BOOT_FASTBOOT>;
 258                         mode-loader = <BOOT_BL_DOWNLOAD>;
 259                         mode-ums = <BOOT_UMS>;
 260                 };
 261         };
 262
 263         grf: grf@20008000 {
 264                 compatible = "syscon";
 265                 reg = <0x20008000 0x200>;
 266         };
 267
 268         i2c0: i2c@2002d000 {
 269                 compatible = "rockchip,rk3066-i2c";
 270                 reg = <0x2002d000 0x1000>;
 271                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274
 275                 rockchip,grf = <&grf>;
 276
 277                 clock-names = "i2c";
 278                 clocks = <&cru PCLK_I2C0>;
 279
 280                 status = "disabled";
 281         };
 282
 283         i2c1: i2c@2002f000 {
 284                 compatible = "rockchip,rk3066-i2c";
 285                 reg = <0x2002f000 0x1000>;
 286                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 287                 #address-cells = <1>;
 288                 #size-cells = <0>;
 289
 290                 rockchip,grf = <&grf>;
 291
 292                 clocks = <&cru PCLK_I2C1>;
 293                 clock-names = "i2c";
 294
 295                 status = "disabled";
 296         };
 297
 298         pwm0: pwm@20030000 {
 299                 compatible = "rockchip,rk2928-pwm";
 300                 reg = <0x20030000 0x10>;
 301                 #pwm-cells = <2>;
 302                 clocks = <&cru PCLK_PWM01>;
 303                 status = "disabled";
 304         };
 305
 306         pwm1: pwm@20030010 {
 307                 compatible = "rockchip,rk2928-pwm";
 308                 reg = <0x20030010 0x10>;
 309                 #pwm-cells = <2>;
 310                 clocks = <&cru PCLK_PWM01>;
 311                 status = "disabled";
 312         };
 313
 314         wdt: watchdog@2004c000 {
 315                 compatible = "snps,dw-wdt";
 316                 reg = <0x2004c000 0x100>;
 317                 clocks = <&cru PCLK_WDT>;
 318                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 319                 status = "disabled";
 320         };
 321
 322         pwm2: pwm@20050020 {
 323                 compatible = "rockchip,rk2928-pwm";
 324                 reg = <0x20050020 0x10>;
 325                 #pwm-cells = <2>;
 326                 clocks = <&cru PCLK_PWM23>;
 327                 status = "disabled";
 328         };
 329
 330         pwm3: pwm@20050030 {
 331                 compatible = "rockchip,rk2928-pwm";
 332                 reg = <0x20050030 0x10>;
 333                 #pwm-cells = <2>;
 334                 clocks = <&cru PCLK_PWM23>;
 335                 status = "disabled";
 336         };
 337
 338         i2c2: i2c@20056000 {
 339                 compatible = "rockchip,rk3066-i2c";
 340                 reg = <0x20056000 0x1000>;
 341                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344
 345                 rockchip,grf = <&grf>;
 346
 347                 clocks = <&cru PCLK_I2C2>;
 348                 clock-names = "i2c";
 349
 350                 status = "disabled";
 351         };
 352
 353         i2c3: i2c@2005a000 {
 354                 compatible = "rockchip,rk3066-i2c";
 355                 reg = <0x2005a000 0x1000>;
 356                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359
 360                 rockchip,grf = <&grf>;
 361
 362                 clocks = <&cru PCLK_I2C3>;
 363                 clock-names = "i2c";
 364
 365                 status = "disabled";
 366         };
 367
 368         i2c4: i2c@2005e000 {
 369                 compatible = "rockchip,rk3066-i2c";
 370                 reg = <0x2005e000 0x1000>;
 371                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374
 375                 rockchip,grf = <&grf>;
 376
 377                 clocks = <&cru PCLK_I2C4>;
 378                 clock-names = "i2c";
 379
 380                 status = "disabled";
 381         };
 382
 383         uart2: serial@20064000 {
 384                 compatible = "snps,dw-apb-uart";
 385                 reg = <0x20064000 0x400>;
 386                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 387                 reg-shift = <2>;
 388                 reg-io-width = <1>;
 389                 clock-names = "baudclk", "apb_pclk";
 390                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 391                 status = "disabled";
 392         };
 393
 394         uart3: serial@20068000 {
 395                 compatible = "snps,dw-apb-uart";
 396                 reg = <0x20068000 0x400>;
 397                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 398                 reg-shift = <2>;
 399                 reg-io-width = <1>;
 400                 clock-names = "baudclk", "apb_pclk";
 401                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 402                 status = "disabled";
 403         };
 404
 405         saradc: saradc@2006c000 {
 406                 compatible = "rockchip,saradc";
 407                 reg = <0x2006c000 0x100>;
 408                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 409                 #io-channel-cells = <1>;
 410                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 411                 clock-names = "saradc", "apb_pclk";
 412                 resets = <&cru SRST_SARADC>;
 413                 reset-names = "saradc-apb";
 414                 status = "disabled";
 415         };
 416
 417         spi0: spi@20070000 {
 418                 compatible = "rockchip,rk3066-spi";
 419                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 420                 clock-names = "spiclk", "apb_pclk";
 421                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 422                 reg = <0x20070000 0x1000>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 dmas = <&dmac2 10>, <&dmac2 11>;
 426                 dma-names = "tx", "rx";
 427                 status = "disabled";
 428         };
 429
 430         spi1: spi@20074000 {
 431                 compatible = "rockchip,rk3066-spi";
 432                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 433                 clock-names = "spiclk", "apb_pclk";
 434                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 435                 reg = <0x20074000 0x1000>;
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 dmas = <&dmac2 12>, <&dmac2 13>;
 439                 dma-names = "tx", "rx";
 440                 status = "disabled";
 441         };
 442 };