arch/arm/boot/dts/rk3xxx.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include "skeleton.dtsi"
  47
  48 / {
  49         interrupt-parent = <&gic>;
  50
  51         aliases {
  52                 i2c0 = &i2c0;
  53                 i2c1 = &i2c1;
  54                 i2c2 = &i2c2;
  55                 i2c3 = &i2c3;
  56                 i2c4 = &i2c4;
  57                 mshc0 = &emmc;
  58                 mshc1 = &mmc0;
  59                 mshc2 = &mmc1;
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 serial3 = &uart3;
  64                 spi0 = &spi0;
  65                 spi1 = &spi1;
  66         };
  67
  68         amba {
  69                 compatible = "arm,amba-bus";
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72                 ranges;
  73
  74                 dmac1_s: dma-controller@20018000 {
  75                         compatible = "arm,pl330", "arm,primecell";
  76                         reg = <0x20018000 0x4000>;
  77                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  79                         #dma-cells = <1>;
  80                         arm,pl330-broken-no-flushp;
  81                         clocks = <&cru ACLK_DMA1>;
  82                         clock-names = "apb_pclk";
  83                 };
  84
  85                 dmac1_ns: dma-controller@2001c000 {
  86                         compatible = "arm,pl330", "arm,primecell";
  87                         reg = <0x2001c000 0x4000>;
  88                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  89                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  90                         #dma-cells = <1>;
  91                         arm,pl330-broken-no-flushp;
  92                         clocks = <&cru ACLK_DMA1>;
  93                         clock-names = "apb_pclk";
  94                         status = "disabled";
  95                 };
  96
  97                 dmac2: dma-controller@20078000 {
  98                         compatible = "arm,pl330", "arm,primecell";
  99                         reg = <0x20078000 0x4000>;
 100                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 101                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 102                         #dma-cells = <1>;
 103                         arm,pl330-broken-no-flushp;
 104                         clocks = <&cru ACLK_DMA2>;
 105                         clock-names = "apb_pclk";
 106                 };
 107         };
 108
 109         xin24m: oscillator {
 110                 compatible = "fixed-clock";
 111                 clock-frequency = <24000000>;
 112                 #clock-cells = <0>;
 113                 clock-output-names = "xin24m";
 114         };
 115
 116         L2: l2-cache-controller@10138000 {
 117                 compatible = "arm,pl310-cache";
 118                 reg = <0x10138000 0x1000>;
 119                 cache-unified;
 120                 cache-level = <2>;
 121         };
 122
 123         scu@1013c000 {
 124                 compatible = "arm,cortex-a9-scu";
 125                 reg = <0x1013c000 0x100>;
 126         };
 127
 128         global_timer: global-timer@1013c200 {
 129                 compatible = "arm,cortex-a9-global-timer";
 130                 reg = <0x1013c200 0x20>;
 131                 interrupts = <GIC_PPI 11 0x304>;
 132                 clocks = <&cru CORE_PERI>;
 133         };
 134
 135         local_timer: local-timer@1013c600 {
 136                 compatible = "arm,cortex-a9-twd-timer";
 137                 reg = <0x1013c600 0x20>;
 138                 interrupts = <GIC_PPI 13 0x304>;
 139                 clocks = <&cru CORE_PERI>;
 140         };
 141
 142         gic: interrupt-controller@1013d000 {
 143                 compatible = "arm,cortex-a9-gic";
 144                 interrupt-controller;
 145                 #interrupt-cells = <3>;
 146                 reg = <0x1013d000 0x1000>,
 147                       <0x1013c100 0x0100>;
 148         };
 149
 150         uart0: serial@10124000 {
 151                 compatible = "snps,dw-apb-uart";
 152                 reg = <0x10124000 0x400>;
 153                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 154                 reg-shift = <2>;
 155                 reg-io-width = <1>;
 156                 clock-names = "baudclk", "apb_pclk";
 157                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 158                 status = "disabled";
 159         };
 160
 161         uart1: serial@10126000 {
 162                 compatible = "snps,dw-apb-uart";
 163                 reg = <0x10126000 0x400>;
 164                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 165                 reg-shift = <2>;
 166                 reg-io-width = <1>;
 167                 clock-names = "baudclk", "apb_pclk";
 168                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 169                 status = "disabled";
 170         };
 171
 172         usb_otg: usb@10180000 {
 173                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 174                 reg = <0x10180000 0x40000>;
 175                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru HCLK_OTG0>;
 177                 clock-names = "otg";
 178                 dr_mode = "otg";
 179                 g-np-tx-fifo-size = <16>;
 180                 g-rx-fifo-size = <275>;
 181                 g-tx-fifo-size = <256 128 128 64 64 32>;
 182                 g-use-dma;
 183                 phys = <&usbphy0>;
 184                 phy-names = "usb2-phy";
 185                 status = "disabled";
 186         };
 187
 188         usb_host: usb@101c0000 {
 189                 compatible = "snps,dwc2";
 190                 reg = <0x101c0000 0x40000>;
 191                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&cru HCLK_OTG1>;
 193                 clock-names = "otg";
 194                 dr_mode = "host";
 195                 phys = <&usbphy1>;
 196                 phy-names = "usb2-phy";
 197                 status = "disabled";
 198         };
 199
 200         emac: ethernet@10204000 {
 201                 compatible = "snps,arc-emac";
 202                 reg = <0x10204000 0x3c>;
 203                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 204                 #address-cells = <1>;
 205                 #size-cells = <0>;
 206
 207                 rockchip,grf = <&grf>;
 208
 209                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 210                 clock-names = "hclk", "macref";
 211                 max-speed = <100>;
 212                 phy-mode = "rmii";
 213
 214                 status = "disabled";
 215         };
 216
 217         mmc0: dwmmc@10214000 {
 218                 compatible = "rockchip,rk2928-dw-mshc";
 219                 reg = <0x10214000 0x1000>;
 220                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 222                 clock-names = "biu", "ciu";
 223                 fifo-depth = <256>;
 224                 status = "disabled";
 225         };
 226
 227         mmc1: dwmmc@10218000 {
 228                 compatible = "rockchip,rk2928-dw-mshc";
 229                 reg = <0x10218000 0x1000>;
 230                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 231                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 232                 clock-names = "biu", "ciu";
 233                 fifo-depth = <256>;
 234                 status = "disabled";
 235         };
 236
 237         emmc: dwmmc@1021c000 {
 238                 compatible = "rockchip,rk2928-dw-mshc";
 239                 reg = <0x1021c000 0x1000>;
 240                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 242                 clock-names = "biu", "ciu";
 243                 fifo-depth = <256>;
 244                 status = "disabled";
 245         };
 246
 247         pmu: pmu@20004000 {
 248                 compatible = "rockchip,rk3066-pmu", "syscon";
 249                 reg = <0x20004000 0x100>;
 250         };
 251
 252         grf: grf@20008000 {
 253                 compatible = "syscon";
 254                 reg = <0x20008000 0x200>;
 255         };
 256
 257         i2c0: i2c@2002d000 {
 258                 compatible = "rockchip,rk3066-i2c";
 259                 reg = <0x2002d000 0x1000>;
 260                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263
 264                 rockchip,grf = <&grf>;
 265
 266                 clock-names = "i2c";
 267                 clocks = <&cru PCLK_I2C0>;
 268
 269                 status = "disabled";
 270         };
 271
 272         i2c1: i2c@2002f000 {
 273                 compatible = "rockchip,rk3066-i2c";
 274                 reg = <0x2002f000 0x1000>;
 275                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278
 279                 rockchip,grf = <&grf>;
 280
 281                 clocks = <&cru PCLK_I2C1>;
 282                 clock-names = "i2c";
 283
 284                 status = "disabled";
 285         };
 286
 287         pwm0: pwm@20030000 {
 288                 compatible = "rockchip,rk2928-pwm";
 289                 reg = <0x20030000 0x10>;
 290                 #pwm-cells = <2>;
 291                 clocks = <&cru PCLK_PWM01>;
 292                 status = "disabled";
 293         };
 294
 295         pwm1: pwm@20030010 {
 296                 compatible = "rockchip,rk2928-pwm";
 297                 reg = <0x20030010 0x10>;
 298                 #pwm-cells = <2>;
 299                 clocks = <&cru PCLK_PWM01>;
 300                 status = "disabled";
 301         };
 302
 303         wdt: watchdog@2004c000 {
 304                 compatible = "snps,dw-wdt";
 305                 reg = <0x2004c000 0x100>;
 306                 clocks = <&cru PCLK_WDT>;
 307                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 308                 status = "disabled";
 309         };
 310
 311         pwm2: pwm@20050020 {
 312                 compatible = "rockchip,rk2928-pwm";
 313                 reg = <0x20050020 0x10>;
 314                 #pwm-cells = <2>;
 315                 clocks = <&cru PCLK_PWM23>;
 316                 status = "disabled";
 317         };
 318
 319         pwm3: pwm@20050030 {
 320                 compatible = "rockchip,rk2928-pwm";
 321                 reg = <0x20050030 0x10>;
 322                 #pwm-cells = <2>;
 323                 clocks = <&cru PCLK_PWM23>;
 324                 status = "disabled";
 325         };
 326
 327         i2c2: i2c@20056000 {
 328                 compatible = "rockchip,rk3066-i2c";
 329                 reg = <0x20056000 0x1000>;
 330                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333
 334                 rockchip,grf = <&grf>;
 335
 336                 clocks = <&cru PCLK_I2C2>;
 337                 clock-names = "i2c";
 338
 339                 status = "disabled";
 340         };
 341
 342         i2c3: i2c@2005a000 {
 343                 compatible = "rockchip,rk3066-i2c";
 344                 reg = <0x2005a000 0x1000>;
 345                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348
 349                 rockchip,grf = <&grf>;
 350
 351                 clocks = <&cru PCLK_I2C3>;
 352                 clock-names = "i2c";
 353
 354                 status = "disabled";
 355         };
 356
 357         i2c4: i2c@2005e000 {
 358                 compatible = "rockchip,rk3066-i2c";
 359                 reg = <0x2005e000 0x1000>;
 360                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363
 364                 rockchip,grf = <&grf>;
 365
 366                 clocks = <&cru PCLK_I2C4>;
 367                 clock-names = "i2c";
 368
 369                 status = "disabled";
 370         };
 371
 372         uart2: serial@20064000 {
 373                 compatible = "snps,dw-apb-uart";
 374                 reg = <0x20064000 0x400>;
 375                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 376                 reg-shift = <2>;
 377                 reg-io-width = <1>;
 378                 clock-names = "baudclk", "apb_pclk";
 379                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 380                 status = "disabled";
 381         };
 382
 383         uart3: serial@20068000 {
 384                 compatible = "snps,dw-apb-uart";
 385                 reg = <0x20068000 0x400>;
 386                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 387                 reg-shift = <2>;
 388                 reg-io-width = <1>;
 389                 clock-names = "baudclk", "apb_pclk";
 390                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 391                 status = "disabled";
 392         };
 393
 394         saradc: saradc@2006c000 {
 395                 compatible = "rockchip,saradc";
 396                 reg = <0x2006c000 0x100>;
 397                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 398                 #io-channel-cells = <1>;
 399                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 400                 clock-names = "saradc", "apb_pclk";
 401                 status = "disabled";
 402         };
 403
 404         spi0: spi@20070000 {
 405                 compatible = "rockchip,rk3066-spi";
 406                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 407                 clock-names = "spiclk", "apb_pclk";
 408                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 409                 reg = <0x20070000 0x1000>;
 410                 #address-cells = <1>;
 411                 #size-cells = <0>;
 412                 dmas = <&dmac2 10>, <&dmac2 11>;
 413                 dma-names = "tx", "rx";
 414                 status = "disabled";
 415         };
 416
 417         spi1: spi@20074000 {
 418                 compatible = "rockchip,rk3066-spi";
 419                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 420                 clock-names = "spiclk", "apb_pclk";
 421                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 422                 reg = <0x20074000 0x1000>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 dmas = <&dmac2 12>, <&dmac2 13>;
 426                 dma-names = "tx", "rx";
 427                 status = "disabled";
 428         };
 429 };