arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 mshc0 = &emmc;
  65                 mshc1 = &sdmmc;
  66                 mshc2 = &sdio0;
  67                 mshc3 = &sdio1;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73                 spi0 = &spi0;
  74                 spi1 = &spi1;
  75                 spi2 = &spi2;
  76         };
  77
  78         arm-pmu {
  79                 compatible = "arm,cortex-a12-pmu";
  80                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  84                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  85         };
  86
  87         cpus {
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 enable-method = "rockchip,rk3066-smp";
  91                 rockchip,pmu = <&pmu>;
  92
  93                 cpu0: cpu@500 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a12";
  96                         reg = <0x500>;
  97                         resets = <&cru SRST_CORE0>;
  98                         operating-points-v2 = <&cpu0_opp_table>;
  99                         #cooling-cells = <2>; /* min followed by max */
 100                         clocks = <&cru ARMCLK>;
 101                 };
 102                 cpu1: cpu@501 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a12";
 105                         reg = <0x501>;
 106                         resets = <&cru SRST_CORE1>;
 107                         operating-points-v2 = <&cpu0_opp_table>;
 108                 };
 109                 cpu2: cpu@502 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a12";
 112                         reg = <0x502>;
 113                         resets = <&cru SRST_CORE2>;
 114                         operating-points-v2 = <&cpu0_opp_table>;
 115                 };
 116                 cpu3: cpu@503 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x503>;
 120                         resets = <&cru SRST_CORE3>;
 121                         operating-points-v2 = <&cpu0_opp_table>;
 122                 };
 123         };
 124
 125         cpu0_opp_table: opp_table0 {
 126                 compatible = "operating-points-v2";
 127                 opp-shared;
 128
 129                 opp@126000000 {
 130                         opp-hz = /bits/ 64 <126000000>;
 131                         opp-microvolt = <900000>;
 132                         clock-latency-ns = <40000>;
 133                 };
 134                 opp@216000000 {
 135                         opp-hz = /bits/ 64 <216000000>;
 136                         opp-microvolt = <900000>;
 137                         clock-latency-ns = <40000>;
 138                 };
 139                 opp@408000000 {
 140                         opp-hz = /bits/ 64 <408000000>;
 141                         opp-microvolt = <900000>;
 142                         clock-latency-ns = <40000>;
 143                 };
 144                 opp@600000000 {
 145                         opp-hz = /bits/ 64 <600000000>;
 146                         opp-microvolt = <900000>;
 147                         clock-latency-ns = <40000>;
 148                 };
 149                 opp@696000000 {
 150                         opp-hz = /bits/ 64 <696000000>;
 151                         opp-microvolt = <950000>;
 152                         clock-latency-ns = <40000>;
 153                 };
 154                 opp@816000000 {
 155                         opp-hz = /bits/ 64 <816000000>;
 156                         opp-microvolt = <1000000>;
 157                         clock-latency-ns = <40000>;
 158                         opp-suspend;
 159                 };
 160                 opp@1008000000 {
 161                         opp-hz = /bits/ 64 <1008000000>;
 162                         opp-microvolt = <1050000>;
 163                         clock-latency-ns = <40000>;
 164                 };
 165                 opp@1200000000 {
 166                         opp-hz = /bits/ 64 <1200000000>;
 167                         opp-microvolt = <1100000>;
 168                         clock-latency-ns = <40000>;
 169                 };
 170                 opp@1416000000 {
 171                         opp-hz = /bits/ 64 <1416000000>;
 172                         opp-microvolt = <1200000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp@1512000000 {
 176                         opp-hz = /bits/ 64 <1512000000>;
 177                         opp-microvolt = <1300000>;
 178                         clock-latency-ns = <40000>;
 179                 };
 180                 opp@1608000000 {
 181                         opp-hz = /bits/ 64 <1608000000>;
 182                         opp-microvolt = <1350000>;
 183                         clock-latency-ns = <40000>;
 184                 };
 185         };
 186
 187         cpu_avs: cpu-avs {
 188                 cluster0-avs {
 189                         cluster-id = <0>;
 190                         min-volt = <900000>; /* uV */
 191                         min-freq = <126000>; /* KHz */
 192                         leakage-adjust-volt = <
 193                         /*  mA        mA         uV */
 194                             0         254        0
 195                         >;
 196                         nvmem-cells = <&cpu_leakage>;
 197                         nvmem-cell-names = "cpu_leakage";
 198                 };
 199         };
 200
 201         amba {
 202                 compatible = "arm,amba-bus";
 203                 #address-cells = <1>;
 204                 #size-cells = <1>;
 205                 ranges;
 206
 207                 dmac_peri: dma-controller@ff250000 {
 208                         compatible = "arm,pl330", "arm,primecell";
 209                         reg = <0xff250000 0x4000>;
 210                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 212                         #dma-cells = <1>;
 213                         arm,pl330-broken-no-flushp;
 214                         peripherals-req-type-burst;
 215                         clocks = <&cru ACLK_DMAC2>;
 216                         clock-names = "apb_pclk";
 217                 };
 218
 219                 dmac_bus_ns: dma-controller@ff600000 {
 220                         compatible = "arm,pl330", "arm,primecell";
 221                         reg = <0xff600000 0x4000>;
 222                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 224                         #dma-cells = <1>;
 225                         arm,pl330-broken-no-flushp;
 226                         peripherals-req-type-burst;
 227                         clocks = <&cru ACLK_DMAC1>;
 228                         clock-names = "apb_pclk";
 229                         status = "disabled";
 230                 };
 231
 232                 dmac_bus_s: dma-controller@ffb20000 {
 233                         compatible = "arm,pl330", "arm,primecell";
 234                         reg = <0xffb20000 0x4000>;
 235                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 237                         #dma-cells = <1>;
 238                         arm,pl330-broken-no-flushp;
 239                         peripherals-req-type-burst;
 240                         clocks = <&cru ACLK_DMAC1>;
 241                         clock-names = "apb_pclk";
 242                 };
 243         };
 244
 245         reserved-memory {
 246                 #address-cells = <1>;
 247                 #size-cells = <1>;
 248                 ranges;
 249
 250                 /*
 251                  * The rk3288 cannot use the memory area above 0xfe000000
 252                  * for dma operations for some reason. While there is
 253                  * probably a better solution available somewhere, we
 254                  * haven't found it yet and while devices with 2GB of ram
 255                  * are not affected, this issue prevents 4GB from booting.
 256                  * So to make these devices at least bootable, block
 257                  * this area for the time being until the real solution
 258                  * is found.
 259                  */
 260                 dma-unusable@fe000000 {
 261                         reg = <0xfe000000 0x1000000>;
 262                 };
 263         };
 264
 265         xin24m: oscillator {
 266                 compatible = "fixed-clock";
 267                 clock-frequency = <24000000>;
 268                 clock-output-names = "xin24m";
 269                 #clock-cells = <0>;
 270         };
 271
 272         timer {
 273                 compatible = "arm,armv7-timer";
 274                 arm,cpu-registers-not-fw-configured;
 275                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 276                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 277                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 278                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 279                 clock-frequency = <24000000>;
 280         };
 281
 282         timer: timer@ff810000 {
 283                 compatible = "rockchip,rk3288-timer";
 284                 reg = <0xff810000 0x20>;
 285                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 287                 clock-names = "timer", "pclk";
 288         };
 289
 290         display-subsystem {
 291                 compatible = "rockchip,display-subsystem";
 292                 ports = <&vopl_out>, <&vopb_out>;
 293         };
 294
 295         sdmmc: dwmmc@ff0c0000 {
 296                 compatible = "rockchip,rk3288-dw-mshc";
 297                 clock-freq-min-max = <400000 150000000>;
 298                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 299                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 300                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 301                 fifo-depth = <0x100>;
 302                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 303                 reg = <0xff0c0000 0x4000>;
 304                 status = "disabled";
 305         };
 306
 307         sdio0: dwmmc@ff0d0000 {
 308                 compatible = "rockchip,rk3288-dw-mshc";
 309                 clock-freq-min-max = <400000 150000000>;
 310                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 311                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 312                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 313                 fifo-depth = <0x100>;
 314                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 315                 reg = <0xff0d0000 0x4000>;
 316                 status = "disabled";
 317         };
 318
 319         sdio1: dwmmc@ff0e0000 {
 320                 compatible = "rockchip,rk3288-dw-mshc";
 321                 clock-freq-min-max = <400000 150000000>;
 322                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 323                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 324                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 325                 fifo-depth = <0x100>;
 326                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 327                 reg = <0xff0e0000 0x4000>;
 328                 status = "disabled";
 329         };
 330
 331         emmc: dwmmc@ff0f0000 {
 332                 compatible = "rockchip,rk3288-dw-mshc";
 333                 clock-freq-min-max = <400000 150000000>;
 334                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 335                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 336                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 337                 fifo-depth = <0x100>;
 338                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 339                 reg = <0xff0f0000 0x4000>;
 340                 status = "disabled";
 341                 supports-emmc;
 342         };
 343
 344         saradc: saradc@ff100000 {
 345                 compatible = "rockchip,saradc";
 346                 reg = <0xff100000 0x100>;
 347                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 348                 #io-channel-cells = <1>;
 349                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 350                 clock-names = "saradc", "apb_pclk";
 351                 resets = <&cru SRST_SARADC>;
 352                 reset-names = "saradc-apb";
 353                 status = "disabled";
 354         };
 355
 356         spi0: spi@ff110000 {
 357                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 358                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 359                 clock-names = "spiclk", "apb_pclk";
 360                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 361                 dma-names = "tx", "rx";
 362                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 365                 reg = <0xff110000 0x1000>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 status = "disabled";
 369         };
 370
 371         spi1: spi@ff120000 {
 372                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 373                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 374                 clock-names = "spiclk", "apb_pclk";
 375                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 376                 dma-names = "tx", "rx";
 377                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 378                 pinctrl-names = "default";
 379                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 380                 reg = <0xff120000 0x1000>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 status = "disabled";
 384         };
 385
 386         spi2: spi@ff130000 {
 387                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 388                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 389                 clock-names = "spiclk", "apb_pclk";
 390                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 391                 dma-names = "tx", "rx";
 392                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 395                 reg = <0xff130000 0x1000>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 status = "disabled";
 399         };
 400
 401         i2c1: i2c@ff140000 {
 402                 compatible = "rockchip,rk3288-i2c";
 403                 reg = <0xff140000 0x1000>;
 404                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 clock-names = "i2c";
 408                 clocks = <&cru PCLK_I2C1>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&i2c1_xfer>;
 411                 status = "disabled";
 412         };
 413
 414         i2c3: i2c@ff150000 {
 415                 compatible = "rockchip,rk3288-i2c";
 416                 reg = <0xff150000 0x1000>;
 417                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 clock-names = "i2c";
 421                 clocks = <&cru PCLK_I2C3>;
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&i2c3_xfer>;
 424                 status = "disabled";
 425         };
 426
 427         i2c4: i2c@ff160000 {
 428                 compatible = "rockchip,rk3288-i2c";
 429                 reg = <0xff160000 0x1000>;
 430                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 431                 #address-cells = <1>;
 432                 #size-cells = <0>;
 433                 clock-names = "i2c";
 434                 clocks = <&cru PCLK_I2C4>;
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&i2c4_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         i2c5: i2c@ff170000 {
 441                 compatible = "rockchip,rk3288-i2c";
 442                 reg = <0xff170000 0x1000>;
 443                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 clock-names = "i2c";
 447                 clocks = <&cru PCLK_I2C5>;
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&i2c5_xfer>;
 450                 status = "disabled";
 451         };
 452
 453         uart0: serial@ff180000 {
 454                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 455                 reg = <0xff180000 0x100>;
 456                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 457                 reg-shift = <2>;
 458                 reg-io-width = <4>;
 459                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 460                 clock-names = "baudclk", "apb_pclk";
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&uart0_xfer>;
 463                 status = "disabled";
 464         };
 465
 466         uart1: serial@ff190000 {
 467                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 468                 reg = <0xff190000 0x100>;
 469                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 470                 reg-shift = <2>;
 471                 reg-io-width = <4>;
 472                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 473                 clock-names = "baudclk", "apb_pclk";
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&uart1_xfer>;
 476                 status = "disabled";
 477         };
 478
 479         uart2: serial@ff690000 {
 480                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 481                 reg = <0xff690000 0x100>;
 482                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 483                 reg-shift = <2>;
 484                 reg-io-width = <4>;
 485                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 486                 clock-names = "baudclk", "apb_pclk";
 487                 pinctrl-names = "default";
 488                 pinctrl-0 = <&uart2_xfer>;
 489                 status = "disabled";
 490         };
 491
 492         uart3: serial@ff1b0000 {
 493                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 494                 reg = <0xff1b0000 0x100>;
 495                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 496                 reg-shift = <2>;
 497                 reg-io-width = <4>;
 498                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 499                 clock-names = "baudclk", "apb_pclk";
 500                 pinctrl-names = "default";
 501                 pinctrl-0 = <&uart3_xfer>;
 502                 status = "disabled";
 503         };
 504
 505         uart4: serial@ff1c0000 {
 506                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 507                 reg = <0xff1c0000 0x100>;
 508                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 509                 reg-shift = <2>;
 510                 reg-io-width = <4>;
 511                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 512                 clock-names = "baudclk", "apb_pclk";
 513                 pinctrl-names = "default";
 514                 pinctrl-0 = <&uart4_xfer>;
 515                 status = "disabled";
 516         };
 517
 518         thermal-zones {
 519                 reserve_thermal: reserve_thermal {
 520                         polling-delay-passive = <1000>; /* milliseconds */
 521                         polling-delay = <5000>; /* milliseconds */
 522
 523                         thermal-sensors = <&tsadc 0>;
 524                 };
 525
 526                 cpu_thermal: cpu_thermal {
 527                         polling-delay-passive = <250>; /* milliseconds */
 528                         polling-delay = <5000>; /* milliseconds */
 529
 530                         thermal-sensors = <&tsadc 1>;
 531
 532                         trips {
 533                                 cpu_alert0: cpu_alert0 {
 534                                         temperature = <70000>; /* millicelsius */
 535                                         hysteresis = <2000>; /* millicelsius */
 536                                         type = "passive";
 537                                 };
 538                                 cpu_alert1: cpu_alert1 {
 539                                         temperature = <80000>; /* millicelsius */
 540                                         hysteresis = <2000>; /* millicelsius */
 541                                         type = "passive";
 542                                 };
 543                                 cpu_crit: cpu_crit {
 544                                         temperature = <90000>; /* millicelsius */
 545                                         hysteresis = <2000>; /* millicelsius */
 546                                         type = "critical";
 547                                 };
 548                         };
 549
 550                         cooling-maps {
 551                                 map0 {
 552                                         trip = <&cpu_alert0>;
 553                                         cooling-device =
 554                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 555                                 };
 556                                 map1 {
 557                                         trip = <&cpu_alert1>;
 558                                         cooling-device =
 559                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 560                                 };
 561                         };
 562                 };
 563
 564                 gpu_thermal: gpu_thermal {
 565                         polling-delay-passive = <250>; /* milliseconds */
 566                         polling-delay = <5000>; /* milliseconds */
 567
 568                         thermal-sensors = <&tsadc 2>;
 569
 570                         trips {
 571                                 gpu_alert0: gpu_alert0 {
 572                                         temperature = <80000>; /* millicelsius */
 573                                         hysteresis = <2000>; /* millicelsius */
 574                                         type = "passive";
 575                                 };
 576                                 gpu_crit: gpu_crit {
 577                                         temperature = <90000>; /* millicelsius */
 578                                         hysteresis = <2000>; /* millicelsius */
 579                                         type = "critical";
 580                                 };
 581                         };
 582
 583                         cooling-maps {
 584                                 map0 {
 585                                         trip = <&gpu_alert0>;
 586                                         cooling-device =
 587                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 588                                 };
 589                         };
 590                 };
 591         };
 592
 593         tsadc: tsadc@ff280000 {
 594                 compatible = "rockchip,rk3288-tsadc";
 595                 reg = <0xff280000 0x100>;
 596                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 597                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 598                 clock-names = "tsadc", "apb_pclk";
 599                 resets = <&cru SRST_TSADC>;
 600                 reset-names = "tsadc-apb";
 601                 pinctrl-names = "init", "default", "sleep";
 602                 pinctrl-0 = <&otp_gpio>;
 603                 pinctrl-1 = <&otp_out>;
 604                 pinctrl-2 = <&otp_gpio>;
 605                 #thermal-sensor-cells = <1>;
 606                 rockchip,hw-tshut-temp = <95000>;
 607                 status = "disabled";
 608         };
 609
 610         gmac: ethernet@ff290000 {
 611                 compatible = "rockchip,rk3288-gmac";
 612                 reg = <0xff290000 0x10000>;
 613                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 614                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 615                 interrupt-names = "macirq", "eth_wake_irq";
 616                 rockchip,grf = <&grf>;
 617                 clocks = <&cru SCLK_MAC>,
 618                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 619                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 620                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 621                 clock-names = "stmmaceth",
 622                         "mac_clk_rx", "mac_clk_tx",
 623                         "clk_mac_ref", "clk_mac_refout",
 624                         "aclk_mac", "pclk_mac";
 625                 resets = <&cru SRST_MAC>;
 626                 reset-names = "stmmaceth";
 627                 max-speed = <100>;
 628                 status = "disabled";
 629         };
 630
 631         usb_host0_ehci: usb@ff500000 {
 632                 compatible = "generic-ehci";
 633                 reg = <0xff500000 0x100>;
 634                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&cru HCLK_USBHOST0>;
 636                 clock-names = "usbhost";
 637                 phys = <&usbphy1>;
 638                 phy-names = "usb";
 639                 status = "disabled";
 640         };
 641
 642         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 643
 644         usb_host1: usb@ff540000 {
 645                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 646                                 "snps,dwc2";
 647                 reg = <0xff540000 0x40000>;
 648                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&cru HCLK_USBHOST1>;
 650                 clock-names = "otg";
 651                 dr_mode = "host";
 652                 phys = <&usbphy2>;
 653                 phy-names = "usb2-phy";
 654                 status = "disabled";
 655         };
 656
 657         usb_otg: usb@ff580000 {
 658                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 659                                 "snps,dwc2";
 660                 reg = <0xff580000 0x40000>;
 661                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&cru HCLK_OTG0>;
 663                 clock-names = "otg";
 664                 dr_mode = "otg";
 665                 g-np-tx-fifo-size = <16>;
 666                 g-rx-fifo-size = <275>;
 667                 g-tx-fifo-size = <256 128 128 64 64 32>;
 668                 g-use-dma;
 669                 phys = <&usbphy0>;
 670                 phy-names = "usb2-phy";
 671                 status = "disabled";
 672         };
 673
 674         usb_hsic: usb@ff5c0000 {
 675                 compatible = "generic-ehci";
 676                 reg = <0xff5c0000 0x100>;
 677                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&cru HCLK_HSIC>;
 679                 clock-names = "usbhost";
 680                 status = "disabled";
 681         };
 682
 683         dmc: dmc@ff610000 {
 684                 compatible = "rockchip,rk3288-dmc", "syscon";
 685                 rockchip,cru = <&cru>;
 686                 rockchip,grf = <&grf>;
 687                 rockchip,pmu = <&pmu>;
 688                 rockchip,sgrf = <&sgrf>;
 689                 rockchip,noc = <&noc>;
 690                 reg = <0xff610000 0x3fc
 691                        0xff620000 0x294
 692                        0xff630000 0x3fc
 693                        0xff640000 0x294>;
 694                 rockchip,sram = <&ddr_sram>;
 695                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 696                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 697                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 698                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 699                               "pclk_ddrupctl1", "pclk_publ1",
 700                               "arm_clk", "aclk_dmac1";
 701         };
 702
 703         i2c0: i2c@ff650000 {
 704                 compatible = "rockchip,rk3288-i2c";
 705                 reg = <0xff650000 0x1000>;
 706                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 707                 #address-cells = <1>;
 708                 #size-cells = <0>;
 709                 clock-names = "i2c";
 710                 clocks = <&cru PCLK_I2C0>;
 711                 pinctrl-names = "default";
 712                 pinctrl-0 = <&i2c0_xfer>;
 713                 status = "disabled";
 714         };
 715
 716         i2c2: i2c@ff660000 {
 717                 compatible = "rockchip,rk3288-i2c";
 718                 reg = <0xff660000 0x1000>;
 719                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 720                 #address-cells = <1>;
 721                 #size-cells = <0>;
 722                 clock-names = "i2c";
 723                 clocks = <&cru PCLK_I2C2>;
 724                 pinctrl-names = "default";
 725                 pinctrl-0 = <&i2c2_xfer>;
 726                 status = "disabled";
 727         };
 728
 729         pwm0: pwm@ff680000 {
 730                 compatible = "rockchip,rk3288-pwm";
 731                 reg = <0xff680000 0x10>;
 732                 #pwm-cells = <3>;
 733                 pinctrl-names = "default";
 734                 pinctrl-0 = <&pwm0_pin>;
 735                 clocks = <&cru PCLK_PWM>;
 736                 clock-names = "pwm";
 737                 status = "disabled";
 738         };
 739
 740         pwm1: pwm@ff680010 {
 741                 compatible = "rockchip,rk3288-pwm";
 742                 reg = <0xff680010 0x10>;
 743                 #pwm-cells = <3>;
 744                 pinctrl-names = "default";
 745                 pinctrl-0 = <&pwm1_pin>;
 746                 clocks = <&cru PCLK_PWM>;
 747                 clock-names = "pwm";
 748                 status = "disabled";
 749         };
 750
 751         pwm2: pwm@ff680020 {
 752                 compatible = "rockchip,rk3288-pwm";
 753                 reg = <0xff680020 0x10>;
 754                 #pwm-cells = <3>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&pwm2_pin>;
 757                 clocks = <&cru PCLK_PWM>;
 758                 clock-names = "pwm";
 759                 status = "disabled";
 760         };
 761
 762         pwm3: pwm@ff680030 {
 763                 compatible = "rockchip,rk3288-pwm";
 764                 reg = <0xff680030 0x10>;
 765                 #pwm-cells = <2>;
 766                 pinctrl-names = "default";
 767                 pinctrl-0 = <&pwm3_pin>;
 768                 clocks = <&cru PCLK_PWM>;
 769                 clock-names = "pwm";
 770                 status = "disabled";
 771         };
 772
 773         bus_intmem@ff700000 {
 774                 compatible = "mmio-sram";
 775                 reg = <0xff700000 0x18000>;
 776                 #address-cells = <1>;
 777                 #size-cells = <1>;
 778                 ranges = <0 0xff700000 0x18000>;
 779                 smp-sram@0 {
 780                         compatible = "rockchip,rk3066-smp-sram";
 781                         reg = <0x00 0x10>;
 782                 };
 783                 ddr_sram: ddr-sram@1000 {
 784                         compatible = "rockchip,rk3288-ddr-sram";
 785                         reg = <0x1000 0x4000>;
 786                 };
 787         };
 788
 789         sram@ff720000 {
 790                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 791                 reg = <0xff720000 0x1000>;
 792         };
 793
 794         qos_gpu_r: qos@ffaa0000 {
 795                 compatible = "syscon";
 796                 reg = <0xffaa0000 0x20>;
 797         };
 798
 799         qos_gpu_w: qos@ffaa0080 {
 800                 compatible = "syscon";
 801                 reg = <0xffaa0080 0x20>;
 802         };
 803
 804         qos_vio1_vop: qos@ffad0000 {
 805                 compatible = "syscon";
 806                 reg = <0xffad0000 0x20>;
 807         };
 808
 809         qos_vio1_isp_w0: qos@ffad0100 {
 810                 compatible = "syscon";
 811                 reg = <0xffad0100 0x20>;
 812         };
 813
 814         qos_vio1_isp_w1: qos@ffad0180 {
 815                 compatible = "syscon";
 816                 reg = <0xffad0180 0x20>;
 817         };
 818
 819         qos_vio0_vop: qos@ffad0400 {
 820                 compatible = "syscon";
 821                 reg = <0xffad0400 0x20>;
 822         };
 823
 824         qos_vio0_vip: qos@ffad0480 {
 825                 compatible = "syscon";
 826                 reg = <0xffad0480 0x20>;
 827         };
 828
 829         qos_vio0_iep: qos@ffad0500 {
 830                 compatible = "syscon";
 831                 reg = <0xffad0500 0x20>;
 832         };
 833
 834         qos_vio2_rga_r: qos@ffad0800 {
 835                 compatible = "syscon";
 836                 reg = <0xffad0800 0x20>;
 837         };
 838
 839         qos_vio2_rga_w: qos@ffad0880 {
 840                 compatible = "syscon";
 841                 reg = <0xffad0880 0x20>;
 842         };
 843
 844         qos_vio1_isp_r: qos@ffad0900 {
 845                 compatible = "syscon";
 846                 reg = <0xffad0900 0x20>;
 847         };
 848
 849         qos_video: qos@ffae0000 {
 850                 compatible = "syscon";
 851                 reg = <0xffae0000 0x20>;
 852         };
 853
 854         qos_hevc_r: qos@ffaf0000 {
 855                 compatible = "syscon";
 856                 reg = <0xffaf0000 0x20>;
 857         };
 858
 859         qos_hevc_w: qos@ffaf0080 {
 860                 compatible = "syscon";
 861                 reg = <0xffaf0080 0x20>;
 862         };
 863
 864         pmu: power-management@ff730000 {
 865                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 866                 reg = <0xff730000 0x100>;
 867
 868                 power: power-controller {
 869                         compatible = "rockchip,rk3288-power-controller";
 870                         #power-domain-cells = <1>;
 871                         #address-cells = <1>;
 872                         #size-cells = <0>;
 873
 874                         /*
 875                          * Note: Although SCLK_* are the working clocks
 876                          * of device without including on the NOC, needed for
 877                          * synchronous reset.
 878                          *
 879                          * The clocks on the which NOC:
 880                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 881                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 882                          * ACLK_RGA is on ACLK_RGA_NIU.
 883                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 884                          *
 885                          * Which clock are device clocks:
 886                          *      clocks          devices
 887                          *      *_IEP           IEP:Image Enhancement Processor
 888                          *      *_ISP           ISP:Image Signal Processing
 889                          *      *_VIP           VIP:Video Input Processor
 890                          *      *_VOP*          VOP:Visual Output Processor
 891                          *      *_RGA           RGA
 892                          *      *_EDP*          EDP
 893                          *      *_LVDS_*        LVDS
 894                          *      *_HDMI          HDMI
 895                          *      *_MIPI_*        MIPI
 896                          */
 897                         pd_vio@RK3288_PD_VIO {
 898                                 reg = <RK3288_PD_VIO>;
 899                                 clocks = <&cru ACLK_IEP>,
 900                                          <&cru ACLK_ISP>,
 901                                          <&cru ACLK_RGA>,
 902                                          <&cru ACLK_VIP>,
 903                                          <&cru ACLK_VOP0>,
 904                                          <&cru ACLK_VOP1>,
 905                                          <&cru DCLK_VOP0>,
 906                                          <&cru DCLK_VOP1>,
 907                                          <&cru HCLK_IEP>,
 908                                          <&cru HCLK_ISP>,
 909                                          <&cru HCLK_RGA>,
 910                                          <&cru HCLK_VIP>,
 911                                          <&cru HCLK_VOP0>,
 912                                          <&cru HCLK_VOP1>,
 913                                          <&cru PCLK_EDP_CTRL>,
 914                                          <&cru PCLK_HDMI_CTRL>,
 915                                          <&cru PCLK_LVDS_PHY>,
 916                                          <&cru PCLK_MIPI_CSI>,
 917                                          <&cru PCLK_MIPI_DSI0>,
 918                                          <&cru PCLK_MIPI_DSI1>,
 919                                          <&cru SCLK_EDP_24M>,
 920                                          <&cru SCLK_EDP>,
 921                                          <&cru SCLK_ISP_JPE>,
 922                                          <&cru SCLK_ISP>,
 923                                          <&cru SCLK_RGA>;
 924                                 pm_qos = <&qos_vio0_iep>,
 925                                          <&qos_vio1_vop>,
 926                                          <&qos_vio1_isp_w0>,
 927                                          <&qos_vio1_isp_w1>,
 928                                          <&qos_vio0_vop>,
 929                                          <&qos_vio0_vip>,
 930                                          <&qos_vio2_rga_r>,
 931                                          <&qos_vio2_rga_w>,
 932                                          <&qos_vio1_isp_r>;
 933                         };
 934
 935                         /*
 936                          * Note: The following 3 are HEVC(H.265) clocks,
 937                          * and on the ACLK_HEVC_NIU (NOC).
 938                          */
 939                         pd_hevc@RK3288_PD_HEVC {
 940                                 reg = <RK3288_PD_HEVC>;
 941                                 clocks = <&cru ACLK_HEVC>,
 942                                          <&cru SCLK_HEVC_CABAC>,
 943                                          <&cru SCLK_HEVC_CORE>;
 944                                 pm_qos = <&qos_hevc_r>,
 945                                          <&qos_hevc_w>;
 946                         };
 947
 948                         /*
 949                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 950                          * (video endecoder & decoder) clocks that on the
 951                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 952                          */
 953                         pd_video@RK3288_PD_VIDEO {
 954                                 reg = <RK3288_PD_VIDEO>;
 955                                 clocks = <&cru ACLK_VCODEC>,
 956                                          <&cru HCLK_VCODEC>;
 957                                 pm_qos = <&qos_video>;
 958                         };
 959
 960                         /*
 961                          * Note: ACLK_GPU is the GPU clock,
 962                          * and on the ACLK_GPU_NIU (NOC).
 963                          */
 964                         pd_gpu@RK3288_PD_GPU {
 965                                 reg = <RK3288_PD_GPU>;
 966                                 clocks = <&cru ACLK_GPU>;
 967                                 pm_qos = <&qos_gpu_r>,
 968                                          <&qos_gpu_w>;
 969                         };
 970                 };
 971
 972                 reboot-mode {
 973                         compatible = "syscon-reboot-mode";
 974                         offset = <0x94>;
 975                         mode-normal = <BOOT_NORMAL>;
 976                         mode-recovery = <BOOT_RECOVERY>;
 977                         mode-bootloader = <BOOT_FASTBOOT>;
 978                         mode-loader = <BOOT_BL_DOWNLOAD>;
 979                         mode-ums = <BOOT_UMS>;
 980                 };
 981         };
 982
 983         sgrf: syscon@ff740000 {
 984                 compatible = "rockchip,rk3288-sgrf", "syscon";
 985                 reg = <0xff740000 0x1000>;
 986         };
 987
 988         cru: clock-controller@ff760000 {
 989                 compatible = "rockchip,rk3288-cru";
 990                 reg = <0xff760000 0x1000>;
 991                 rockchip,grf = <&grf>;
 992                 #clock-cells = <1>;
 993                 #reset-cells = <1>;
 994                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 995                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 996                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 997                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 998                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 999                                   <&cru PCLK_PERI>;
1000                 assigned-clock-rates = <0>, <0>,
1001                                        <594000000>, <400000000>,
1002                                        <500000000>, <300000000>,
1003                                        <150000000>, <75000000>,
1004                                        <300000000>, <150000000>,
1005                                        <75000000>;
1006                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
1007         };
1008
1009         grf: syscon@ff770000 {
1010                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
1011                 reg = <0xff770000 0x1000>;
1012
1013                 edp_phy: edp-phy {
1014                         compatible = "rockchip,rk3288-dp-phy";
1015                         clocks = <&cru SCLK_EDP_24M>;
1016                         clock-names = "24m";
1017                         #phy-cells = <0>;
1018                         status = "disabled";
1019                 };
1020
1021                 io_domains: io-domains {
1022                         compatible = "rockchip,rk3288-io-voltage-domain";
1023                         status = "disabled";
1024                 };
1025
1026                 usbphy: usbphy {
1027                         compatible = "rockchip,rk3288-usb-phy";
1028                         #address-cells = <1>;
1029                         #size-cells = <0>;
1030                         status = "disabled";
1031
1032                         usbphy0: usb-phy@320 {
1033                                 #phy-cells = <0>;
1034                                 reg = <0x320>;
1035                                 clocks = <&cru SCLK_OTGPHY0>;
1036                                 clock-names = "phyclk";
1037                                 #clock-cells = <0>;
1038                                 resets = <&cru SRST_USBOTG_PHY>;
1039                                 reset-names = "phy-reset";
1040                         };
1041
1042                         usbphy1: usb-phy@334 {
1043                                 #phy-cells = <0>;
1044                                 reg = <0x334>;
1045                                 clocks = <&cru SCLK_OTGPHY1>;
1046                                 clock-names = "phyclk";
1047                                 #clock-cells = <0>;
1048                         };
1049
1050                         usbphy2: usb-phy@348 {
1051                                 #phy-cells = <0>;
1052                                 reg = <0x348>;
1053                                 clocks = <&cru SCLK_OTGPHY2>;
1054                                 clock-names = "phyclk";
1055                                 #clock-cells = <0>;
1056                                 resets = <&cru SRST_USBHOST1_PHY>;
1057                                 reset-names = "phy-reset";
1058                         };
1059                 };
1060         };
1061
1062         wdt: watchdog@ff800000 {
1063                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1064                 reg = <0xff800000 0x100>;
1065                 clocks = <&cru PCLK_WDT>;
1066                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1067                 status = "disabled";
1068         };
1069
1070         spdif: sound@ff88b0000 {
1071                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1072                 reg = <0xff8b0000 0x10000>;
1073                 #sound-dai-cells = <0>;
1074                 clock-names = "hclk", "mclk";
1075                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1076                 dmas = <&dmac_bus_s 3>;
1077                 dma-names = "tx";
1078                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1079                 pinctrl-names = "default";
1080                 pinctrl-0 = <&spdif_tx>;
1081                 rockchip,grf = <&grf>;
1082                 status = "disabled";
1083         };
1084
1085         i2s: i2s@ff890000 {
1086                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1087                 reg = <0xff890000 0x10000>;
1088                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1089                 #address-cells = <1>;
1090                 #size-cells = <0>;
1091                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1092                 dma-names = "tx", "rx";
1093                 clock-names = "i2s_hclk", "i2s_clk";
1094                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1095                 pinctrl-names = "default";
1096                 pinctrl-0 = <&i2s0_bus>;
1097                 rockchip,playback-channels = <8>;
1098                 rockchip,capture-channels = <2>;
1099                 status = "disabled";
1100         };
1101
1102         cif_isp0: cif_isp@ff910000 {
1103                 compatible = "rockchip,rk3288-cif-isp";
1104                 rockchip,grf = <&grf>;
1105                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1106                 reg-names = "register", "csihost-register";
1107                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1108                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1109                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1110                         <&cru SCLK_MIPIDSI_24M>;
1111                 clock-names = "aclk_isp", "hclk_isp",
1112                         "sclk_isp", "sclk_isp_jpe",
1113                         "pclk_mipi_csi", "pclk_isp_in",
1114                         "sclk_mipidsi_24m";
1115                 resets = <&cru SRST_ISP>;
1116                 reset-names = "rst_isp";
1117                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1118                 interrupt-names = "cif_isp10_irq";
1119                 status = "disabled";
1120         };
1121
1122         rga: rga@ff920000 {
1123                 compatible = "rockchip,rk3288-rga";
1124                 reg = <0xff920000 0x180>;
1125                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1126                 interrupt-names = "rga";
1127                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1128                 clock-names = "aclk", "hclk", "sclk";
1129                 power-domains = <&power RK3288_PD_VIO>;
1130                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1131                 reset-names = "core", "axi", "ahb";
1132                 status = "disabled";
1133         };
1134
1135         vopb: vop@ff930000 {
1136                 compatible = "rockchip,rk3288-vop";
1137                 reg = <0xff930000 0x19c>;
1138                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1139                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1140                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1141                 power-domains = <&power RK3288_PD_VIO>;
1142                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1143                 reset-names = "axi", "ahb", "dclk";
1144                 iommus = <&vopb_mmu>;
1145                 status = "disabled";
1146
1147                 vopb_out: port {
1148                         #address-cells = <1>;
1149                         #size-cells = <0>;
1150
1151                         vopb_out_hdmi: endpoint@0 {
1152                                 reg = <0>;
1153                                 remote-endpoint = <&hdmi_in_vopb>;
1154                         };
1155
1156                         vopb_out_edp: endpoint@1 {
1157                                 reg = <1>;
1158                                 remote-endpoint = <&edp_in_vopb>;
1159                         };
1160
1161                         vopb_out_mipi: endpoint@2 {
1162                                 reg = <2>;
1163                                 remote-endpoint = <&mipi_in_vopb>;
1164                         };
1165
1166                         vopb_out_lvds: endpoint@3 {
1167                                 reg = <3>;
1168                                 remote-endpoint = <&lvds_in_vopb>;
1169                         };
1170                 };
1171         };
1172
1173         vopb_mmu: iommu@ff930300 {
1174                 compatible = "rockchip,iommu";
1175                 reg = <0xff930300 0x100>;
1176                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1177                 interrupt-names = "vopb_mmu";
1178                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1179                 clock-names = "aclk", "hclk";
1180                 power-domains = <&power RK3288_PD_VIO>;
1181                 #iommu-cells = <0>;
1182                 status = "disabled";
1183         };
1184
1185         vopl: vop@ff940000 {
1186                 compatible = "rockchip,rk3288-vop";
1187                 reg = <0xff940000 0x19c>;
1188                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1189                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1190                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1191                 power-domains = <&power RK3288_PD_VIO>;
1192                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1193                 reset-names = "axi", "ahb", "dclk";
1194                 iommus = <&vopl_mmu>;
1195                 status = "disabled";
1196
1197                 vopl_out: port {
1198                         #address-cells = <1>;
1199                         #size-cells = <0>;
1200
1201                         vopl_out_hdmi: endpoint@0 {
1202                                 reg = <0>;
1203                                 remote-endpoint = <&hdmi_in_vopl>;
1204                         };
1205
1206                         vopl_out_edp: endpoint@1 {
1207                                 reg = <1>;
1208                                 remote-endpoint = <&edp_in_vopl>;
1209                         };
1210
1211                         vopl_out_mipi: endpoint@2 {
1212                                 reg = <2>;
1213                                 remote-endpoint = <&mipi_in_vopl>;
1214                         };
1215
1216                         vopl_out_lvds: endpoint@3 {
1217                                 reg = <3>;
1218                                 remote-endpoint = <&lvds_in_vopl>;
1219                         };
1220
1221                 };
1222         };
1223
1224         vopl_mmu: iommu@ff940300 {
1225                 compatible = "rockchip,iommu";
1226                 reg = <0xff940300 0x100>;
1227                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1228                 interrupt-names = "vopl_mmu";
1229                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1230                 clock-names = "aclk", "hclk";
1231                 power-domains = <&power RK3288_PD_VIO>;
1232                 #iommu-cells = <0>;
1233                 status = "disabled";
1234         };
1235
1236         mipi_dsi: mipi@ff960000 {
1237                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1238                 reg = <0xff960000 0x4000>;
1239                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1240                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1241                 clock-names = "ref", "pclk";
1242                 power-domains = <&power RK3288_PD_VIO>;
1243                 rockchip,grf = <&grf>;
1244                 #address-cells = <1>;
1245                 #size-cells = <0>;
1246                 status = "disabled";
1247
1248                 ports {
1249                         mipi_in: port {
1250                                 #address-cells = <1>;
1251                                 #size-cells = <0>;
1252                                 mipi_in_vopb: endpoint@0 {
1253                                         reg = <0>;
1254                                         remote-endpoint = <&vopb_out_mipi>;
1255                                 };
1256                                 mipi_in_vopl: endpoint@1 {
1257                                         reg = <1>;
1258                                         remote-endpoint = <&vopl_out_mipi>;
1259                                 };
1260                         };
1261                 };
1262         };
1263
1264         edp: dp@ff970000 {
1265                 compatible = "rockchip,rk3288-dp";
1266                 reg = <0xff970000 0x4000>;
1267                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1268                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1269                 clock-names = "dp", "pclk";
1270                 power-domains = <&power RK3288_PD_VIO>;
1271                 phys = <&edp_phy>;
1272                 phy-names = "dp";
1273                 resets = <&cru SRST_EDP>;
1274                 reset-names = "dp";
1275                 rockchip,grf = <&grf>;
1276                 status = "disabled";
1277
1278                 ports {
1279                         #address-cells = <1>;
1280                         #size-cells = <0>;
1281                         edp_in: port@0 {
1282                                 reg = <0>;
1283                                 #address-cells = <1>;
1284                                 #size-cells = <0>;
1285                                 edp_in_vopb: endpoint@0 {
1286                                         reg = <0>;
1287                                         remote-endpoint = <&vopb_out_edp>;
1288                                 };
1289                                 edp_in_vopl: endpoint@1 {
1290                                         reg = <1>;
1291                                         remote-endpoint = <&vopl_out_edp>;
1292                                 };
1293                         };
1294                 };
1295         };
1296
1297         lvds: lvds@ff96c000 {
1298                 compatible = "rockchip,rk3288-lvds";
1299                 reg = <0xff96c000 0x4000>;
1300                 clocks = <&cru PCLK_LVDS_PHY>;
1301                 clock-names = "pclk_lvds";
1302                 pinctrl-names = "default";
1303                 pinctrl-0 = <&lcdc0_ctl>;
1304                 power-domains = <&power RK3288_PD_VIO>;
1305                 rockchip,grf = <&grf>;
1306                 status = "disabled";
1307
1308                 ports {
1309                         #address-cells = <1>;
1310                         #size-cells = <0>;
1311
1312                         lvds_in: port@0 {
1313                                 reg = <0>;
1314
1315                                 #address-cells = <1>;
1316                                 #size-cells = <0>;
1317
1318                                 lvds_in_vopb: endpoint@0 {
1319                                         reg = <0>;
1320                                         remote-endpoint = <&vopb_out_lvds>;
1321                                 };
1322                                 lvds_in_vopl: endpoint@1 {
1323                                         reg = <1>;
1324                                         remote-endpoint = <&vopl_out_lvds>;
1325                                 };
1326                         };
1327                 };
1328         };
1329
1330         hdmi: hdmi@ff980000 {
1331                 compatible = "rockchip,rk3288-dw-hdmi";
1332                 reg = <0xff980000 0x20000>;
1333                 reg-io-width = <4>;
1334                 rockchip,grf = <&grf>;
1335                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1336                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1337                 clock-names = "iahb", "isfr";
1338                 pinctrl-names = "default";
1339                 pinctrl-0 = <&hdmi_ddc>;
1340                 power-domains = <&power RK3288_PD_VIO>;
1341                 status = "disabled";
1342
1343                 ports {
1344                         hdmi_in: port {
1345                                 #address-cells = <1>;
1346                                 #size-cells = <0>;
1347                                 hdmi_in_vopb: endpoint@0 {
1348                                         reg = <0>;
1349                                         remote-endpoint = <&vopb_out_hdmi>;
1350                                 };
1351                                 hdmi_in_vopl: endpoint@1 {
1352                                         reg = <1>;
1353                                         remote-endpoint = <&vopl_out_hdmi>;
1354                                 };
1355                         };
1356                 };
1357         };
1358
1359         vpu: video-codec@ff9a0000 {
1360                 compatible = "rockchip,rk3288-vpu";
1361                 reg = <0xff9a0000 0x800>;
1362                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1363                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1364                 interrupt-names = "vepu", "vdpu";
1365                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1366                 clock-names = "aclk", "hclk";
1367                 power-domains = <&power RK3288_PD_VIDEO>;
1368                 iommus = <&vpu_mmu>;
1369                 assigned-clocks = <&cru ACLK_VCODEC>;
1370                 assigned-clock-rates = <400000000>;
1371                 status = "disabled";
1372         };
1373
1374         vpu_service: vpu-service@ff9a0000 {
1375                 compatible = "rockchip,vpu_service";
1376                 reg = <0xff9a0000 0x800>;
1377                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1378                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1379                 interrupt-names = "irq_enc", "irq_dec";
1380                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1381                 clock-names = "aclk_vcodec", "hclk_vcodec";
1382                 power-domains = <&power RK3288_PD_VIDEO>;
1383                 rockchip,grf = <&grf>;
1384                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1385                 reset-names = "video_a", "video_h";
1386                 iommus = <&vpu_mmu>;
1387                 iommu_enabled = <1>;
1388                 dev_mode = <0>;
1389                 status = "disabled";
1390                 /* 0 means ion, 1 means drm */
1391                 allocator = <1>;
1392         };
1393
1394         vpu_mmu: iommu@ff9a0800 {
1395                 compatible = "rockchip,iommu";
1396                 reg = <0xff9a0800 0x100>;
1397                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1398                 interrupt-names = "vpu_mmu";
1399                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1400                 clock-names = "aclk", "hclk";
1401                 power-domains = <&power RK3288_PD_VIDEO>;
1402                 #iommu-cells = <0>;
1403         };
1404
1405         hevc_service: hevc-service@ff9c0000 {
1406                 compatible = "rockchip,hevc_service";
1407                 reg = <0xff9c0000 0x400>;
1408                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1409                 interrupt-names = "irq_dec";
1410                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1411                         <&cru SCLK_HEVC_CORE>,
1412                         <&cru SCLK_HEVC_CABAC>;
1413                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1414                         "clk_cabac";
1415                 /*
1416                  * The 4K hevc would also work well with 500/125/300/300,
1417                  * no more err irq and reset request.
1418                  */
1419                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1420                                   <&cru SCLK_HEVC_CORE>,
1421                                   <&cru SCLK_HEVC_CABAC>;
1422                 assigned-clock-rates = <400000000>, <100000000>,
1423                                        <300000000>, <300000000>;
1424
1425                 resets = <&cru SRST_HEVC>;
1426                 reset-names = "video";
1427                 power-domains = <&power RK3288_PD_HEVC>;
1428                 rockchip,grf = <&grf>;
1429                 dev_mode = <1>;
1430                 iommus = <&hevc_mmu>;
1431                 iommu_enabled = <1>;
1432                 status = "disabled";
1433                 /* 0 means ion, 1 means drm */
1434                 allocator = <1>;
1435         };
1436
1437         hevc_mmu: iommu@ff9c0440 {
1438                 compatible = "rockchip,iommu";
1439                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1440                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1441                 interrupt-names = "hevc_mmu";
1442                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1443                         <&cru SCLK_HEVC_CORE>,
1444                         <&cru SCLK_HEVC_CABAC>;
1445                 clock-names = "aclk", "hclk", "clk_core",
1446                         "clk_cabac";
1447                 power-domains = <&power RK3288_PD_HEVC>;
1448                 #iommu-cells = <0>;
1449         };
1450
1451         gpu: gpu@ffa30000 {
1452                 compatible = "arm,malit764",
1453                              "arm,malit76x",
1454                              "arm,malit7xx",
1455                              "arm,mali-midgard";
1456                 reg = <0xffa30000 0x10000>;
1457                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1458                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1459                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1460                 interrupt-names = "JOB", "MMU", "GPU";
1461                 clocks = <&cru ACLK_GPU>;
1462                 clock-names = "clk_mali";
1463                 operating-points-v2 = <&gpu_opp_table>;
1464                 #cooling-cells = <2>; /* min followed by max */
1465                 power-domains = <&power RK3288_PD_GPU>;
1466                 status = "disabled";
1467
1468                 gpu_power_model: power_model {
1469                         compatible = "arm,mali-simple-power-model";
1470                         voltage = <950>;
1471                         frequency = <500>;
1472                         static-power = <300>;
1473                         dynamic-power = <396>;
1474                         ts = <32000 4700 (-80) 2>;
1475                         thermal-zone = "gpu_thermal";
1476                 };
1477         };
1478
1479         gpu_opp_table: opp-table1 {
1480                 compatible = "operating-points-v2";
1481
1482                 opp@100000000 {
1483                         opp-hz = /bits/ 64 <100000000>;
1484                         opp-microvolt = <950000>;
1485                 };
1486                 opp@200000000 {
1487                         opp-hz = /bits/ 64 <200000000>;
1488                         opp-microvolt = <950000>;
1489                 };
1490                 opp@300000000 {
1491                         opp-hz = /bits/ 64 <300000000>;
1492                         opp-microvolt = <1000000>;
1493                 };
1494                 opp@400000000 {
1495                         opp-hz = /bits/ 64 <400000000>;
1496                         opp-microvolt = <1100000>;
1497                 };
1498                 opp@600000000 {
1499                         opp-hz = /bits/ 64 <600000000>;
1500                         opp-microvolt = <1250000>;
1501                 };
1502         };
1503
1504         noc: syscon@ffac0000 {
1505                 compatible = "rockchip,rk3288-noc", "syscon";
1506                 reg = <0xffac0000 0x2000>;
1507         };
1508
1509         efuse: efuse@ffb40000 {
1510                 compatible = "rockchip,rockchip-efuse";
1511                 reg = <0xffb40000 0x20>;
1512                 #address-cells = <1>;
1513                 #size-cells = <1>;
1514                 clocks = <&cru PCLK_EFUSE256>;
1515                 clock-names = "pclk_efuse";
1516
1517                 cpu_leakage: cpu_leakage@17 {
1518                         reg = <0x17 0x1>;
1519                 };
1520         };
1521
1522         gic: interrupt-controller@ffc01000 {
1523                 compatible = "arm,gic-400";
1524                 interrupt-controller;
1525                 #interrupt-cells = <3>;
1526                 #address-cells = <0>;
1527
1528                 reg = <0xffc01000 0x1000>,
1529                       <0xffc02000 0x1000>,
1530                       <0xffc04000 0x2000>,
1531                       <0xffc06000 0x2000>;
1532                 interrupts = <GIC_PPI 9 0xf04>;
1533         };
1534
1535         pinctrl: pinctrl {
1536                 compatible = "rockchip,rk3288-pinctrl";
1537                 rockchip,grf = <&grf>;
1538                 rockchip,pmu = <&pmu>;
1539                 #address-cells = <1>;
1540                 #size-cells = <1>;
1541                 ranges;
1542
1543                 gpio0: gpio0@ff750000 {
1544                         compatible = "rockchip,gpio-bank";
1545                         reg =   <0xff750000 0x100>;
1546                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1547                         clocks = <&cru PCLK_GPIO0>;
1548
1549                         gpio-controller;
1550                         #gpio-cells = <2>;
1551
1552                         interrupt-controller;
1553                         #interrupt-cells = <2>;
1554                 };
1555
1556                 gpio1: gpio1@ff780000 {
1557                         compatible = "rockchip,gpio-bank";
1558                         reg = <0xff780000 0x100>;
1559                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1560                         clocks = <&cru PCLK_GPIO1>;
1561
1562                         gpio-controller;
1563                         #gpio-cells = <2>;
1564
1565                         interrupt-controller;
1566                         #interrupt-cells = <2>;
1567                 };
1568
1569                 gpio2: gpio2@ff790000 {
1570                         compatible = "rockchip,gpio-bank";
1571                         reg = <0xff790000 0x100>;
1572                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1573                         clocks = <&cru PCLK_GPIO2>;
1574
1575                         gpio-controller;
1576                         #gpio-cells = <2>;
1577
1578                         interrupt-controller;
1579                         #interrupt-cells = <2>;
1580                 };
1581
1582                 gpio3: gpio3@ff7a0000 {
1583                         compatible = "rockchip,gpio-bank";
1584                         reg = <0xff7a0000 0x100>;
1585                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1586                         clocks = <&cru PCLK_GPIO3>;
1587
1588                         gpio-controller;
1589                         #gpio-cells = <2>;
1590
1591                         interrupt-controller;
1592                         #interrupt-cells = <2>;
1593                 };
1594
1595                 gpio4: gpio4@ff7b0000 {
1596                         compatible = "rockchip,gpio-bank";
1597                         reg = <0xff7b0000 0x100>;
1598                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1599                         clocks = <&cru PCLK_GPIO4>;
1600
1601                         gpio-controller;
1602                         #gpio-cells = <2>;
1603
1604                         interrupt-controller;
1605                         #interrupt-cells = <2>;
1606                 };
1607
1608                 gpio5: gpio5@ff7c0000 {
1609                         compatible = "rockchip,gpio-bank";
1610                         reg = <0xff7c0000 0x100>;
1611                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1612                         clocks = <&cru PCLK_GPIO5>;
1613
1614                         gpio-controller;
1615                         #gpio-cells = <2>;
1616
1617                         interrupt-controller;
1618                         #interrupt-cells = <2>;
1619                 };
1620
1621                 gpio6: gpio6@ff7d0000 {
1622                         compatible = "rockchip,gpio-bank";
1623                         reg = <0xff7d0000 0x100>;
1624                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1625                         clocks = <&cru PCLK_GPIO6>;
1626
1627                         gpio-controller;
1628                         #gpio-cells = <2>;
1629
1630                         interrupt-controller;
1631                         #interrupt-cells = <2>;
1632                 };
1633
1634                 gpio7: gpio7@ff7e0000 {
1635                         compatible = "rockchip,gpio-bank";
1636                         reg = <0xff7e0000 0x100>;
1637                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1638                         clocks = <&cru PCLK_GPIO7>;
1639
1640                         gpio-controller;
1641                         #gpio-cells = <2>;
1642
1643                         interrupt-controller;
1644                         #interrupt-cells = <2>;
1645                 };
1646
1647                 gpio8: gpio8@ff7f0000 {
1648                         compatible = "rockchip,gpio-bank";
1649                         reg = <0xff7f0000 0x100>;
1650                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1651                         clocks = <&cru PCLK_GPIO8>;
1652
1653                         gpio-controller;
1654                         #gpio-cells = <2>;
1655
1656                         interrupt-controller;
1657                         #interrupt-cells = <2>;
1658                 };
1659
1660                 hdmi {
1661                         hdmi_ddc: hdmi-ddc {
1662                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1663                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1664                         };
1665                 };
1666
1667                 pcfg_pull_up: pcfg-pull-up {
1668                         bias-pull-up;
1669                 };
1670
1671                 pcfg_pull_down: pcfg-pull-down {
1672                         bias-pull-down;
1673                 };
1674
1675                 pcfg_pull_none: pcfg-pull-none {
1676                         bias-disable;
1677                 };
1678
1679                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1680                         bias-disable;
1681                         drive-strength = <12>;
1682                 };
1683
1684                 sleep {
1685                         global_pwroff: global-pwroff {
1686                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1687                         };
1688
1689                         ddrio_pwroff: ddrio-pwroff {
1690                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1691                         };
1692
1693                         ddr0_retention: ddr0-retention {
1694                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1695                         };
1696
1697                         ddr1_retention: ddr1-retention {
1698                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1699                         };
1700                 };
1701
1702                 edp {
1703                         edp_hpd: edp-hpd {
1704                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1705                         };
1706                 };
1707
1708                 i2c0 {
1709                         i2c0_xfer: i2c0-xfer {
1710                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1711                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1712                         };
1713                 };
1714
1715                 i2c1 {
1716                         i2c1_xfer: i2c1-xfer {
1717                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1718                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1719                         };
1720                 };
1721
1722                 i2c2 {
1723                         i2c2_xfer: i2c2-xfer {
1724                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1725                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1726                         };
1727                 };
1728
1729                 i2c3 {
1730                         i2c3_xfer: i2c3-xfer {
1731                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1732                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1733                         };
1734                 };
1735
1736                 i2c4 {
1737                         i2c4_xfer: i2c4-xfer {
1738                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1739                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1740                         };
1741                 };
1742
1743                 i2c5 {
1744                         i2c5_xfer: i2c5-xfer {
1745                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1746                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1747                         };
1748                 };
1749
1750                 i2s0 {
1751                         i2s0_bus: i2s0-bus {
1752                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1753                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1754                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1755                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1756                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1757                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1758                         };
1759                 };
1760
1761                 lcdc0 {
1762                         lcdc0_ctl: lcdc0-ctl {
1763                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1764                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1765                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1766                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1767                         };
1768                 };
1769
1770                 sdmmc {
1771                         sdmmc_clk: sdmmc-clk {
1772                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774
1775                         sdmmc_cmd: sdmmc-cmd {
1776                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1777                         };
1778
1779                         sdmmc_cd: sdmcc-cd {
1780                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1781                         };
1782
1783                         sdmmc_bus1: sdmmc-bus1 {
1784                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1785                         };
1786
1787                         sdmmc_bus4: sdmmc-bus4 {
1788                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1789                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1790                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1791                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1792                         };
1793                 };
1794
1795                 sdio0 {
1796                         sdio0_bus1: sdio0-bus1 {
1797                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1798                         };
1799
1800                         sdio0_bus4: sdio0-bus4 {
1801                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1802                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1803                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1804                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1805                         };
1806
1807                         sdio0_cmd: sdio0-cmd {
1808                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1809                         };
1810
1811                         sdio0_clk: sdio0-clk {
1812                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1813                         };
1814
1815                         sdio0_cd: sdio0-cd {
1816                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1817                         };
1818
1819                         sdio0_wp: sdio0-wp {
1820                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1821                         };
1822
1823                         sdio0_pwr: sdio0-pwr {
1824                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1825                         };
1826
1827                         sdio0_bkpwr: sdio0-bkpwr {
1828                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1829                         };
1830
1831                         sdio0_int: sdio0-int {
1832                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1833                         };
1834                 };
1835
1836                 sdio1 {
1837                         sdio1_bus1: sdio1-bus1 {
1838                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1839                         };
1840
1841                         sdio1_bus4: sdio1-bus4 {
1842                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1843                                                 <3 25 4 &pcfg_pull_up>,
1844                                                 <3 26 4 &pcfg_pull_up>,
1845                                                 <3 27 4 &pcfg_pull_up>;
1846                         };
1847
1848                         sdio1_cd: sdio1-cd {
1849                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1850                         };
1851
1852                         sdio1_wp: sdio1-wp {
1853                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1854                         };
1855
1856                         sdio1_bkpwr: sdio1-bkpwr {
1857                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1858                         };
1859
1860                         sdio1_int: sdio1-int {
1861                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1862                         };
1863
1864                         sdio1_cmd: sdio1-cmd {
1865                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1866                         };
1867
1868                         sdio1_clk: sdio1-clk {
1869                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1870                         };
1871
1872                         sdio1_pwr: sdio1-pwr {
1873                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1874                         };
1875                 };
1876
1877                 emmc {
1878                         emmc_clk: emmc-clk {
1879                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1880                         };
1881
1882                         emmc_cmd: emmc-cmd {
1883                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1884                         };
1885
1886                         emmc_pwr: emmc-pwr {
1887                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1888                         };
1889
1890                         emmc_bus1: emmc-bus1 {
1891                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1892                         };
1893
1894                         emmc_bus4: emmc-bus4 {
1895                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1896                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1897                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1898                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1899                         };
1900
1901                         emmc_bus8: emmc-bus8 {
1902                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1903                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1904                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1905                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1906                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1907                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1908                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1909                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1910                         };
1911                 };
1912
1913                 spi0 {
1914                         spi0_clk: spi0-clk {
1915                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1916                         };
1917                         spi0_cs0: spi0-cs0 {
1918                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1919                         };
1920                         spi0_tx: spi0-tx {
1921                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1922                         };
1923                         spi0_rx: spi0-rx {
1924                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1925                         };
1926                         spi0_cs1: spi0-cs1 {
1927                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1928                         };
1929                 };
1930                 spi1 {
1931                         spi1_clk: spi1-clk {
1932                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1933                         };
1934                         spi1_cs0: spi1-cs0 {
1935                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1936                         };
1937                         spi1_rx: spi1-rx {
1938                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1939                         };
1940                         spi1_tx: spi1-tx {
1941                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1942                         };
1943                 };
1944
1945                 spi2 {
1946                         spi2_cs1: spi2-cs1 {
1947                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1948                         };
1949                         spi2_clk: spi2-clk {
1950                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1951                         };
1952                         spi2_cs0: spi2-cs0 {
1953                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1954                         };
1955                         spi2_rx: spi2-rx {
1956                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1957                         };
1958                         spi2_tx: spi2-tx {
1959                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1960                         };
1961                 };
1962
1963                 uart0 {
1964                         uart0_xfer: uart0-xfer {
1965                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1966                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1967                         };
1968
1969                         uart0_cts: uart0-cts {
1970                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1971                         };
1972
1973                         uart0_rts: uart0-rts {
1974                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1975                         };
1976                 };
1977
1978                 uart1 {
1979                         uart1_xfer: uart1-xfer {
1980                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1981                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1982                         };
1983
1984                         uart1_cts: uart1-cts {
1985                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1986                         };
1987
1988                         uart1_rts: uart1-rts {
1989                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1990                         };
1991                 };
1992
1993                 uart2 {
1994                         uart2_xfer: uart2-xfer {
1995                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1996                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1997                         };
1998                         /* no rts / cts for uart2 */
1999                 };
2000
2001                 uart3 {
2002                         uart3_xfer: uart3-xfer {
2003                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2004                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2005                         };
2006
2007                         uart3_cts: uart3-cts {
2008                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2009                         };
2010
2011                         uart3_rts: uart3-rts {
2012                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2013                         };
2014                 };
2015
2016                 uart4 {
2017                         uart4_xfer: uart4-xfer {
2018                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2019                                                 <5 13 3 &pcfg_pull_none>;
2020                         };
2021
2022                         uart4_cts: uart4-cts {
2023                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2024                         };
2025
2026                         uart4_rts: uart4-rts {
2027                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2028                         };
2029                 };
2030
2031                 tsadc {
2032                         otp_gpio: otp-gpio {
2033                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2034                         };
2035
2036                         otp_out: otp-out {
2037                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2038                         };
2039                 };
2040
2041                 pwm0 {
2042                         pwm0_pin: pwm0-pin {
2043                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2044                         };
2045                 };
2046
2047                 pwm1 {
2048                         pwm1_pin: pwm1-pin {
2049                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2050                         };
2051                 };
2052
2053                 pwm2 {
2054                         pwm2_pin: pwm2-pin {
2055                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2056                         };
2057                 };
2058
2059                 pwm3 {
2060                         pwm3_pin: pwm3-pin {
2061                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2062                         };
2063                 };
2064
2065                 gmac {
2066                         rgmii_pins: rgmii-pins {
2067                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2068                                                 <3 31 3 &pcfg_pull_none>,
2069                                                 <3 26 3 &pcfg_pull_none>,
2070                                                 <3 27 3 &pcfg_pull_none>,
2071                                                 <3 28 3 &pcfg_pull_none_12ma>,
2072                                                 <3 29 3 &pcfg_pull_none_12ma>,
2073                                                 <3 24 3 &pcfg_pull_none_12ma>,
2074                                                 <3 25 3 &pcfg_pull_none_12ma>,
2075                                                 <4 0 3 &pcfg_pull_none>,
2076                                                 <4 5 3 &pcfg_pull_none>,
2077                                                 <4 6 3 &pcfg_pull_none>,
2078                                                 <4 9 3 &pcfg_pull_none_12ma>,
2079                                                 <4 4 3 &pcfg_pull_none_12ma>,
2080                                                 <4 1 3 &pcfg_pull_none>,
2081                                                 <4 3 3 &pcfg_pull_none>;
2082                         };
2083
2084                         rmii_pins: rmii-pins {
2085                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2086                                                 <3 31 3 &pcfg_pull_none>,
2087                                                 <3 28 3 &pcfg_pull_none>,
2088                                                 <3 29 3 &pcfg_pull_none>,
2089                                                 <4 0 3 &pcfg_pull_none>,
2090                                                 <4 5 3 &pcfg_pull_none>,
2091                                                 <4 4 3 &pcfg_pull_none>,
2092                                                 <4 1 3 &pcfg_pull_none>,
2093                                                 <4 2 3 &pcfg_pull_none>,
2094                                                 <4 3 3 &pcfg_pull_none>;
2095                         };
2096                 };
2097
2098                 spdif {
2099                         spdif_tx: spdif-tx {
2100                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2101                         };
2102                 };
2103
2104                 cif {
2105                         cif_dvp_d2d9: cif-dvp-d2d9 {
2106                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2107                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2108                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2109                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2110                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2111                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2112                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2113                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2114                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2115                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2116                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2117                         };
2118                 };
2119         };
2120 };