arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "arm,amba-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         peripherals-req-type-burst;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         peripherals-req-type-burst;
 162                         clocks = <&cru ACLK_DMAC1>;
 163                         clock-names = "apb_pclk";
 164                         status = "disabled";
 165                 };
 166
 167                 dmac_bus_s: dma-controller@ffb20000 {
 168                         compatible = "arm,pl330", "arm,primecell";
 169                         reg = <0xffb20000 0x4000>;
 170                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 172                         #dma-cells = <1>;
 173                         arm,pl330-broken-no-flushp;
 174                         peripherals-req-type-burst;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         timer {
 208                 compatible = "arm,armv7-timer";
 209                 arm,cpu-registers-not-fw-configured;
 210                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 212                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 213                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 214                 clock-frequency = <24000000>;
 215         };
 216
 217         timer: timer@ff810000 {
 218                 compatible = "rockchip,rk3288-timer";
 219                 reg = <0xff810000 0x20>;
 220                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 222                 clock-names = "timer", "pclk";
 223         };
 224
 225         display-subsystem {
 226                 compatible = "rockchip,display-subsystem";
 227                 ports = <&vopl_out>, <&vopb_out>;
 228         };
 229
 230         sdmmc: dwmmc@ff0c0000 {
 231                 compatible = "rockchip,rk3288-dw-mshc";
 232                 clock-freq-min-max = <400000 150000000>;
 233                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 234                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 236                 fifo-depth = <0x100>;
 237                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 238                 reg = <0xff0c0000 0x4000>;
 239                 status = "disabled";
 240         };
 241
 242         sdio0: dwmmc@ff0d0000 {
 243                 compatible = "rockchip,rk3288-dw-mshc";
 244                 clock-freq-min-max = <400000 150000000>;
 245                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 246                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 250                 reg = <0xff0d0000 0x4000>;
 251                 status = "disabled";
 252         };
 253
 254         sdio1: dwmmc@ff0e0000 {
 255                 compatible = "rockchip,rk3288-dw-mshc";
 256                 clock-freq-min-max = <400000 150000000>;
 257                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 258                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 259                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 260                 fifo-depth = <0x100>;
 261                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 262                 reg = <0xff0e0000 0x4000>;
 263                 status = "disabled";
 264         };
 265
 266         emmc: dwmmc@ff0f0000 {
 267                 compatible = "rockchip,rk3288-dw-mshc";
 268                 clock-freq-min-max = <400000 150000000>;
 269                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 270                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 271                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 272                 fifo-depth = <0x100>;
 273                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 274                 reg = <0xff0f0000 0x4000>;
 275                 status = "disabled";
 276                 supports-emmc;
 277         };
 278
 279         saradc: saradc@ff100000 {
 280                 compatible = "rockchip,saradc";
 281                 reg = <0xff100000 0x100>;
 282                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 283                 #io-channel-cells = <1>;
 284                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 285                 clock-names = "saradc", "apb_pclk";
 286                 resets = <&cru SRST_SARADC>;
 287                 reset-names = "saradc-apb";
 288                 status = "disabled";
 289         };
 290
 291         spi0: spi@ff110000 {
 292                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 293                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 294                 clock-names = "spiclk", "apb_pclk";
 295                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 296                 dma-names = "tx", "rx";
 297                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 300                 reg = <0xff110000 0x1000>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 status = "disabled";
 304         };
 305
 306         spi1: spi@ff120000 {
 307                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 308                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 309                 clock-names = "spiclk", "apb_pclk";
 310                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 311                 dma-names = "tx", "rx";
 312                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 315                 reg = <0xff120000 0x1000>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 status = "disabled";
 319         };
 320
 321         spi2: spi@ff130000 {
 322                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 323                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 324                 clock-names = "spiclk", "apb_pclk";
 325                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 326                 dma-names = "tx", "rx";
 327                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 328                 pinctrl-names = "default";
 329                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 330                 reg = <0xff130000 0x1000>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 status = "disabled";
 334         };
 335
 336         i2c1: i2c@ff140000 {
 337                 compatible = "rockchip,rk3288-i2c";
 338                 reg = <0xff140000 0x1000>;
 339                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clock-names = "i2c";
 343                 clocks = <&cru PCLK_I2C1>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&i2c1_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         i2c3: i2c@ff150000 {
 350                 compatible = "rockchip,rk3288-i2c";
 351                 reg = <0xff150000 0x1000>;
 352                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clock-names = "i2c";
 356                 clocks = <&cru PCLK_I2C3>;
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&i2c3_xfer>;
 359                 status = "disabled";
 360         };
 361
 362         i2c4: i2c@ff160000 {
 363                 compatible = "rockchip,rk3288-i2c";
 364                 reg = <0xff160000 0x1000>;
 365                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clock-names = "i2c";
 369                 clocks = <&cru PCLK_I2C4>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&i2c4_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         i2c5: i2c@ff170000 {
 376                 compatible = "rockchip,rk3288-i2c";
 377                 reg = <0xff170000 0x1000>;
 378                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clock-names = "i2c";
 382                 clocks = <&cru PCLK_I2C5>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&i2c5_xfer>;
 385                 status = "disabled";
 386         };
 387
 388         uart0: serial@ff180000 {
 389                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 390                 reg = <0xff180000 0x100>;
 391                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 392                 reg-shift = <2>;
 393                 reg-io-width = <4>;
 394                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 395                 clock-names = "baudclk", "apb_pclk";
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&uart0_xfer>;
 398                 status = "disabled";
 399         };
 400
 401         uart1: serial@ff190000 {
 402                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 403                 reg = <0xff190000 0x100>;
 404                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 408                 clock-names = "baudclk", "apb_pclk";
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&uart1_xfer>;
 411                 status = "disabled";
 412         };
 413
 414         uart2: serial@ff690000 {
 415                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 416                 reg = <0xff690000 0x100>;
 417                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 418                 reg-shift = <2>;
 419                 reg-io-width = <4>;
 420                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 421                 clock-names = "baudclk", "apb_pclk";
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&uart2_xfer>;
 424                 status = "disabled";
 425         };
 426
 427         uart3: serial@ff1b0000 {
 428                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 429                 reg = <0xff1b0000 0x100>;
 430                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 431                 reg-shift = <2>;
 432                 reg-io-width = <4>;
 433                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 434                 clock-names = "baudclk", "apb_pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&uart3_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         uart4: serial@ff1c0000 {
 441                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 442                 reg = <0xff1c0000 0x100>;
 443                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 444                 reg-shift = <2>;
 445                 reg-io-width = <4>;
 446                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 447                 clock-names = "baudclk", "apb_pclk";
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&uart4_xfer>;
 450                 status = "disabled";
 451         };
 452
 453         thermal-zones {
 454                 #include "rk3288-thermal.dtsi"
 455         };
 456
 457         tsadc: tsadc@ff280000 {
 458                 compatible = "rockchip,rk3288-tsadc";
 459                 reg = <0xff280000 0x100>;
 460                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 461                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 462                 clock-names = "tsadc", "apb_pclk";
 463                 resets = <&cru SRST_TSADC>;
 464                 reset-names = "tsadc-apb";
 465                 pinctrl-names = "init", "default", "sleep";
 466                 pinctrl-0 = <&otp_gpio>;
 467                 pinctrl-1 = <&otp_out>;
 468                 pinctrl-2 = <&otp_gpio>;
 469                 #thermal-sensor-cells = <1>;
 470                 rockchip,hw-tshut-temp = <95000>;
 471                 status = "disabled";
 472         };
 473
 474         gmac: ethernet@ff290000 {
 475                 compatible = "rockchip,rk3288-gmac";
 476                 reg = <0xff290000 0x10000>;
 477                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 478                 interrupt-names = "macirq";
 479                 rockchip,grf = <&grf>;
 480                 clocks = <&cru SCLK_MAC>,
 481                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 482                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 483                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 484                 clock-names = "stmmaceth",
 485                         "mac_clk_rx", "mac_clk_tx",
 486                         "clk_mac_ref", "clk_mac_refout",
 487                         "aclk_mac", "pclk_mac";
 488                 resets = <&cru SRST_MAC>;
 489                 reset-names = "stmmaceth";
 490                 max-speed = <100>;
 491                 status = "disabled";
 492         };
 493
 494         usb_host0_ehci: usb@ff500000 {
 495                 compatible = "generic-ehci";
 496                 reg = <0xff500000 0x100>;
 497                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&cru HCLK_USBHOST0>;
 499                 clock-names = "usbhost";
 500                 phys = <&usbphy1>;
 501                 phy-names = "usb";
 502                 status = "disabled";
 503         };
 504
 505         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 506
 507         usb_host1: usb@ff540000 {
 508                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 509                                 "snps,dwc2";
 510                 reg = <0xff540000 0x40000>;
 511                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&cru HCLK_USBHOST1>;
 513                 clock-names = "otg";
 514                 dr_mode = "host";
 515                 phys = <&usbphy2>;
 516                 phy-names = "usb2-phy";
 517                 status = "disabled";
 518         };
 519
 520         usb_otg: usb@ff580000 {
 521                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 522                                 "snps,dwc2";
 523                 reg = <0xff580000 0x40000>;
 524                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&cru HCLK_OTG0>;
 526                 clock-names = "otg";
 527                 dr_mode = "otg";
 528                 g-np-tx-fifo-size = <16>;
 529                 g-rx-fifo-size = <275>;
 530                 g-tx-fifo-size = <256 128 128 64 64 32>;
 531                 g-use-dma;
 532                 phys = <&usbphy0>;
 533                 phy-names = "usb2-phy";
 534                 status = "disabled";
 535         };
 536
 537         usb_hsic: usb@ff5c0000 {
 538                 compatible = "generic-ehci";
 539                 reg = <0xff5c0000 0x100>;
 540                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&cru HCLK_HSIC>;
 542                 clock-names = "usbhost";
 543                 status = "disabled";
 544         };
 545
 546         i2c0: i2c@ff650000 {
 547                 compatible = "rockchip,rk3288-i2c";
 548                 reg = <0xff650000 0x1000>;
 549                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 clock-names = "i2c";
 553                 clocks = <&cru PCLK_I2C0>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&i2c0_xfer>;
 556                 status = "disabled";
 557         };
 558
 559         i2c2: i2c@ff660000 {
 560                 compatible = "rockchip,rk3288-i2c";
 561                 reg = <0xff660000 0x1000>;
 562                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 clock-names = "i2c";
 566                 clocks = <&cru PCLK_I2C2>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&i2c2_xfer>;
 569                 status = "disabled";
 570         };
 571
 572         pwm0: pwm@ff680000 {
 573                 compatible = "rockchip,rk3288-pwm";
 574                 reg = <0xff680000 0x10>;
 575                 #pwm-cells = <3>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&pwm0_pin>;
 578                 clocks = <&cru PCLK_PWM>;
 579                 clock-names = "pwm";
 580                 status = "disabled";
 581         };
 582
 583         pwm1: pwm@ff680010 {
 584                 compatible = "rockchip,rk3288-pwm";
 585                 reg = <0xff680010 0x10>;
 586                 #pwm-cells = <3>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&pwm1_pin>;
 589                 clocks = <&cru PCLK_PWM>;
 590                 clock-names = "pwm";
 591                 status = "disabled";
 592         };
 593
 594         pwm2: pwm@ff680020 {
 595                 compatible = "rockchip,rk3288-pwm";
 596                 reg = <0xff680020 0x10>;
 597                 #pwm-cells = <3>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&pwm2_pin>;
 600                 clocks = <&cru PCLK_PWM>;
 601                 clock-names = "pwm";
 602                 status = "disabled";
 603         };
 604
 605         pwm3: pwm@ff680030 {
 606                 compatible = "rockchip,rk3288-pwm";
 607                 reg = <0xff680030 0x10>;
 608                 #pwm-cells = <2>;
 609                 pinctrl-names = "default";
 610                 pinctrl-0 = <&pwm3_pin>;
 611                 clocks = <&cru PCLK_PWM>;
 612                 clock-names = "pwm";
 613                 status = "disabled";
 614         };
 615
 616         bus_intmem@ff700000 {
 617                 compatible = "mmio-sram";
 618                 reg = <0xff700000 0x18000>;
 619                 #address-cells = <1>;
 620                 #size-cells = <1>;
 621                 ranges = <0 0xff700000 0x18000>;
 622                 smp-sram@0 {
 623                         compatible = "rockchip,rk3066-smp-sram";
 624                         reg = <0x00 0x10>;
 625                 };
 626         };
 627
 628         sram@ff720000 {
 629                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 630                 reg = <0xff720000 0x1000>;
 631         };
 632
 633         qos_gpu_r: qos@ffaa0000 {
 634                 compatible = "syscon";
 635                 reg = <0xffaa0000 0x20>;
 636         };
 637
 638         qos_gpu_w: qos@ffaa0080 {
 639                 compatible = "syscon";
 640                 reg = <0xffaa0080 0x20>;
 641         };
 642
 643         qos_vio1_vop: qos@ffad0000 {
 644                 compatible = "syscon";
 645                 reg = <0xffad0000 0x20>;
 646         };
 647
 648         qos_vio1_isp_w0: qos@ffad0100 {
 649                 compatible = "syscon";
 650                 reg = <0xffad0100 0x20>;
 651         };
 652
 653         qos_vio1_isp_w1: qos@ffad0180 {
 654                 compatible = "syscon";
 655                 reg = <0xffad0180 0x20>;
 656         };
 657
 658         qos_vio0_vop: qos@ffad0400 {
 659                 compatible = "syscon";
 660                 reg = <0xffad0400 0x20>;
 661         };
 662
 663         qos_vio0_vip: qos@ffad0480 {
 664                 compatible = "syscon";
 665                 reg = <0xffad0480 0x20>;
 666         };
 667
 668         qos_vio0_iep: qos@ffad0500 {
 669                 compatible = "syscon";
 670                 reg = <0xffad0500 0x20>;
 671         };
 672
 673         qos_vio2_rga_r: qos@ffad0800 {
 674                 compatible = "syscon";
 675                 reg = <0xffad0800 0x20>;
 676         };
 677
 678         qos_vio2_rga_w: qos@ffad0880 {
 679                 compatible = "syscon";
 680                 reg = <0xffad0880 0x20>;
 681         };
 682
 683         qos_vio1_isp_r: qos@ffad0900 {
 684                 compatible = "syscon";
 685                 reg = <0xffad0900 0x20>;
 686         };
 687
 688         qos_video: qos@ffae0000 {
 689                 compatible = "syscon";
 690                 reg = <0xffae0000 0x20>;
 691         };
 692
 693         qos_hevc_r: qos@ffaf0000 {
 694                 compatible = "syscon";
 695                 reg = <0xffaf0000 0x20>;
 696         };
 697
 698         qos_hevc_w: qos@ffaf0080 {
 699                 compatible = "syscon";
 700                 reg = <0xffaf0080 0x20>;
 701         };
 702
 703         pmu: power-management@ff730000 {
 704                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 705                 reg = <0xff730000 0x100>;
 706
 707                 power: power-controller {
 708                         compatible = "rockchip,rk3288-power-controller";
 709                         #power-domain-cells = <1>;
 710                         #address-cells = <1>;
 711                         #size-cells = <0>;
 712
 713                         /*
 714                          * Note: Although SCLK_* are the working clocks
 715                          * of device without including on the NOC, needed for
 716                          * synchronous reset.
 717                          *
 718                          * The clocks on the which NOC:
 719                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 720                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 721                          * ACLK_RGA is on ACLK_RGA_NIU.
 722                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 723                          *
 724                          * Which clock are device clocks:
 725                          *      clocks          devices
 726                          *      *_IEP           IEP:Image Enhancement Processor
 727                          *      *_ISP           ISP:Image Signal Processing
 728                          *      *_VIP           VIP:Video Input Processor
 729                          *      *_VOP*          VOP:Visual Output Processor
 730                          *      *_RGA           RGA
 731                          *      *_EDP*          EDP
 732                          *      *_LVDS_*        LVDS
 733                          *      *_HDMI          HDMI
 734                          *      *_MIPI_*        MIPI
 735                          */
 736                         pd_vio@RK3288_PD_VIO {
 737                                 reg = <RK3288_PD_VIO>;
 738                                 clocks = <&cru ACLK_IEP>,
 739                                          <&cru ACLK_ISP>,
 740                                          <&cru ACLK_RGA>,
 741                                          <&cru ACLK_VIP>,
 742                                          <&cru ACLK_VOP0>,
 743                                          <&cru ACLK_VOP1>,
 744                                          <&cru DCLK_VOP0>,
 745                                          <&cru DCLK_VOP1>,
 746                                          <&cru HCLK_IEP>,
 747                                          <&cru HCLK_ISP>,
 748                                          <&cru HCLK_RGA>,
 749                                          <&cru HCLK_VIP>,
 750                                          <&cru HCLK_VOP0>,
 751                                          <&cru HCLK_VOP1>,
 752                                          <&cru PCLK_EDP_CTRL>,
 753                                          <&cru PCLK_HDMI_CTRL>,
 754                                          <&cru PCLK_LVDS_PHY>,
 755                                          <&cru PCLK_MIPI_CSI>,
 756                                          <&cru PCLK_MIPI_DSI0>,
 757                                          <&cru PCLK_MIPI_DSI1>,
 758                                          <&cru SCLK_EDP_24M>,
 759                                          <&cru SCLK_EDP>,
 760                                          <&cru SCLK_ISP_JPE>,
 761                                          <&cru SCLK_ISP>,
 762                                          <&cru SCLK_RGA>;
 763                                 pm_qos = <&qos_vio0_iep>,
 764                                          <&qos_vio1_vop>,
 765                                          <&qos_vio1_isp_w0>,
 766                                          <&qos_vio1_isp_w1>,
 767                                          <&qos_vio0_vop>,
 768                                          <&qos_vio0_vip>,
 769                                          <&qos_vio2_rga_r>,
 770                                          <&qos_vio2_rga_w>,
 771                                          <&qos_vio1_isp_r>;
 772                         };
 773
 774                         /*
 775                          * Note: The following 3 are HEVC(H.265) clocks,
 776                          * and on the ACLK_HEVC_NIU (NOC).
 777                          */
 778                         pd_hevc@RK3288_PD_HEVC {
 779                                 reg = <RK3288_PD_HEVC>;
 780                                 clocks = <&cru ACLK_HEVC>,
 781                                          <&cru SCLK_HEVC_CABAC>,
 782                                          <&cru SCLK_HEVC_CORE>;
 783                                 pm_qos = <&qos_hevc_r>,
 784                                          <&qos_hevc_w>;
 785                         };
 786
 787                         /*
 788                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 789                          * (video endecoder & decoder) clocks that on the
 790                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 791                          */
 792                         pd_video@RK3288_PD_VIDEO {
 793                                 reg = <RK3288_PD_VIDEO>;
 794                                 clocks = <&cru ACLK_VCODEC>,
 795                                          <&cru HCLK_VCODEC>;
 796                                 pm_qos = <&qos_video>;
 797                         };
 798
 799                         /*
 800                          * Note: ACLK_GPU is the GPU clock,
 801                          * and on the ACLK_GPU_NIU (NOC).
 802                          */
 803                         pd_gpu@RK3288_PD_GPU {
 804                                 reg = <RK3288_PD_GPU>;
 805                                 clocks = <&cru ACLK_GPU>;
 806                                 pm_qos = <&qos_gpu_r>,
 807                                          <&qos_gpu_w>;
 808                         };
 809                 };
 810
 811                 reboot-mode {
 812                         compatible = "syscon-reboot-mode";
 813                         offset = <0x94>;
 814                         mode-normal = <BOOT_NORMAL>;
 815                         mode-recovery = <BOOT_RECOVERY>;
 816                         mode-bootloader = <BOOT_FASTBOOT>;
 817                         mode-loader = <BOOT_LOADER>;
 818                         mode-ums = <BOOT_UMS>;
 819                 };
 820         };
 821
 822         sgrf: syscon@ff740000 {
 823                 compatible = "rockchip,rk3288-sgrf", "syscon";
 824                 reg = <0xff740000 0x1000>;
 825         };
 826
 827         cru: clock-controller@ff760000 {
 828                 compatible = "rockchip,rk3288-cru";
 829                 reg = <0xff760000 0x1000>;
 830                 rockchip,grf = <&grf>;
 831                 #clock-cells = <1>;
 832                 #reset-cells = <1>;
 833                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 834                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 835                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 836                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 837                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 838                                   <&cru PCLK_PERI>;
 839                 assigned-clock-rates = <0>, <0>,
 840                                        <594000000>, <400000000>,
 841                                        <500000000>, <300000000>,
 842                                        <150000000>, <75000000>,
 843                                        <300000000>, <150000000>,
 844                                        <75000000>;
 845                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 846         };
 847
 848         grf: syscon@ff770000 {
 849                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 850                 reg = <0xff770000 0x1000>;
 851
 852                 edp_phy: edp-phy {
 853                         compatible = "rockchip,rk3288-dp-phy";
 854                         clocks = <&cru SCLK_EDP_24M>;
 855                         clock-names = "24m";
 856                         #phy-cells = <0>;
 857                         status = "disabled";
 858                 };
 859
 860                 io_domains: io-domains {
 861                         compatible = "rockchip,rk3288-io-voltage-domain";
 862                         status = "disabled";
 863                 };
 864
 865                 usbphy: usbphy {
 866                         compatible = "rockchip,rk3288-usb-phy";
 867                         #address-cells = <1>;
 868                         #size-cells = <0>;
 869                         status = "disabled";
 870
 871                         usbphy0: usb-phy@320 {
 872                                 #phy-cells = <0>;
 873                                 reg = <0x320>;
 874                                 clocks = <&cru SCLK_OTGPHY0>;
 875                                 clock-names = "phyclk";
 876                                 #clock-cells = <0>;
 877                                 resets = <&cru SRST_USBOTG_PHY>;
 878                                 reset-names = "phy-reset";
 879                         };
 880
 881                         usbphy1: usb-phy@334 {
 882                                 #phy-cells = <0>;
 883                                 reg = <0x334>;
 884                                 clocks = <&cru SCLK_OTGPHY1>;
 885                                 clock-names = "phyclk";
 886                                 #clock-cells = <0>;
 887                         };
 888
 889                         usbphy2: usb-phy@348 {
 890                                 #phy-cells = <0>;
 891                                 reg = <0x348>;
 892                                 clocks = <&cru SCLK_OTGPHY2>;
 893                                 clock-names = "phyclk";
 894                                 #clock-cells = <0>;
 895                                 resets = <&cru SRST_USBHOST1_PHY>;
 896                                 reset-names = "phy-reset";
 897                         };
 898                 };
 899         };
 900
 901         wdt: watchdog@ff800000 {
 902                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 903                 reg = <0xff800000 0x100>;
 904                 clocks = <&cru PCLK_WDT>;
 905                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 906                 status = "disabled";
 907         };
 908
 909         spdif: sound@ff88b0000 {
 910                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 911                 reg = <0xff8b0000 0x10000>;
 912                 #sound-dai-cells = <0>;
 913                 clock-names = "hclk", "mclk";
 914                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 915                 dmas = <&dmac_bus_s 3>;
 916                 dma-names = "tx";
 917                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 918                 pinctrl-names = "default";
 919                 pinctrl-0 = <&spdif_tx>;
 920                 rockchip,grf = <&grf>;
 921                 status = "disabled";
 922         };
 923
 924         i2s: i2s@ff890000 {
 925                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 926                 reg = <0xff890000 0x10000>;
 927                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 928                 #address-cells = <1>;
 929                 #size-cells = <0>;
 930                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 931                 dma-names = "tx", "rx";
 932                 clock-names = "i2s_hclk", "i2s_clk";
 933                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 934                 pinctrl-names = "default";
 935                 pinctrl-0 = <&i2s0_bus>;
 936                 status = "disabled";
 937         };
 938
 939         vopb: vop@ff930000 {
 940                 compatible = "rockchip,rk3288-vop";
 941                 reg = <0xff930000 0x19c>;
 942                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 943                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 944                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 945                 power-domains = <&power RK3288_PD_VIO>;
 946                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 947                 reset-names = "axi", "ahb", "dclk";
 948                 iommus = <&vopb_mmu>;
 949                 status = "disabled";
 950
 951                 vopb_out: port {
 952                         #address-cells = <1>;
 953                         #size-cells = <0>;
 954
 955                         vopb_out_hdmi: endpoint@0 {
 956                                 reg = <0>;
 957                                 remote-endpoint = <&hdmi_in_vopb>;
 958                         };
 959
 960                         vopb_out_edp: endpoint@1 {
 961                                 reg = <1>;
 962                                 remote-endpoint = <&edp_in_vopb>;
 963                         };
 964
 965                         vopb_out_mipi: endpoint@2 {
 966                                 reg = <2>;
 967                                 remote-endpoint = <&mipi_in_vopb>;
 968                         };
 969
 970                         vopb_out_lvds: endpoint@3 {
 971                                 reg = <3>;
 972                                 remote-endpoint = <&lvds_in_vopb>;
 973                         };
 974                 };
 975         };
 976
 977         vopb_mmu: iommu@ff930300 {
 978                 compatible = "rockchip,iommu";
 979                 reg = <0xff930300 0x100>;
 980                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 981                 interrupt-names = "vopb_mmu";
 982                 power-domains = <&power RK3288_PD_VIO>;
 983                 #iommu-cells = <0>;
 984                 status = "disabled";
 985         };
 986
 987         vopl: vop@ff940000 {
 988                 compatible = "rockchip,rk3288-vop";
 989                 reg = <0xff940000 0x19c>;
 990                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 991                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 992                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 993                 power-domains = <&power RK3288_PD_VIO>;
 994                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 995                 reset-names = "axi", "ahb", "dclk";
 996                 iommus = <&vopl_mmu>;
 997                 status = "disabled";
 998
 999                 vopl_out: port {
1000                         #address-cells = <1>;
1001                         #size-cells = <0>;
1002
1003                         vopl_out_hdmi: endpoint@0 {
1004                                 reg = <0>;
1005                                 remote-endpoint = <&hdmi_in_vopl>;
1006                         };
1007
1008                         vopl_out_edp: endpoint@1 {
1009                                 reg = <1>;
1010                                 remote-endpoint = <&edp_in_vopl>;
1011                         };
1012
1013                         vopl_out_mipi: endpoint@2 {
1014                                 reg = <2>;
1015                                 remote-endpoint = <&mipi_in_vopl>;
1016                         };
1017
1018                         vopl_out_lvds: endpoint@3 {
1019                                 reg = <3>;
1020                                 remote-endpoint = <&lvds_in_vopl>;
1021                         };
1022
1023                 };
1024         };
1025
1026         vopl_mmu: iommu@ff940300 {
1027                 compatible = "rockchip,iommu";
1028                 reg = <0xff940300 0x100>;
1029                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1030                 interrupt-names = "vopl_mmu";
1031                 power-domains = <&power RK3288_PD_VIO>;
1032                 #iommu-cells = <0>;
1033                 status = "disabled";
1034         };
1035
1036         mipi_dsi: mipi@ff960000 {
1037                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1038                 reg = <0xff960000 0x4000>;
1039                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1040                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1041                 clock-names = "ref", "pclk";
1042                 rockchip,grf = <&grf>;
1043                 #address-cells = <1>;
1044                 #size-cells = <0>;
1045                 status = "disabled";
1046
1047                 ports {
1048                         #address-cells = <1>;
1049                         #size-cells = <0>;
1050                         reg = <1>;
1051
1052                         mipi_in: port {
1053                                 #address-cells = <1>;
1054                                 #size-cells = <0>;
1055                                 mipi_in_vopb: endpoint@0 {
1056                                         reg = <0>;
1057                                         remote-endpoint = <&vopb_out_mipi>;
1058                                 };
1059                                 mipi_in_vopl: endpoint@1 {
1060                                         reg = <1>;
1061                                         remote-endpoint = <&vopl_out_mipi>;
1062                                 };
1063                         };
1064                 };
1065         };
1066
1067         edp: dp@ff970000 {
1068                 compatible = "rockchip,rk3288-dp";
1069                 reg = <0xff970000 0x4000>;
1070                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1071                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1072                 clock-names = "dp", "pclk";
1073                 phys = <&edp_phy>;
1074                 phy-names = "dp";
1075                 resets = <&cru SRST_EDP>;
1076                 reset-names = "dp";
1077                 rockchip,grf = <&grf>;
1078                 status = "disabled";
1079
1080                 ports {
1081                         #address-cells = <1>;
1082                         #size-cells = <0>;
1083                         edp_in: port@0 {
1084                                 reg = <0>;
1085                                 #address-cells = <1>;
1086                                 #size-cells = <0>;
1087                                 edp_in_vopb: endpoint@0 {
1088                                         reg = <0>;
1089                                         remote-endpoint = <&vopb_out_edp>;
1090                                 };
1091                                 edp_in_vopl: endpoint@1 {
1092                                         reg = <1>;
1093                                         remote-endpoint = <&vopl_out_edp>;
1094                                 };
1095                         };
1096                 };
1097         };
1098
1099         lvds: lvds@ff96c000 {
1100                 compatible = "rockchip,rk3288-lvds";
1101                 reg = <0xff96c000 0x4000>;
1102                 clocks = <&cru PCLK_LVDS_PHY>;
1103                 clock-names = "pclk_lvds";
1104                 pinctrl-names = "default";
1105                 pinctrl-0 = <&lcdc0_ctl>;
1106                 power-domains = <&power RK3288_PD_VIO>;
1107                 rockchip,grf = <&grf>;
1108                 status = "disabled";
1109
1110                 ports {
1111                         #address-cells = <1>;
1112                         #size-cells = <0>;
1113
1114                         lvds_in: port@0 {
1115                                 reg = <0>;
1116
1117                                 #address-cells = <1>;
1118                                 #size-cells = <0>;
1119
1120                                 lvds_in_vopb: endpoint@0 {
1121                                         reg = <0>;
1122                                         remote-endpoint = <&vopb_out_lvds>;
1123                                 };
1124                                 lvds_in_vopl: endpoint@1 {
1125                                         reg = <1>;
1126                                         remote-endpoint = <&vopl_out_lvds>;
1127                                 };
1128                         };
1129                 };
1130         };
1131
1132         hdmi: hdmi@ff980000 {
1133                 compatible = "rockchip,rk3288-dw-hdmi";
1134                 reg = <0xff980000 0x20000>;
1135                 reg-io-width = <4>;
1136                 rockchip,grf = <&grf>;
1137                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1138                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1139                 clock-names = "iahb", "isfr";
1140                 power-domains = <&power RK3288_PD_VIO>;
1141                 status = "disabled";
1142
1143                 ports {
1144                         hdmi_in: port {
1145                                 #address-cells = <1>;
1146                                 #size-cells = <0>;
1147                                 hdmi_in_vopb: endpoint@0 {
1148                                         reg = <0>;
1149                                         remote-endpoint = <&vopb_out_hdmi>;
1150                                 };
1151                                 hdmi_in_vopl: endpoint@1 {
1152                                         reg = <1>;
1153                                         remote-endpoint = <&vopl_out_hdmi>;
1154                                 };
1155                         };
1156                 };
1157         };
1158
1159         gpu: gpu@ffa30000 {
1160                 compatible = "arm,malit764",
1161                              "arm,malit76x",
1162                              "arm,malit7xx",
1163                              "arm,mali-midgard";
1164                 reg = <0xffa30000 0x10000>;
1165                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1166                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1167                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1168                 interrupt-names = "JOB", "MMU", "GPU";
1169                 clocks = <&cru ACLK_GPU>;
1170                 clock-names = "clk_mali";
1171                 operating-points = <
1172                         /* KHz uV */
1173                         600000 1250000
1174                         /* 500000 1200000 - See crosbug.com/p/33857 */
1175                         400000 1100000
1176                         300000 1000000
1177                         200000 950000
1178                         100000 950000
1179                 >;
1180                 #cooling-cells = <2>; /* min followed by max */
1181                 power-domains = <&power RK3288_PD_GPU>;
1182                 status = "disabled";
1183         };
1184
1185         vpu: video-codec@ff9a0000 {
1186                 compatible = "rockchip,rk3288-vpu";
1187                 reg = <0xff9a0000 0x800>;
1188                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1189                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1190                 interrupt-names = "vepu", "vdpu";
1191                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1192                 clock-names = "aclk", "hclk";
1193                 power-domains = <&power RK3288_PD_VIDEO>;
1194                 iommus = <&vpu_mmu>;
1195                 assigned-clocks = <&cru ACLK_VCODEC>;
1196                 assigned-clock-rates = <400000000>;
1197                 status = "disabled";
1198         };
1199
1200         vpu_service: vpu-service@ff9a0000 {
1201                 compatible = "rockchip,vpu_service";
1202                 reg = <0xff9a0000 0x800>;
1203                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1204                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1205                 interrupt-names = "irq_enc", "irq_dec";
1206                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1207                 clock-names = "aclk_vcodec", "hclk_vcodec";
1208                 power-domains = <&power RK3288_PD_VIDEO>;
1209                 rockchip,grf = <&grf>;
1210                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1211                 reset-names = "video_a", "video_h";
1212                 iommus = <&vpu_mmu>;
1213                 iommu_enabled = <1>;
1214                 dev_mode = <0>;
1215                 status = "disabled";
1216         };
1217
1218         vpu_mmu: iommu@ff9a0800 {
1219                 compatible = "rockchip,iommu";
1220                 reg = <0xff9a0800 0x100>;
1221                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1222                 interrupt-names = "vpu_mmu";
1223                 power-domains = <&power RK3288_PD_VIDEO>;
1224                 #iommu-cells = <0>;
1225         };
1226
1227         hevc_service: hevc-service@ff9c0000 {
1228                 compatible = "rockchip,hevc_service";
1229                 reg = <0xff9c0000 0x400>;
1230                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1231                 interrupt-names = "irq_dec";
1232                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1233                         <&cru SCLK_HEVC_CORE>,
1234                         <&cru SCLK_HEVC_CABAC>;
1235                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1236                         "clk_cabac";
1237                 /*
1238                  * The 4K hevc would also work well with 500/125/300/300,
1239                  * no more err irq and reset request.
1240                  */
1241                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1242                                   <&cru SCLK_HEVC_CORE>,
1243                                   <&cru SCLK_HEVC_CABAC>;
1244                 assigned-clock-rates = <400000000>, <100000000>,
1245                                        <300000000>, <300000000>;
1246
1247                 resets = <&cru SRST_HEVC>;
1248                 reset-names = "video";
1249                 power-domains = <&power RK3288_PD_HEVC>;
1250                 rockchip,grf = <&grf>;
1251                 dev_mode = <1>;
1252                 iommus = <&hevc_mmu>;
1253                 iommu_enabled = <1>;
1254                 status = "disabled";
1255         };
1256
1257         hevc_mmu: iommu@ff9c0440 {
1258                 compatible = "rockchip,iommu";
1259                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1260                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1261                 interrupt-names = "hevc_mmu";
1262                 power-domains = <&power RK3288_PD_HEVC>;
1263                 #iommu-cells = <0>;
1264         };
1265
1266         gic: interrupt-controller@ffc01000 {
1267                 compatible = "arm,gic-400";
1268                 interrupt-controller;
1269                 #interrupt-cells = <3>;
1270                 #address-cells = <0>;
1271
1272                 reg = <0xffc01000 0x1000>,
1273                       <0xffc02000 0x1000>,
1274                       <0xffc04000 0x2000>,
1275                       <0xffc06000 0x2000>;
1276                 interrupts = <GIC_PPI 9 0xf04>;
1277         };
1278
1279         efuse: efuse@ffb40000 {
1280                 compatible = "rockchip,rockchip-efuse";
1281                 reg = <0xffb40000 0x20>;
1282                 #address-cells = <1>;
1283                 #size-cells = <1>;
1284                 clocks = <&cru PCLK_EFUSE256>;
1285                 clock-names = "pclk_efuse";
1286
1287                 cpu_leakage: cpu_leakage@17 {
1288                         reg = <0x17 0x1>;
1289                 };
1290         };
1291
1292         cif_isp0: cif_isp@ff910000 {
1293                 compatible = "rockchip,rk3288-cif-isp";
1294                 rockchip,grf = <&grf>;
1295                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1296                 reg-names = "register", "csihost-register";
1297                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1298                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1299                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1300                         <&cru SCLK_MIPIDSI_24M>;
1301                 clock-names = "aclk_isp", "hclk_isp",
1302                         "sclk_isp", "sclk_isp_jpe",
1303                         "pclk_mipi_csi", "pclk_isp_in",
1304                         "sclk_mipidsi_24m";
1305                 resets = <&cru SRST_ISP>;
1306                 reset-names = "rst_isp";
1307                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1308                 interrupt-names = "cif_isp10_irq";
1309                 status = "disabled";
1310         };
1311
1312         pinctrl: pinctrl {
1313                 compatible = "rockchip,rk3288-pinctrl";
1314                 rockchip,grf = <&grf>;
1315                 rockchip,pmu = <&pmu>;
1316                 #address-cells = <1>;
1317                 #size-cells = <1>;
1318                 ranges;
1319
1320                 gpio0: gpio0@ff750000 {
1321                         compatible = "rockchip,gpio-bank";
1322                         reg =   <0xff750000 0x100>;
1323                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1324                         clocks = <&cru PCLK_GPIO0>;
1325
1326                         gpio-controller;
1327                         #gpio-cells = <2>;
1328
1329                         interrupt-controller;
1330                         #interrupt-cells = <2>;
1331                 };
1332
1333                 gpio1: gpio1@ff780000 {
1334                         compatible = "rockchip,gpio-bank";
1335                         reg = <0xff780000 0x100>;
1336                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1337                         clocks = <&cru PCLK_GPIO1>;
1338
1339                         gpio-controller;
1340                         #gpio-cells = <2>;
1341
1342                         interrupt-controller;
1343                         #interrupt-cells = <2>;
1344                 };
1345
1346                 gpio2: gpio2@ff790000 {
1347                         compatible = "rockchip,gpio-bank";
1348                         reg = <0xff790000 0x100>;
1349                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1350                         clocks = <&cru PCLK_GPIO2>;
1351
1352                         gpio-controller;
1353                         #gpio-cells = <2>;
1354
1355                         interrupt-controller;
1356                         #interrupt-cells = <2>;
1357                 };
1358
1359                 gpio3: gpio3@ff7a0000 {
1360                         compatible = "rockchip,gpio-bank";
1361                         reg = <0xff7a0000 0x100>;
1362                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1363                         clocks = <&cru PCLK_GPIO3>;
1364
1365                         gpio-controller;
1366                         #gpio-cells = <2>;
1367
1368                         interrupt-controller;
1369                         #interrupt-cells = <2>;
1370                 };
1371
1372                 gpio4: gpio4@ff7b0000 {
1373                         compatible = "rockchip,gpio-bank";
1374                         reg = <0xff7b0000 0x100>;
1375                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1376                         clocks = <&cru PCLK_GPIO4>;
1377
1378                         gpio-controller;
1379                         #gpio-cells = <2>;
1380
1381                         interrupt-controller;
1382                         #interrupt-cells = <2>;
1383                 };
1384
1385                 gpio5: gpio5@ff7c0000 {
1386                         compatible = "rockchip,gpio-bank";
1387                         reg = <0xff7c0000 0x100>;
1388                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1389                         clocks = <&cru PCLK_GPIO5>;
1390
1391                         gpio-controller;
1392                         #gpio-cells = <2>;
1393
1394                         interrupt-controller;
1395                         #interrupt-cells = <2>;
1396                 };
1397
1398                 gpio6: gpio6@ff7d0000 {
1399                         compatible = "rockchip,gpio-bank";
1400                         reg = <0xff7d0000 0x100>;
1401                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1402                         clocks = <&cru PCLK_GPIO6>;
1403
1404                         gpio-controller;
1405                         #gpio-cells = <2>;
1406
1407                         interrupt-controller;
1408                         #interrupt-cells = <2>;
1409                 };
1410
1411                 gpio7: gpio7@ff7e0000 {
1412                         compatible = "rockchip,gpio-bank";
1413                         reg = <0xff7e0000 0x100>;
1414                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1415                         clocks = <&cru PCLK_GPIO7>;
1416
1417                         gpio-controller;
1418                         #gpio-cells = <2>;
1419
1420                         interrupt-controller;
1421                         #interrupt-cells = <2>;
1422                 };
1423
1424                 gpio8: gpio8@ff7f0000 {
1425                         compatible = "rockchip,gpio-bank";
1426                         reg = <0xff7f0000 0x100>;
1427                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1428                         clocks = <&cru PCLK_GPIO8>;
1429
1430                         gpio-controller;
1431                         #gpio-cells = <2>;
1432
1433                         interrupt-controller;
1434                         #interrupt-cells = <2>;
1435                 };
1436
1437                 hdmi {
1438                         hdmi_ddc: hdmi-ddc {
1439                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1440                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1441                         };
1442                 };
1443
1444                 pcfg_pull_up: pcfg-pull-up {
1445                         bias-pull-up;
1446                 };
1447
1448                 pcfg_pull_down: pcfg-pull-down {
1449                         bias-pull-down;
1450                 };
1451
1452                 pcfg_pull_none: pcfg-pull-none {
1453                         bias-disable;
1454                 };
1455
1456                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1457                         bias-disable;
1458                         drive-strength = <12>;
1459                 };
1460
1461                 sleep {
1462                         global_pwroff: global-pwroff {
1463                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465
1466                         ddrio_pwroff: ddrio-pwroff {
1467                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1468                         };
1469
1470                         ddr0_retention: ddr0-retention {
1471                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1472                         };
1473
1474                         ddr1_retention: ddr1-retention {
1475                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1476                         };
1477                 };
1478
1479                 edp {
1480                         edp_hpd: edp-hpd {
1481                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1482                         };
1483                 };
1484
1485                 i2c0 {
1486                         i2c0_xfer: i2c0-xfer {
1487                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1488                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1489                         };
1490                 };
1491
1492                 i2c1 {
1493                         i2c1_xfer: i2c1-xfer {
1494                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1495                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1496                         };
1497                 };
1498
1499                 i2c2 {
1500                         i2c2_xfer: i2c2-xfer {
1501                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1502                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1503                         };
1504                 };
1505
1506                 i2c3 {
1507                         i2c3_xfer: i2c3-xfer {
1508                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1509                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1510                         };
1511                 };
1512
1513                 i2c4 {
1514                         i2c4_xfer: i2c4-xfer {
1515                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1516                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1517                         };
1518                 };
1519
1520                 i2c5 {
1521                         i2c5_xfer: i2c5-xfer {
1522                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1523                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1524                         };
1525                 };
1526
1527                 i2s0 {
1528                         i2s0_bus: i2s0-bus {
1529                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1530                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1531                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1532                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1533                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1534                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1535                         };
1536                 };
1537
1538                 lcdc0 {
1539                         lcdc0_ctl: lcdc0-ctl {
1540                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1541                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1542                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1543                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1544                         };
1545                 };
1546
1547                 sdmmc {
1548                         sdmmc_clk: sdmmc-clk {
1549                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1550                         };
1551
1552                         sdmmc_cmd: sdmmc-cmd {
1553                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1554                         };
1555
1556                         sdmmc_cd: sdmcc-cd {
1557                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1558                         };
1559
1560                         sdmmc_bus1: sdmmc-bus1 {
1561                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1562                         };
1563
1564                         sdmmc_bus4: sdmmc-bus4 {
1565                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1566                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1567                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1568                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1569                         };
1570                 };
1571
1572                 sdio0 {
1573                         sdio0_bus1: sdio0-bus1 {
1574                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1575                         };
1576
1577                         sdio0_bus4: sdio0-bus4 {
1578                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1579                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1580                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1581                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1582                         };
1583
1584                         sdio0_cmd: sdio0-cmd {
1585                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1586                         };
1587
1588                         sdio0_clk: sdio0-clk {
1589                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1590                         };
1591
1592                         sdio0_cd: sdio0-cd {
1593                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1594                         };
1595
1596                         sdio0_wp: sdio0-wp {
1597                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1598                         };
1599
1600                         sdio0_pwr: sdio0-pwr {
1601                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1602                         };
1603
1604                         sdio0_bkpwr: sdio0-bkpwr {
1605                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1606                         };
1607
1608                         sdio0_int: sdio0-int {
1609                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1610                         };
1611                 };
1612
1613                 sdio1 {
1614                         sdio1_bus1: sdio1-bus1 {
1615                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1616                         };
1617
1618                         sdio1_bus4: sdio1-bus4 {
1619                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1620                                                 <3 25 4 &pcfg_pull_up>,
1621                                                 <3 26 4 &pcfg_pull_up>,
1622                                                 <3 27 4 &pcfg_pull_up>;
1623                         };
1624
1625                         sdio1_cd: sdio1-cd {
1626                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1627                         };
1628
1629                         sdio1_wp: sdio1-wp {
1630                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1631                         };
1632
1633                         sdio1_bkpwr: sdio1-bkpwr {
1634                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1635                         };
1636
1637                         sdio1_int: sdio1-int {
1638                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1639                         };
1640
1641                         sdio1_cmd: sdio1-cmd {
1642                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1643                         };
1644
1645                         sdio1_clk: sdio1-clk {
1646                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1647                         };
1648
1649                         sdio1_pwr: sdio1-pwr {
1650                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1651                         };
1652                 };
1653
1654                 emmc {
1655                         emmc_clk: emmc-clk {
1656                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1657                         };
1658
1659                         emmc_cmd: emmc-cmd {
1660                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1661                         };
1662
1663                         emmc_pwr: emmc-pwr {
1664                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1665                         };
1666
1667                         emmc_bus1: emmc-bus1 {
1668                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1669                         };
1670
1671                         emmc_bus4: emmc-bus4 {
1672                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1673                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1674                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1675                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1676                         };
1677
1678                         emmc_bus8: emmc-bus8 {
1679                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1680                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1681                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1682                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1683                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1684                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1685                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1686                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1687                         };
1688                 };
1689
1690                 spi0 {
1691                         spi0_clk: spi0-clk {
1692                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1693                         };
1694                         spi0_cs0: spi0-cs0 {
1695                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1696                         };
1697                         spi0_tx: spi0-tx {
1698                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1699                         };
1700                         spi0_rx: spi0-rx {
1701                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1702                         };
1703                         spi0_cs1: spi0-cs1 {
1704                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1705                         };
1706                 };
1707                 spi1 {
1708                         spi1_clk: spi1-clk {
1709                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1710                         };
1711                         spi1_cs0: spi1-cs0 {
1712                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1713                         };
1714                         spi1_rx: spi1-rx {
1715                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1716                         };
1717                         spi1_tx: spi1-tx {
1718                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1719                         };
1720                 };
1721
1722                 spi2 {
1723                         spi2_cs1: spi2-cs1 {
1724                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1725                         };
1726                         spi2_clk: spi2-clk {
1727                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1728                         };
1729                         spi2_cs0: spi2-cs0 {
1730                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1731                         };
1732                         spi2_rx: spi2-rx {
1733                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1734                         };
1735                         spi2_tx: spi2-tx {
1736                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1737                         };
1738                 };
1739
1740                 uart0 {
1741                         uart0_xfer: uart0-xfer {
1742                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1743                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1744                         };
1745
1746                         uart0_cts: uart0-cts {
1747                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1748                         };
1749
1750                         uart0_rts: uart0-rts {
1751                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1752                         };
1753                 };
1754
1755                 uart1 {
1756                         uart1_xfer: uart1-xfer {
1757                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1758                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1759                         };
1760
1761                         uart1_cts: uart1-cts {
1762                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1763                         };
1764
1765                         uart1_rts: uart1-rts {
1766                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1767                         };
1768                 };
1769
1770                 uart2 {
1771                         uart2_xfer: uart2-xfer {
1772                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1773                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1774                         };
1775                         /* no rts / cts for uart2 */
1776                 };
1777
1778                 uart3 {
1779                         uart3_xfer: uart3-xfer {
1780                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1781                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1782                         };
1783
1784                         uart3_cts: uart3-cts {
1785                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1786                         };
1787
1788                         uart3_rts: uart3-rts {
1789                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1790                         };
1791                 };
1792
1793                 uart4 {
1794                         uart4_xfer: uart4-xfer {
1795                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1796                                                 <5 13 3 &pcfg_pull_none>;
1797                         };
1798
1799                         uart4_cts: uart4-cts {
1800                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1801                         };
1802
1803                         uart4_rts: uart4-rts {
1804                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1805                         };
1806                 };
1807
1808                 tsadc {
1809                         otp_gpio: otp-gpio {
1810                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1811                         };
1812
1813                         otp_out: otp-out {
1814                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1815                         };
1816                 };
1817
1818                 pwm0 {
1819                         pwm0_pin: pwm0-pin {
1820                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1821                         };
1822                 };
1823
1824                 pwm1 {
1825                         pwm1_pin: pwm1-pin {
1826                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1827                         };
1828                 };
1829
1830                 pwm2 {
1831                         pwm2_pin: pwm2-pin {
1832                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1833                         };
1834                 };
1835
1836                 pwm3 {
1837                         pwm3_pin: pwm3-pin {
1838                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1839                         };
1840                 };
1841
1842                 gmac {
1843                         rgmii_pins: rgmii-pins {
1844                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1845                                                 <3 31 3 &pcfg_pull_none>,
1846                                                 <3 26 3 &pcfg_pull_none>,
1847                                                 <3 27 3 &pcfg_pull_none>,
1848                                                 <3 28 3 &pcfg_pull_none_12ma>,
1849                                                 <3 29 3 &pcfg_pull_none_12ma>,
1850                                                 <3 24 3 &pcfg_pull_none_12ma>,
1851                                                 <3 25 3 &pcfg_pull_none_12ma>,
1852                                                 <4 0 3 &pcfg_pull_none>,
1853                                                 <4 5 3 &pcfg_pull_none>,
1854                                                 <4 6 3 &pcfg_pull_none>,
1855                                                 <4 9 3 &pcfg_pull_none_12ma>,
1856                                                 <4 4 3 &pcfg_pull_none_12ma>,
1857                                                 <4 1 3 &pcfg_pull_none>,
1858                                                 <4 3 3 &pcfg_pull_none>;
1859                         };
1860
1861                         rmii_pins: rmii-pins {
1862                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1863                                                 <3 31 3 &pcfg_pull_none>,
1864                                                 <3 28 3 &pcfg_pull_none>,
1865                                                 <3 29 3 &pcfg_pull_none>,
1866                                                 <4 0 3 &pcfg_pull_none>,
1867                                                 <4 5 3 &pcfg_pull_none>,
1868                                                 <4 4 3 &pcfg_pull_none>,
1869                                                 <4 1 3 &pcfg_pull_none>,
1870                                                 <4 2 3 &pcfg_pull_none>,
1871                                                 <4 3 3 &pcfg_pull_none>;
1872                         };
1873                 };
1874
1875                 spdif {
1876                         spdif_tx: spdif-tx {
1877                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1878                         };
1879                 };
1880
1881                 cif {
1882                         cif_dvp_d2d9: cif-dvp-d2d9 {
1883                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
1884                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1885                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1886                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1887                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1888                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1889                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1890                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1891                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1892                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1893                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
1894                         };
1895                 };
1896         };
1897 };