arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 mshc0 = &emmc;
  65                 mshc1 = &sdmmc;
  66                 mshc2 = &sdio0;
  67                 mshc3 = &sdio1;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73                 spi0 = &spi0;
  74                 spi1 = &spi1;
  75                 spi2 = &spi2;
  76         };
  77
  78         arm-pmu {
  79                 compatible = "arm,cortex-a12-pmu";
  80                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  84                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  85         };
  86
  87         cpus {
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 enable-method = "rockchip,rk3066-smp";
  91                 rockchip,pmu = <&pmu>;
  92
  93                 cpu0: cpu@500 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a12";
  96                         reg = <0x500>;
  97                         resets = <&cru SRST_CORE0>;
  98                         operating-points = <
  99                                 /* KHz    uV */
 100                                 1608000 1350000
 101                                 1512000 1300000
 102                                 1416000 1200000
 103                                 1200000 1100000
 104                                 1008000 1050000
 105                                  816000 1000000
 106                                  696000  950000
 107                                  600000  900000
 108                                  408000  900000
 109                                  312000  900000
 110                                  216000  900000
 111                                  126000  900000
 112                         >;
 113                         #cooling-cells = <2>; /* min followed by max */
 114                         clock-latency = <40000>;
 115                         clocks = <&cru ARMCLK>;
 116                 };
 117                 cpu1: cpu@501 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a12";
 120                         reg = <0x501>;
 121                         resets = <&cru SRST_CORE1>;
 122                 };
 123                 cpu2: cpu@502 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a12";
 126                         reg = <0x502>;
 127                         resets = <&cru SRST_CORE2>;
 128                 };
 129                 cpu3: cpu@503 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a12";
 132                         reg = <0x503>;
 133                         resets = <&cru SRST_CORE3>;
 134                 };
 135         };
 136
 137         amba {
 138                 compatible = "arm,amba-bus";
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 ranges;
 142
 143                 dmac_peri: dma-controller@ff250000 {
 144                         compatible = "arm,pl330", "arm,primecell";
 145                         reg = <0xff250000 0x4000>;
 146                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 148                         #dma-cells = <1>;
 149                         arm,pl330-broken-no-flushp;
 150                         peripherals-req-type-burst;
 151                         clocks = <&cru ACLK_DMAC2>;
 152                         clock-names = "apb_pclk";
 153                 };
 154
 155                 dmac_bus_ns: dma-controller@ff600000 {
 156                         compatible = "arm,pl330", "arm,primecell";
 157                         reg = <0xff600000 0x4000>;
 158                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 159                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 160                         #dma-cells = <1>;
 161                         arm,pl330-broken-no-flushp;
 162                         peripherals-req-type-burst;
 163                         clocks = <&cru ACLK_DMAC1>;
 164                         clock-names = "apb_pclk";
 165                         status = "disabled";
 166                 };
 167
 168                 dmac_bus_s: dma-controller@ffb20000 {
 169                         compatible = "arm,pl330", "arm,primecell";
 170                         reg = <0xffb20000 0x4000>;
 171                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 172                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 173                         #dma-cells = <1>;
 174                         arm,pl330-broken-no-flushp;
 175                         peripherals-req-type-burst;
 176                         clocks = <&cru ACLK_DMAC1>;
 177                         clock-names = "apb_pclk";
 178                 };
 179         };
 180
 181         reserved-memory {
 182                 #address-cells = <1>;
 183                 #size-cells = <1>;
 184                 ranges;
 185
 186                 /*
 187                  * The rk3288 cannot use the memory area above 0xfe000000
 188                  * for dma operations for some reason. While there is
 189                  * probably a better solution available somewhere, we
 190                  * haven't found it yet and while devices with 2GB of ram
 191                  * are not affected, this issue prevents 4GB from booting.
 192                  * So to make these devices at least bootable, block
 193                  * this area for the time being until the real solution
 194                  * is found.
 195                  */
 196                 dma-unusable@fe000000 {
 197                         reg = <0xfe000000 0x1000000>;
 198                 };
 199         };
 200
 201         xin24m: oscillator {
 202                 compatible = "fixed-clock";
 203                 clock-frequency = <24000000>;
 204                 clock-output-names = "xin24m";
 205                 #clock-cells = <0>;
 206         };
 207
 208         timer {
 209                 compatible = "arm,armv7-timer";
 210                 arm,cpu-registers-not-fw-configured;
 211                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 212                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 213                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 214                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 215                 clock-frequency = <24000000>;
 216         };
 217
 218         timer: timer@ff810000 {
 219                 compatible = "rockchip,rk3288-timer";
 220                 reg = <0xff810000 0x20>;
 221                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 223                 clock-names = "timer", "pclk";
 224         };
 225
 226         display-subsystem {
 227                 compatible = "rockchip,display-subsystem";
 228                 ports = <&vopl_out>, <&vopb_out>;
 229         };
 230
 231         sdmmc: dwmmc@ff0c0000 {
 232                 compatible = "rockchip,rk3288-dw-mshc";
 233                 clock-freq-min-max = <400000 150000000>;
 234                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 235                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 236                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 237                 fifo-depth = <0x100>;
 238                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 239                 reg = <0xff0c0000 0x4000>;
 240                 status = "disabled";
 241         };
 242
 243         sdio0: dwmmc@ff0d0000 {
 244                 compatible = "rockchip,rk3288-dw-mshc";
 245                 clock-freq-min-max = <400000 150000000>;
 246                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 247                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 248                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 249                 fifo-depth = <0x100>;
 250                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 251                 reg = <0xff0d0000 0x4000>;
 252                 status = "disabled";
 253         };
 254
 255         sdio1: dwmmc@ff0e0000 {
 256                 compatible = "rockchip,rk3288-dw-mshc";
 257                 clock-freq-min-max = <400000 150000000>;
 258                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 259                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 260                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 261                 fifo-depth = <0x100>;
 262                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 263                 reg = <0xff0e0000 0x4000>;
 264                 status = "disabled";
 265         };
 266
 267         emmc: dwmmc@ff0f0000 {
 268                 compatible = "rockchip,rk3288-dw-mshc";
 269                 clock-freq-min-max = <400000 150000000>;
 270                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 271                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 272                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 273                 fifo-depth = <0x100>;
 274                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 275                 reg = <0xff0f0000 0x4000>;
 276                 status = "disabled";
 277                 supports-emmc;
 278         };
 279
 280         saradc: saradc@ff100000 {
 281                 compatible = "rockchip,saradc";
 282                 reg = <0xff100000 0x100>;
 283                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 284                 #io-channel-cells = <1>;
 285                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 286                 clock-names = "saradc", "apb_pclk";
 287                 resets = <&cru SRST_SARADC>;
 288                 reset-names = "saradc-apb";
 289                 status = "disabled";
 290         };
 291
 292         spi0: spi@ff110000 {
 293                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 294                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 295                 clock-names = "spiclk", "apb_pclk";
 296                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 297                 dma-names = "tx", "rx";
 298                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 301                 reg = <0xff110000 0x1000>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304                 status = "disabled";
 305         };
 306
 307         spi1: spi@ff120000 {
 308                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 309                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 310                 clock-names = "spiclk", "apb_pclk";
 311                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 312                 dma-names = "tx", "rx";
 313                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 314                 pinctrl-names = "default";
 315                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 316                 reg = <0xff120000 0x1000>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 status = "disabled";
 320         };
 321
 322         spi2: spi@ff130000 {
 323                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 324                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 325                 clock-names = "spiclk", "apb_pclk";
 326                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 327                 dma-names = "tx", "rx";
 328                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 331                 reg = <0xff130000 0x1000>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 status = "disabled";
 335         };
 336
 337         i2c1: i2c@ff140000 {
 338                 compatible = "rockchip,rk3288-i2c";
 339                 reg = <0xff140000 0x1000>;
 340                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 341                 #address-cells = <1>;
 342                 #size-cells = <0>;
 343                 clock-names = "i2c";
 344                 clocks = <&cru PCLK_I2C1>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&i2c1_xfer>;
 347                 status = "disabled";
 348         };
 349
 350         i2c3: i2c@ff150000 {
 351                 compatible = "rockchip,rk3288-i2c";
 352                 reg = <0xff150000 0x1000>;
 353                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 clock-names = "i2c";
 357                 clocks = <&cru PCLK_I2C3>;
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&i2c3_xfer>;
 360                 status = "disabled";
 361         };
 362
 363         i2c4: i2c@ff160000 {
 364                 compatible = "rockchip,rk3288-i2c";
 365                 reg = <0xff160000 0x1000>;
 366                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 clock-names = "i2c";
 370                 clocks = <&cru PCLK_I2C4>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&i2c4_xfer>;
 373                 status = "disabled";
 374         };
 375
 376         i2c5: i2c@ff170000 {
 377                 compatible = "rockchip,rk3288-i2c";
 378                 reg = <0xff170000 0x1000>;
 379                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 clock-names = "i2c";
 383                 clocks = <&cru PCLK_I2C5>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&i2c5_xfer>;
 386                 status = "disabled";
 387         };
 388
 389         uart0: serial@ff180000 {
 390                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 391                 reg = <0xff180000 0x100>;
 392                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 393                 reg-shift = <2>;
 394                 reg-io-width = <4>;
 395                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 396                 clock-names = "baudclk", "apb_pclk";
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&uart0_xfer>;
 399                 status = "disabled";
 400         };
 401
 402         uart1: serial@ff190000 {
 403                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 404                 reg = <0xff190000 0x100>;
 405                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 406                 reg-shift = <2>;
 407                 reg-io-width = <4>;
 408                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 409                 clock-names = "baudclk", "apb_pclk";
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&uart1_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         uart2: serial@ff690000 {
 416                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 417                 reg = <0xff690000 0x100>;
 418                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 419                 reg-shift = <2>;
 420                 reg-io-width = <4>;
 421                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 422                 clock-names = "baudclk", "apb_pclk";
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&uart2_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         uart3: serial@ff1b0000 {
 429                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 430                 reg = <0xff1b0000 0x100>;
 431                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 432                 reg-shift = <2>;
 433                 reg-io-width = <4>;
 434                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 435                 clock-names = "baudclk", "apb_pclk";
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&uart3_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         uart4: serial@ff1c0000 {
 442                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 443                 reg = <0xff1c0000 0x100>;
 444                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 445                 reg-shift = <2>;
 446                 reg-io-width = <4>;
 447                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 448                 clock-names = "baudclk", "apb_pclk";
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&uart4_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         thermal-zones {
 455                 reserve_thermal: reserve_thermal {
 456                         polling-delay-passive = <1000>; /* milliseconds */
 457                         polling-delay = <5000>; /* milliseconds */
 458
 459                         thermal-sensors = <&tsadc 0>;
 460                 };
 461
 462                 cpu_thermal: cpu_thermal {
 463                         polling-delay-passive = <100>; /* milliseconds */
 464                         polling-delay = <5000>; /* milliseconds */
 465
 466                         thermal-sensors = <&tsadc 1>;
 467
 468                         trips {
 469                                 cpu_alert0: cpu_alert0 {
 470                                         temperature = <70000>; /* millicelsius */
 471                                         hysteresis = <2000>; /* millicelsius */
 472                                         type = "passive";
 473                                 };
 474                                 cpu_alert1: cpu_alert1 {
 475                                         temperature = <75000>; /* millicelsius */
 476                                         hysteresis = <2000>; /* millicelsius */
 477                                         type = "passive";
 478                                 };
 479                                 cpu_crit: cpu_crit {
 480                                         temperature = <90000>; /* millicelsius */
 481                                         hysteresis = <2000>; /* millicelsius */
 482                                         type = "critical";
 483                                 };
 484                         };
 485
 486                         cooling-maps {
 487                                 map0 {
 488                                         trip = <&cpu_alert0>;
 489                                         cooling-device =
 490                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 491                                 };
 492                                 map1 {
 493                                         trip = <&cpu_alert1>;
 494                                         cooling-device =
 495                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 496                                 };
 497                         };
 498                 };
 499
 500                 gpu_thermal: gpu_thermal {
 501                         polling-delay-passive = <100>; /* milliseconds */
 502                         polling-delay = <5000>; /* milliseconds */
 503
 504                         thermal-sensors = <&tsadc 2>;
 505
 506                         trips {
 507                                 gpu_alert0: gpu_alert0 {
 508                                         temperature = <70000>; /* millicelsius */
 509                                         hysteresis = <2000>; /* millicelsius */
 510                                         type = "passive";
 511                                 };
 512                                 gpu_crit: gpu_crit {
 513                                         temperature = <90000>; /* millicelsius */
 514                                         hysteresis = <2000>; /* millicelsius */
 515                                         type = "critical";
 516                                 };
 517                         };
 518
 519                         cooling-maps {
 520                                 map0 {
 521                                         trip = <&gpu_alert0>;
 522                                         cooling-device =
 523                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 524                                 };
 525                         };
 526                 };
 527         };
 528
 529         tsadc: tsadc@ff280000 {
 530                 compatible = "rockchip,rk3288-tsadc";
 531                 reg = <0xff280000 0x100>;
 532                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 534                 clock-names = "tsadc", "apb_pclk";
 535                 resets = <&cru SRST_TSADC>;
 536                 reset-names = "tsadc-apb";
 537                 pinctrl-names = "init", "default", "sleep";
 538                 pinctrl-0 = <&otp_gpio>;
 539                 pinctrl-1 = <&otp_out>;
 540                 pinctrl-2 = <&otp_gpio>;
 541                 #thermal-sensor-cells = <1>;
 542                 rockchip,hw-tshut-temp = <95000>;
 543                 status = "disabled";
 544         };
 545
 546         gmac: ethernet@ff290000 {
 547                 compatible = "rockchip,rk3288-gmac";
 548                 reg = <0xff290000 0x10000>;
 549                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 550                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 551                 interrupt-names = "macirq", "eth_wake_irq";
 552                 rockchip,grf = <&grf>;
 553                 clocks = <&cru SCLK_MAC>,
 554                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 555                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 556                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 557                 clock-names = "stmmaceth",
 558                         "mac_clk_rx", "mac_clk_tx",
 559                         "clk_mac_ref", "clk_mac_refout",
 560                         "aclk_mac", "pclk_mac";
 561                 resets = <&cru SRST_MAC>;
 562                 reset-names = "stmmaceth";
 563                 max-speed = <100>;
 564                 status = "disabled";
 565         };
 566
 567         usb_host0_ehci: usb@ff500000 {
 568                 compatible = "generic-ehci";
 569                 reg = <0xff500000 0x100>;
 570                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 571                 clocks = <&cru HCLK_USBHOST0>;
 572                 clock-names = "usbhost";
 573                 phys = <&usbphy1>;
 574                 phy-names = "usb";
 575                 status = "disabled";
 576         };
 577
 578         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 579
 580         usb_host1: usb@ff540000 {
 581                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 582                                 "snps,dwc2";
 583                 reg = <0xff540000 0x40000>;
 584                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 585                 clocks = <&cru HCLK_USBHOST1>;
 586                 clock-names = "otg";
 587                 dr_mode = "host";
 588                 phys = <&usbphy2>;
 589                 phy-names = "usb2-phy";
 590                 status = "disabled";
 591         };
 592
 593         usb_otg: usb@ff580000 {
 594                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 595                                 "snps,dwc2";
 596                 reg = <0xff580000 0x40000>;
 597                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 598                 clocks = <&cru HCLK_OTG0>;
 599                 clock-names = "otg";
 600                 dr_mode = "otg";
 601                 g-np-tx-fifo-size = <16>;
 602                 g-rx-fifo-size = <275>;
 603                 g-tx-fifo-size = <256 128 128 64 64 32>;
 604                 g-use-dma;
 605                 phys = <&usbphy0>;
 606                 phy-names = "usb2-phy";
 607                 status = "disabled";
 608         };
 609
 610         usb_hsic: usb@ff5c0000 {
 611                 compatible = "generic-ehci";
 612                 reg = <0xff5c0000 0x100>;
 613                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&cru HCLK_HSIC>;
 615                 clock-names = "usbhost";
 616                 status = "disabled";
 617         };
 618
 619         i2c0: i2c@ff650000 {
 620                 compatible = "rockchip,rk3288-i2c";
 621                 reg = <0xff650000 0x1000>;
 622                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 clock-names = "i2c";
 626                 clocks = <&cru PCLK_I2C0>;
 627                 pinctrl-names = "default";
 628                 pinctrl-0 = <&i2c0_xfer>;
 629                 status = "disabled";
 630         };
 631
 632         i2c2: i2c@ff660000 {
 633                 compatible = "rockchip,rk3288-i2c";
 634                 reg = <0xff660000 0x1000>;
 635                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 clock-names = "i2c";
 639                 clocks = <&cru PCLK_I2C2>;
 640                 pinctrl-names = "default";
 641                 pinctrl-0 = <&i2c2_xfer>;
 642                 status = "disabled";
 643         };
 644
 645         pwm0: pwm@ff680000 {
 646                 compatible = "rockchip,rk3288-pwm";
 647                 reg = <0xff680000 0x10>;
 648                 #pwm-cells = <3>;
 649                 pinctrl-names = "default";
 650                 pinctrl-0 = <&pwm0_pin>;
 651                 clocks = <&cru PCLK_PWM>;
 652                 clock-names = "pwm";
 653                 status = "disabled";
 654         };
 655
 656         pwm1: pwm@ff680010 {
 657                 compatible = "rockchip,rk3288-pwm";
 658                 reg = <0xff680010 0x10>;
 659                 #pwm-cells = <3>;
 660                 pinctrl-names = "default";
 661                 pinctrl-0 = <&pwm1_pin>;
 662                 clocks = <&cru PCLK_PWM>;
 663                 clock-names = "pwm";
 664                 status = "disabled";
 665         };
 666
 667         pwm2: pwm@ff680020 {
 668                 compatible = "rockchip,rk3288-pwm";
 669                 reg = <0xff680020 0x10>;
 670                 #pwm-cells = <3>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&pwm2_pin>;
 673                 clocks = <&cru PCLK_PWM>;
 674                 clock-names = "pwm";
 675                 status = "disabled";
 676         };
 677
 678         pwm3: pwm@ff680030 {
 679                 compatible = "rockchip,rk3288-pwm";
 680                 reg = <0xff680030 0x10>;
 681                 #pwm-cells = <2>;
 682                 pinctrl-names = "default";
 683                 pinctrl-0 = <&pwm3_pin>;
 684                 clocks = <&cru PCLK_PWM>;
 685                 clock-names = "pwm";
 686                 status = "disabled";
 687         };
 688
 689         bus_intmem@ff700000 {
 690                 compatible = "mmio-sram";
 691                 reg = <0xff700000 0x18000>;
 692                 #address-cells = <1>;
 693                 #size-cells = <1>;
 694                 ranges = <0 0xff700000 0x18000>;
 695                 smp-sram@0 {
 696                         compatible = "rockchip,rk3066-smp-sram";
 697                         reg = <0x00 0x10>;
 698                 };
 699         };
 700
 701         sram@ff720000 {
 702                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 703                 reg = <0xff720000 0x1000>;
 704         };
 705
 706         qos_gpu_r: qos@ffaa0000 {
 707                 compatible = "syscon";
 708                 reg = <0xffaa0000 0x20>;
 709         };
 710
 711         qos_gpu_w: qos@ffaa0080 {
 712                 compatible = "syscon";
 713                 reg = <0xffaa0080 0x20>;
 714         };
 715
 716         qos_vio1_vop: qos@ffad0000 {
 717                 compatible = "syscon";
 718                 reg = <0xffad0000 0x20>;
 719         };
 720
 721         qos_vio1_isp_w0: qos@ffad0100 {
 722                 compatible = "syscon";
 723                 reg = <0xffad0100 0x20>;
 724         };
 725
 726         qos_vio1_isp_w1: qos@ffad0180 {
 727                 compatible = "syscon";
 728                 reg = <0xffad0180 0x20>;
 729         };
 730
 731         qos_vio0_vop: qos@ffad0400 {
 732                 compatible = "syscon";
 733                 reg = <0xffad0400 0x20>;
 734         };
 735
 736         qos_vio0_vip: qos@ffad0480 {
 737                 compatible = "syscon";
 738                 reg = <0xffad0480 0x20>;
 739         };
 740
 741         qos_vio0_iep: qos@ffad0500 {
 742                 compatible = "syscon";
 743                 reg = <0xffad0500 0x20>;
 744         };
 745
 746         qos_vio2_rga_r: qos@ffad0800 {
 747                 compatible = "syscon";
 748                 reg = <0xffad0800 0x20>;
 749         };
 750
 751         qos_vio2_rga_w: qos@ffad0880 {
 752                 compatible = "syscon";
 753                 reg = <0xffad0880 0x20>;
 754         };
 755
 756         qos_vio1_isp_r: qos@ffad0900 {
 757                 compatible = "syscon";
 758                 reg = <0xffad0900 0x20>;
 759         };
 760
 761         qos_video: qos@ffae0000 {
 762                 compatible = "syscon";
 763                 reg = <0xffae0000 0x20>;
 764         };
 765
 766         qos_hevc_r: qos@ffaf0000 {
 767                 compatible = "syscon";
 768                 reg = <0xffaf0000 0x20>;
 769         };
 770
 771         qos_hevc_w: qos@ffaf0080 {
 772                 compatible = "syscon";
 773                 reg = <0xffaf0080 0x20>;
 774         };
 775
 776         pmu: power-management@ff730000 {
 777                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 778                 reg = <0xff730000 0x100>;
 779
 780                 power: power-controller {
 781                         compatible = "rockchip,rk3288-power-controller";
 782                         #power-domain-cells = <1>;
 783                         #address-cells = <1>;
 784                         #size-cells = <0>;
 785
 786                         /*
 787                          * Note: Although SCLK_* are the working clocks
 788                          * of device without including on the NOC, needed for
 789                          * synchronous reset.
 790                          *
 791                          * The clocks on the which NOC:
 792                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 793                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 794                          * ACLK_RGA is on ACLK_RGA_NIU.
 795                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 796                          *
 797                          * Which clock are device clocks:
 798                          *      clocks          devices
 799                          *      *_IEP           IEP:Image Enhancement Processor
 800                          *      *_ISP           ISP:Image Signal Processing
 801                          *      *_VIP           VIP:Video Input Processor
 802                          *      *_VOP*          VOP:Visual Output Processor
 803                          *      *_RGA           RGA
 804                          *      *_EDP*          EDP
 805                          *      *_LVDS_*        LVDS
 806                          *      *_HDMI          HDMI
 807                          *      *_MIPI_*        MIPI
 808                          */
 809                         pd_vio@RK3288_PD_VIO {
 810                                 reg = <RK3288_PD_VIO>;
 811                                 clocks = <&cru ACLK_IEP>,
 812                                          <&cru ACLK_ISP>,
 813                                          <&cru ACLK_RGA>,
 814                                          <&cru ACLK_VIP>,
 815                                          <&cru ACLK_VOP0>,
 816                                          <&cru ACLK_VOP1>,
 817                                          <&cru DCLK_VOP0>,
 818                                          <&cru DCLK_VOP1>,
 819                                          <&cru HCLK_IEP>,
 820                                          <&cru HCLK_ISP>,
 821                                          <&cru HCLK_RGA>,
 822                                          <&cru HCLK_VIP>,
 823                                          <&cru HCLK_VOP0>,
 824                                          <&cru HCLK_VOP1>,
 825                                          <&cru PCLK_EDP_CTRL>,
 826                                          <&cru PCLK_HDMI_CTRL>,
 827                                          <&cru PCLK_LVDS_PHY>,
 828                                          <&cru PCLK_MIPI_CSI>,
 829                                          <&cru PCLK_MIPI_DSI0>,
 830                                          <&cru PCLK_MIPI_DSI1>,
 831                                          <&cru SCLK_EDP_24M>,
 832                                          <&cru SCLK_EDP>,
 833                                          <&cru SCLK_ISP_JPE>,
 834                                          <&cru SCLK_ISP>,
 835                                          <&cru SCLK_RGA>;
 836                                 pm_qos = <&qos_vio0_iep>,
 837                                          <&qos_vio1_vop>,
 838                                          <&qos_vio1_isp_w0>,
 839                                          <&qos_vio1_isp_w1>,
 840                                          <&qos_vio0_vop>,
 841                                          <&qos_vio0_vip>,
 842                                          <&qos_vio2_rga_r>,
 843                                          <&qos_vio2_rga_w>,
 844                                          <&qos_vio1_isp_r>;
 845                         };
 846
 847                         /*
 848                          * Note: The following 3 are HEVC(H.265) clocks,
 849                          * and on the ACLK_HEVC_NIU (NOC).
 850                          */
 851                         pd_hevc@RK3288_PD_HEVC {
 852                                 reg = <RK3288_PD_HEVC>;
 853                                 clocks = <&cru ACLK_HEVC>,
 854                                          <&cru SCLK_HEVC_CABAC>,
 855                                          <&cru SCLK_HEVC_CORE>;
 856                                 pm_qos = <&qos_hevc_r>,
 857                                          <&qos_hevc_w>;
 858                         };
 859
 860                         /*
 861                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 862                          * (video endecoder & decoder) clocks that on the
 863                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 864                          */
 865                         pd_video@RK3288_PD_VIDEO {
 866                                 reg = <RK3288_PD_VIDEO>;
 867                                 clocks = <&cru ACLK_VCODEC>,
 868                                          <&cru HCLK_VCODEC>;
 869                                 pm_qos = <&qos_video>;
 870                         };
 871
 872                         /*
 873                          * Note: ACLK_GPU is the GPU clock,
 874                          * and on the ACLK_GPU_NIU (NOC).
 875                          */
 876                         pd_gpu@RK3288_PD_GPU {
 877                                 reg = <RK3288_PD_GPU>;
 878                                 clocks = <&cru ACLK_GPU>;
 879                                 pm_qos = <&qos_gpu_r>,
 880                                          <&qos_gpu_w>;
 881                         };
 882                 };
 883
 884                 reboot-mode {
 885                         compatible = "syscon-reboot-mode";
 886                         offset = <0x94>;
 887                         mode-normal = <BOOT_NORMAL>;
 888                         mode-recovery = <BOOT_RECOVERY>;
 889                         mode-bootloader = <BOOT_FASTBOOT>;
 890                         mode-loader = <BOOT_LOADER>;
 891                         mode-ums = <BOOT_UMS>;
 892                 };
 893         };
 894
 895         sgrf: syscon@ff740000 {
 896                 compatible = "rockchip,rk3288-sgrf", "syscon";
 897                 reg = <0xff740000 0x1000>;
 898         };
 899
 900         cru: clock-controller@ff760000 {
 901                 compatible = "rockchip,rk3288-cru";
 902                 reg = <0xff760000 0x1000>;
 903                 rockchip,grf = <&grf>;
 904                 #clock-cells = <1>;
 905                 #reset-cells = <1>;
 906                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 907                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 908                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 909                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 910                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 911                                   <&cru PCLK_PERI>;
 912                 assigned-clock-rates = <0>, <0>,
 913                                        <594000000>, <400000000>,
 914                                        <500000000>, <300000000>,
 915                                        <150000000>, <75000000>,
 916                                        <300000000>, <150000000>,
 917                                        <75000000>;
 918                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 919         };
 920
 921         grf: syscon@ff770000 {
 922                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 923                 reg = <0xff770000 0x1000>;
 924
 925                 edp_phy: edp-phy {
 926                         compatible = "rockchip,rk3288-dp-phy";
 927                         clocks = <&cru SCLK_EDP_24M>;
 928                         clock-names = "24m";
 929                         #phy-cells = <0>;
 930                         status = "disabled";
 931                 };
 932
 933                 io_domains: io-domains {
 934                         compatible = "rockchip,rk3288-io-voltage-domain";
 935                         status = "disabled";
 936                 };
 937
 938                 usbphy: usbphy {
 939                         compatible = "rockchip,rk3288-usb-phy";
 940                         #address-cells = <1>;
 941                         #size-cells = <0>;
 942                         status = "disabled";
 943
 944                         usbphy0: usb-phy@320 {
 945                                 #phy-cells = <0>;
 946                                 reg = <0x320>;
 947                                 clocks = <&cru SCLK_OTGPHY0>;
 948                                 clock-names = "phyclk";
 949                                 #clock-cells = <0>;
 950                                 resets = <&cru SRST_USBOTG_PHY>;
 951                                 reset-names = "phy-reset";
 952                         };
 953
 954                         usbphy1: usb-phy@334 {
 955                                 #phy-cells = <0>;
 956                                 reg = <0x334>;
 957                                 clocks = <&cru SCLK_OTGPHY1>;
 958                                 clock-names = "phyclk";
 959                                 #clock-cells = <0>;
 960                         };
 961
 962                         usbphy2: usb-phy@348 {
 963                                 #phy-cells = <0>;
 964                                 reg = <0x348>;
 965                                 clocks = <&cru SCLK_OTGPHY2>;
 966                                 clock-names = "phyclk";
 967                                 #clock-cells = <0>;
 968                                 resets = <&cru SRST_USBHOST1_PHY>;
 969                                 reset-names = "phy-reset";
 970                         };
 971                 };
 972         };
 973
 974         wdt: watchdog@ff800000 {
 975                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 976                 reg = <0xff800000 0x100>;
 977                 clocks = <&cru PCLK_WDT>;
 978                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 979                 status = "disabled";
 980         };
 981
 982         spdif: sound@ff88b0000 {
 983                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 984                 reg = <0xff8b0000 0x10000>;
 985                 #sound-dai-cells = <0>;
 986                 clock-names = "hclk", "mclk";
 987                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 988                 dmas = <&dmac_bus_s 3>;
 989                 dma-names = "tx";
 990                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 991                 pinctrl-names = "default";
 992                 pinctrl-0 = <&spdif_tx>;
 993                 rockchip,grf = <&grf>;
 994                 status = "disabled";
 995         };
 996
 997         i2s: i2s@ff890000 {
 998                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 999                 reg = <0xff890000 0x10000>;
1000                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1001                 #address-cells = <1>;
1002                 #size-cells = <0>;
1003                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1004                 dma-names = "tx", "rx";
1005                 clock-names = "i2s_hclk", "i2s_clk";
1006                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1007                 pinctrl-names = "default";
1008                 pinctrl-0 = <&i2s0_bus>;
1009                 rockchip,playback-channels = <8>;
1010                 rockchip,capture-channels = <2>;
1011                 status = "disabled";
1012         };
1013
1014         vopb: vop@ff930000 {
1015                 compatible = "rockchip,rk3288-vop";
1016                 reg = <0xff930000 0x19c>;
1017                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1019                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1020                 power-domains = <&power RK3288_PD_VIO>;
1021                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1022                 reset-names = "axi", "ahb", "dclk";
1023                 iommus = <&vopb_mmu>;
1024                 status = "disabled";
1025
1026                 vopb_out: port {
1027                         #address-cells = <1>;
1028                         #size-cells = <0>;
1029
1030                         vopb_out_hdmi: endpoint@0 {
1031                                 reg = <0>;
1032                                 remote-endpoint = <&hdmi_in_vopb>;
1033                         };
1034
1035                         vopb_out_edp: endpoint@1 {
1036                                 reg = <1>;
1037                                 remote-endpoint = <&edp_in_vopb>;
1038                         };
1039
1040                         vopb_out_mipi: endpoint@2 {
1041                                 reg = <2>;
1042                                 remote-endpoint = <&mipi_in_vopb>;
1043                         };
1044
1045                         vopb_out_lvds: endpoint@3 {
1046                                 reg = <3>;
1047                                 remote-endpoint = <&lvds_in_vopb>;
1048                         };
1049                 };
1050         };
1051
1052         vopb_mmu: iommu@ff930300 {
1053                 compatible = "rockchip,iommu";
1054                 reg = <0xff930300 0x100>;
1055                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1056                 interrupt-names = "vopb_mmu";
1057                 power-domains = <&power RK3288_PD_VIO>;
1058                 #iommu-cells = <0>;
1059                 status = "disabled";
1060         };
1061
1062         vopl: vop@ff940000 {
1063                 compatible = "rockchip,rk3288-vop";
1064                 reg = <0xff940000 0x19c>;
1065                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1066                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1067                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1068                 power-domains = <&power RK3288_PD_VIO>;
1069                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1070                 reset-names = "axi", "ahb", "dclk";
1071                 iommus = <&vopl_mmu>;
1072                 status = "disabled";
1073
1074                 vopl_out: port {
1075                         #address-cells = <1>;
1076                         #size-cells = <0>;
1077
1078                         vopl_out_hdmi: endpoint@0 {
1079                                 reg = <0>;
1080                                 remote-endpoint = <&hdmi_in_vopl>;
1081                         };
1082
1083                         vopl_out_edp: endpoint@1 {
1084                                 reg = <1>;
1085                                 remote-endpoint = <&edp_in_vopl>;
1086                         };
1087
1088                         vopl_out_mipi: endpoint@2 {
1089                                 reg = <2>;
1090                                 remote-endpoint = <&mipi_in_vopl>;
1091                         };
1092
1093                         vopl_out_lvds: endpoint@3 {
1094                                 reg = <3>;
1095                                 remote-endpoint = <&lvds_in_vopl>;
1096                         };
1097
1098                 };
1099         };
1100
1101         vopl_mmu: iommu@ff940300 {
1102                 compatible = "rockchip,iommu";
1103                 reg = <0xff940300 0x100>;
1104                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1105                 interrupt-names = "vopl_mmu";
1106                 power-domains = <&power RK3288_PD_VIO>;
1107                 #iommu-cells = <0>;
1108                 status = "disabled";
1109         };
1110
1111         mipi_dsi: mipi@ff960000 {
1112                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1113                 reg = <0xff960000 0x4000>;
1114                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1115                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1116                 clock-names = "ref", "pclk";
1117                 power-domains = <&power RK3288_PD_VIO>;
1118                 rockchip,grf = <&grf>;
1119                 #address-cells = <1>;
1120                 #size-cells = <0>;
1121                 status = "disabled";
1122
1123                 ports {
1124                         mipi_in: port {
1125                                 #address-cells = <1>;
1126                                 #size-cells = <0>;
1127                                 mipi_in_vopb: endpoint@0 {
1128                                         reg = <0>;
1129                                         remote-endpoint = <&vopb_out_mipi>;
1130                                 };
1131                                 mipi_in_vopl: endpoint@1 {
1132                                         reg = <1>;
1133                                         remote-endpoint = <&vopl_out_mipi>;
1134                                 };
1135                         };
1136                 };
1137         };
1138
1139         edp: dp@ff970000 {
1140                 compatible = "rockchip,rk3288-dp";
1141                 reg = <0xff970000 0x4000>;
1142                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1143                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1144                 clock-names = "dp", "pclk";
1145                 phys = <&edp_phy>;
1146                 phy-names = "dp";
1147                 resets = <&cru SRST_EDP>;
1148                 reset-names = "dp";
1149                 rockchip,grf = <&grf>;
1150                 status = "disabled";
1151
1152                 ports {
1153                         #address-cells = <1>;
1154                         #size-cells = <0>;
1155                         edp_in: port@0 {
1156                                 reg = <0>;
1157                                 #address-cells = <1>;
1158                                 #size-cells = <0>;
1159                                 edp_in_vopb: endpoint@0 {
1160                                         reg = <0>;
1161                                         remote-endpoint = <&vopb_out_edp>;
1162                                 };
1163                                 edp_in_vopl: endpoint@1 {
1164                                         reg = <1>;
1165                                         remote-endpoint = <&vopl_out_edp>;
1166                                 };
1167                         };
1168                 };
1169         };
1170
1171         lvds: lvds@ff96c000 {
1172                 compatible = "rockchip,rk3288-lvds";
1173                 reg = <0xff96c000 0x4000>;
1174                 clocks = <&cru PCLK_LVDS_PHY>;
1175                 clock-names = "pclk_lvds";
1176                 pinctrl-names = "default";
1177                 pinctrl-0 = <&lcdc0_ctl>;
1178                 power-domains = <&power RK3288_PD_VIO>;
1179                 rockchip,grf = <&grf>;
1180                 status = "disabled";
1181
1182                 ports {
1183                         #address-cells = <1>;
1184                         #size-cells = <0>;
1185
1186                         lvds_in: port@0 {
1187                                 reg = <0>;
1188
1189                                 #address-cells = <1>;
1190                                 #size-cells = <0>;
1191
1192                                 lvds_in_vopb: endpoint@0 {
1193                                         reg = <0>;
1194                                         remote-endpoint = <&vopb_out_lvds>;
1195                                 };
1196                                 lvds_in_vopl: endpoint@1 {
1197                                         reg = <1>;
1198                                         remote-endpoint = <&vopl_out_lvds>;
1199                                 };
1200                         };
1201                 };
1202         };
1203
1204         hdmi: hdmi@ff980000 {
1205                 compatible = "rockchip,rk3288-dw-hdmi";
1206                 reg = <0xff980000 0x20000>;
1207                 reg-io-width = <4>;
1208                 rockchip,grf = <&grf>;
1209                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1210                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1211                 clock-names = "iahb", "isfr";
1212                 power-domains = <&power RK3288_PD_VIO>;
1213                 status = "disabled";
1214
1215                 ports {
1216                         hdmi_in: port {
1217                                 #address-cells = <1>;
1218                                 #size-cells = <0>;
1219                                 hdmi_in_vopb: endpoint@0 {
1220                                         reg = <0>;
1221                                         remote-endpoint = <&vopb_out_hdmi>;
1222                                 };
1223                                 hdmi_in_vopl: endpoint@1 {
1224                                         reg = <1>;
1225                                         remote-endpoint = <&vopl_out_hdmi>;
1226                                 };
1227                         };
1228                 };
1229         };
1230
1231         gpu: gpu@ffa30000 {
1232                 compatible = "arm,malit764",
1233                              "arm,malit76x",
1234                              "arm,malit7xx",
1235                              "arm,mali-midgard";
1236                 reg = <0xffa30000 0x10000>;
1237                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1238                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1239                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1240                 interrupt-names = "JOB", "MMU", "GPU";
1241                 clocks = <&cru ACLK_GPU>;
1242                 clock-names = "clk_mali";
1243                 operating-points = <
1244                         /* KHz uV */
1245                         600000 1250000
1246                         /* 500000 1200000 - See crosbug.com/p/33857 */
1247                         400000 1100000
1248                         300000 1000000
1249                         200000 950000
1250                         100000 950000
1251                 >;
1252                 #cooling-cells = <2>; /* min followed by max */
1253                 power-domains = <&power RK3288_PD_GPU>;
1254                 status = "disabled";
1255         };
1256
1257         vpu: video-codec@ff9a0000 {
1258                 compatible = "rockchip,rk3288-vpu";
1259                 reg = <0xff9a0000 0x800>;
1260                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1261                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1262                 interrupt-names = "vepu", "vdpu";
1263                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1264                 clock-names = "aclk", "hclk";
1265                 power-domains = <&power RK3288_PD_VIDEO>;
1266                 iommus = <&vpu_mmu>;
1267                 assigned-clocks = <&cru ACLK_VCODEC>;
1268                 assigned-clock-rates = <400000000>;
1269                 status = "disabled";
1270         };
1271
1272         vpu_service: vpu-service@ff9a0000 {
1273                 compatible = "rockchip,vpu_service";
1274                 reg = <0xff9a0000 0x800>;
1275                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1276                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1277                 interrupt-names = "irq_enc", "irq_dec";
1278                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1279                 clock-names = "aclk_vcodec", "hclk_vcodec";
1280                 power-domains = <&power RK3288_PD_VIDEO>;
1281                 rockchip,grf = <&grf>;
1282                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1283                 reset-names = "video_a", "video_h";
1284                 iommus = <&vpu_mmu>;
1285                 iommu_enabled = <1>;
1286                 dev_mode = <0>;
1287                 status = "disabled";
1288         };
1289
1290         vpu_mmu: iommu@ff9a0800 {
1291                 compatible = "rockchip,iommu";
1292                 reg = <0xff9a0800 0x100>;
1293                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1294                 interrupt-names = "vpu_mmu";
1295                 power-domains = <&power RK3288_PD_VIDEO>;
1296                 #iommu-cells = <0>;
1297         };
1298
1299         hevc_service: hevc-service@ff9c0000 {
1300                 compatible = "rockchip,hevc_service";
1301                 reg = <0xff9c0000 0x400>;
1302                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1303                 interrupt-names = "irq_dec";
1304                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1305                         <&cru SCLK_HEVC_CORE>,
1306                         <&cru SCLK_HEVC_CABAC>;
1307                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1308                         "clk_cabac";
1309                 /*
1310                  * The 4K hevc would also work well with 500/125/300/300,
1311                  * no more err irq and reset request.
1312                  */
1313                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1314                                   <&cru SCLK_HEVC_CORE>,
1315                                   <&cru SCLK_HEVC_CABAC>;
1316                 assigned-clock-rates = <400000000>, <100000000>,
1317                                        <300000000>, <300000000>;
1318
1319                 resets = <&cru SRST_HEVC>;
1320                 reset-names = "video";
1321                 power-domains = <&power RK3288_PD_HEVC>;
1322                 rockchip,grf = <&grf>;
1323                 dev_mode = <1>;
1324                 iommus = <&hevc_mmu>;
1325                 iommu_enabled = <1>;
1326                 status = "disabled";
1327         };
1328
1329         hevc_mmu: iommu@ff9c0440 {
1330                 compatible = "rockchip,iommu";
1331                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1332                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1333                 interrupt-names = "hevc_mmu";
1334                 power-domains = <&power RK3288_PD_HEVC>;
1335                 #iommu-cells = <0>;
1336         };
1337
1338         gic: interrupt-controller@ffc01000 {
1339                 compatible = "arm,gic-400";
1340                 interrupt-controller;
1341                 #interrupt-cells = <3>;
1342                 #address-cells = <0>;
1343
1344                 reg = <0xffc01000 0x1000>,
1345                       <0xffc02000 0x1000>,
1346                       <0xffc04000 0x2000>,
1347                       <0xffc06000 0x2000>;
1348                 interrupts = <GIC_PPI 9 0xf04>;
1349         };
1350
1351         efuse: efuse@ffb40000 {
1352                 compatible = "rockchip,rockchip-efuse";
1353                 reg = <0xffb40000 0x20>;
1354                 #address-cells = <1>;
1355                 #size-cells = <1>;
1356                 clocks = <&cru PCLK_EFUSE256>;
1357                 clock-names = "pclk_efuse";
1358
1359                 cpu_leakage: cpu_leakage@17 {
1360                         reg = <0x17 0x1>;
1361                 };
1362         };
1363
1364         cif_isp0: cif_isp@ff910000 {
1365                 compatible = "rockchip,rk3288-cif-isp";
1366                 rockchip,grf = <&grf>;
1367                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1368                 reg-names = "register", "csihost-register";
1369                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1370                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1371                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1372                         <&cru SCLK_MIPIDSI_24M>;
1373                 clock-names = "aclk_isp", "hclk_isp",
1374                         "sclk_isp", "sclk_isp_jpe",
1375                         "pclk_mipi_csi", "pclk_isp_in",
1376                         "sclk_mipidsi_24m";
1377                 resets = <&cru SRST_ISP>;
1378                 reset-names = "rst_isp";
1379                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1380                 interrupt-names = "cif_isp10_irq";
1381                 status = "disabled";
1382         };
1383
1384         pinctrl: pinctrl {
1385                 compatible = "rockchip,rk3288-pinctrl";
1386                 rockchip,grf = <&grf>;
1387                 rockchip,pmu = <&pmu>;
1388                 #address-cells = <1>;
1389                 #size-cells = <1>;
1390                 ranges;
1391
1392                 gpio0: gpio0@ff750000 {
1393                         compatible = "rockchip,gpio-bank";
1394                         reg =   <0xff750000 0x100>;
1395                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1396                         clocks = <&cru PCLK_GPIO0>;
1397
1398                         gpio-controller;
1399                         #gpio-cells = <2>;
1400
1401                         interrupt-controller;
1402                         #interrupt-cells = <2>;
1403                 };
1404
1405                 gpio1: gpio1@ff780000 {
1406                         compatible = "rockchip,gpio-bank";
1407                         reg = <0xff780000 0x100>;
1408                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1409                         clocks = <&cru PCLK_GPIO1>;
1410
1411                         gpio-controller;
1412                         #gpio-cells = <2>;
1413
1414                         interrupt-controller;
1415                         #interrupt-cells = <2>;
1416                 };
1417
1418                 gpio2: gpio2@ff790000 {
1419                         compatible = "rockchip,gpio-bank";
1420                         reg = <0xff790000 0x100>;
1421                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1422                         clocks = <&cru PCLK_GPIO2>;
1423
1424                         gpio-controller;
1425                         #gpio-cells = <2>;
1426
1427                         interrupt-controller;
1428                         #interrupt-cells = <2>;
1429                 };
1430
1431                 gpio3: gpio3@ff7a0000 {
1432                         compatible = "rockchip,gpio-bank";
1433                         reg = <0xff7a0000 0x100>;
1434                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1435                         clocks = <&cru PCLK_GPIO3>;
1436
1437                         gpio-controller;
1438                         #gpio-cells = <2>;
1439
1440                         interrupt-controller;
1441                         #interrupt-cells = <2>;
1442                 };
1443
1444                 gpio4: gpio4@ff7b0000 {
1445                         compatible = "rockchip,gpio-bank";
1446                         reg = <0xff7b0000 0x100>;
1447                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1448                         clocks = <&cru PCLK_GPIO4>;
1449
1450                         gpio-controller;
1451                         #gpio-cells = <2>;
1452
1453                         interrupt-controller;
1454                         #interrupt-cells = <2>;
1455                 };
1456
1457                 gpio5: gpio5@ff7c0000 {
1458                         compatible = "rockchip,gpio-bank";
1459                         reg = <0xff7c0000 0x100>;
1460                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1461                         clocks = <&cru PCLK_GPIO5>;
1462
1463                         gpio-controller;
1464                         #gpio-cells = <2>;
1465
1466                         interrupt-controller;
1467                         #interrupt-cells = <2>;
1468                 };
1469
1470                 gpio6: gpio6@ff7d0000 {
1471                         compatible = "rockchip,gpio-bank";
1472                         reg = <0xff7d0000 0x100>;
1473                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1474                         clocks = <&cru PCLK_GPIO6>;
1475
1476                         gpio-controller;
1477                         #gpio-cells = <2>;
1478
1479                         interrupt-controller;
1480                         #interrupt-cells = <2>;
1481                 };
1482
1483                 gpio7: gpio7@ff7e0000 {
1484                         compatible = "rockchip,gpio-bank";
1485                         reg = <0xff7e0000 0x100>;
1486                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1487                         clocks = <&cru PCLK_GPIO7>;
1488
1489                         gpio-controller;
1490                         #gpio-cells = <2>;
1491
1492                         interrupt-controller;
1493                         #interrupt-cells = <2>;
1494                 };
1495
1496                 gpio8: gpio8@ff7f0000 {
1497                         compatible = "rockchip,gpio-bank";
1498                         reg = <0xff7f0000 0x100>;
1499                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1500                         clocks = <&cru PCLK_GPIO8>;
1501
1502                         gpio-controller;
1503                         #gpio-cells = <2>;
1504
1505                         interrupt-controller;
1506                         #interrupt-cells = <2>;
1507                 };
1508
1509                 hdmi {
1510                         hdmi_ddc: hdmi-ddc {
1511                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1512                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1513                         };
1514                 };
1515
1516                 pcfg_pull_up: pcfg-pull-up {
1517                         bias-pull-up;
1518                 };
1519
1520                 pcfg_pull_down: pcfg-pull-down {
1521                         bias-pull-down;
1522                 };
1523
1524                 pcfg_pull_none: pcfg-pull-none {
1525                         bias-disable;
1526                 };
1527
1528                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1529                         bias-disable;
1530                         drive-strength = <12>;
1531                 };
1532
1533                 sleep {
1534                         global_pwroff: global-pwroff {
1535                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1536                         };
1537
1538                         ddrio_pwroff: ddrio-pwroff {
1539                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1540                         };
1541
1542                         ddr0_retention: ddr0-retention {
1543                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1544                         };
1545
1546                         ddr1_retention: ddr1-retention {
1547                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1548                         };
1549                 };
1550
1551                 edp {
1552                         edp_hpd: edp-hpd {
1553                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1554                         };
1555                 };
1556
1557                 i2c0 {
1558                         i2c0_xfer: i2c0-xfer {
1559                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1560                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1561                         };
1562                 };
1563
1564                 i2c1 {
1565                         i2c1_xfer: i2c1-xfer {
1566                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1567                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1568                         };
1569                 };
1570
1571                 i2c2 {
1572                         i2c2_xfer: i2c2-xfer {
1573                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1574                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1575                         };
1576                 };
1577
1578                 i2c3 {
1579                         i2c3_xfer: i2c3-xfer {
1580                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1581                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1582                         };
1583                 };
1584
1585                 i2c4 {
1586                         i2c4_xfer: i2c4-xfer {
1587                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1588                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1589                         };
1590                 };
1591
1592                 i2c5 {
1593                         i2c5_xfer: i2c5-xfer {
1594                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1595                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1596                         };
1597                 };
1598
1599                 i2s0 {
1600                         i2s0_bus: i2s0-bus {
1601                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1602                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1603                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1604                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1605                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1606                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1607                         };
1608                 };
1609
1610                 lcdc0 {
1611                         lcdc0_ctl: lcdc0-ctl {
1612                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1613                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1614                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1615                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1616                         };
1617                 };
1618
1619                 sdmmc {
1620                         sdmmc_clk: sdmmc-clk {
1621                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1622                         };
1623
1624                         sdmmc_cmd: sdmmc-cmd {
1625                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1626                         };
1627
1628                         sdmmc_cd: sdmcc-cd {
1629                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1630                         };
1631
1632                         sdmmc_bus1: sdmmc-bus1 {
1633                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1634                         };
1635
1636                         sdmmc_bus4: sdmmc-bus4 {
1637                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1638                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1639                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1640                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1641                         };
1642                 };
1643
1644                 sdio0 {
1645                         sdio0_bus1: sdio0-bus1 {
1646                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1647                         };
1648
1649                         sdio0_bus4: sdio0-bus4 {
1650                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1651                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1652                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1653                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1654                         };
1655
1656                         sdio0_cmd: sdio0-cmd {
1657                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1658                         };
1659
1660                         sdio0_clk: sdio0-clk {
1661                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1662                         };
1663
1664                         sdio0_cd: sdio0-cd {
1665                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1666                         };
1667
1668                         sdio0_wp: sdio0-wp {
1669                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1670                         };
1671
1672                         sdio0_pwr: sdio0-pwr {
1673                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1674                         };
1675
1676                         sdio0_bkpwr: sdio0-bkpwr {
1677                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1678                         };
1679
1680                         sdio0_int: sdio0-int {
1681                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1682                         };
1683                 };
1684
1685                 sdio1 {
1686                         sdio1_bus1: sdio1-bus1 {
1687                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1688                         };
1689
1690                         sdio1_bus4: sdio1-bus4 {
1691                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1692                                                 <3 25 4 &pcfg_pull_up>,
1693                                                 <3 26 4 &pcfg_pull_up>,
1694                                                 <3 27 4 &pcfg_pull_up>;
1695                         };
1696
1697                         sdio1_cd: sdio1-cd {
1698                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1699                         };
1700
1701                         sdio1_wp: sdio1-wp {
1702                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1703                         };
1704
1705                         sdio1_bkpwr: sdio1-bkpwr {
1706                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1707                         };
1708
1709                         sdio1_int: sdio1-int {
1710                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1711                         };
1712
1713                         sdio1_cmd: sdio1-cmd {
1714                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1715                         };
1716
1717                         sdio1_clk: sdio1-clk {
1718                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1719                         };
1720
1721                         sdio1_pwr: sdio1-pwr {
1722                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1723                         };
1724                 };
1725
1726                 emmc {
1727                         emmc_clk: emmc-clk {
1728                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1729                         };
1730
1731                         emmc_cmd: emmc-cmd {
1732                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1733                         };
1734
1735                         emmc_pwr: emmc-pwr {
1736                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1737                         };
1738
1739                         emmc_bus1: emmc-bus1 {
1740                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1741                         };
1742
1743                         emmc_bus4: emmc-bus4 {
1744                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1745                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1746                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1747                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1748                         };
1749
1750                         emmc_bus8: emmc-bus8 {
1751                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1752                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1753                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1754                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1755                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1756                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1757                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1758                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1759                         };
1760                 };
1761
1762                 spi0 {
1763                         spi0_clk: spi0-clk {
1764                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1765                         };
1766                         spi0_cs0: spi0-cs0 {
1767                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1768                         };
1769                         spi0_tx: spi0-tx {
1770                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1771                         };
1772                         spi0_rx: spi0-rx {
1773                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1774                         };
1775                         spi0_cs1: spi0-cs1 {
1776                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1777                         };
1778                 };
1779                 spi1 {
1780                         spi1_clk: spi1-clk {
1781                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1782                         };
1783                         spi1_cs0: spi1-cs0 {
1784                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1785                         };
1786                         spi1_rx: spi1-rx {
1787                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1788                         };
1789                         spi1_tx: spi1-tx {
1790                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1791                         };
1792                 };
1793
1794                 spi2 {
1795                         spi2_cs1: spi2-cs1 {
1796                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1797                         };
1798                         spi2_clk: spi2-clk {
1799                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1800                         };
1801                         spi2_cs0: spi2-cs0 {
1802                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1803                         };
1804                         spi2_rx: spi2-rx {
1805                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1806                         };
1807                         spi2_tx: spi2-tx {
1808                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1809                         };
1810                 };
1811
1812                 uart0 {
1813                         uart0_xfer: uart0-xfer {
1814                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1815                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1816                         };
1817
1818                         uart0_cts: uart0-cts {
1819                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1820                         };
1821
1822                         uart0_rts: uart0-rts {
1823                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1824                         };
1825                 };
1826
1827                 uart1 {
1828                         uart1_xfer: uart1-xfer {
1829                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1830                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1831                         };
1832
1833                         uart1_cts: uart1-cts {
1834                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1835                         };
1836
1837                         uart1_rts: uart1-rts {
1838                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1839                         };
1840                 };
1841
1842                 uart2 {
1843                         uart2_xfer: uart2-xfer {
1844                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1845                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1846                         };
1847                         /* no rts / cts for uart2 */
1848                 };
1849
1850                 uart3 {
1851                         uart3_xfer: uart3-xfer {
1852                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1853                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1854                         };
1855
1856                         uart3_cts: uart3-cts {
1857                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1858                         };
1859
1860                         uart3_rts: uart3-rts {
1861                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1862                         };
1863                 };
1864
1865                 uart4 {
1866                         uart4_xfer: uart4-xfer {
1867                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1868                                                 <5 13 3 &pcfg_pull_none>;
1869                         };
1870
1871                         uart4_cts: uart4-cts {
1872                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1873                         };
1874
1875                         uart4_rts: uart4-rts {
1876                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1877                         };
1878                 };
1879
1880                 tsadc {
1881                         otp_gpio: otp-gpio {
1882                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1883                         };
1884
1885                         otp_out: otp-out {
1886                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1887                         };
1888                 };
1889
1890                 pwm0 {
1891                         pwm0_pin: pwm0-pin {
1892                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1893                         };
1894                 };
1895
1896                 pwm1 {
1897                         pwm1_pin: pwm1-pin {
1898                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1899                         };
1900                 };
1901
1902                 pwm2 {
1903                         pwm2_pin: pwm2-pin {
1904                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1905                         };
1906                 };
1907
1908                 pwm3 {
1909                         pwm3_pin: pwm3-pin {
1910                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1911                         };
1912                 };
1913
1914                 gmac {
1915                         rgmii_pins: rgmii-pins {
1916                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1917                                                 <3 31 3 &pcfg_pull_none>,
1918                                                 <3 26 3 &pcfg_pull_none>,
1919                                                 <3 27 3 &pcfg_pull_none>,
1920                                                 <3 28 3 &pcfg_pull_none_12ma>,
1921                                                 <3 29 3 &pcfg_pull_none_12ma>,
1922                                                 <3 24 3 &pcfg_pull_none_12ma>,
1923                                                 <3 25 3 &pcfg_pull_none_12ma>,
1924                                                 <4 0 3 &pcfg_pull_none>,
1925                                                 <4 5 3 &pcfg_pull_none>,
1926                                                 <4 6 3 &pcfg_pull_none>,
1927                                                 <4 9 3 &pcfg_pull_none_12ma>,
1928                                                 <4 4 3 &pcfg_pull_none_12ma>,
1929                                                 <4 1 3 &pcfg_pull_none>,
1930                                                 <4 3 3 &pcfg_pull_none>;
1931                         };
1932
1933                         rmii_pins: rmii-pins {
1934                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1935                                                 <3 31 3 &pcfg_pull_none>,
1936                                                 <3 28 3 &pcfg_pull_none>,
1937                                                 <3 29 3 &pcfg_pull_none>,
1938                                                 <4 0 3 &pcfg_pull_none>,
1939                                                 <4 5 3 &pcfg_pull_none>,
1940                                                 <4 4 3 &pcfg_pull_none>,
1941                                                 <4 1 3 &pcfg_pull_none>,
1942                                                 <4 2 3 &pcfg_pull_none>,
1943                                                 <4 3 3 &pcfg_pull_none>;
1944                         };
1945                 };
1946
1947                 spdif {
1948                         spdif_tx: spdif-tx {
1949                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1950                         };
1951                 };
1952
1953                 cif {
1954                         cif_dvp_d2d9: cif-dvp-d2d9 {
1955                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
1956                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1957                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1958                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1959                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1960                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1961                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1962                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1963                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1964                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1965                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
1966                         };
1967                 };
1968         };
1969 };