arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 mshc0 = &emmc;
  65                 mshc1 = &sdmmc;
  66                 mshc2 = &sdio0;
  67                 mshc3 = &sdio1;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73                 spi0 = &spi0;
  74                 spi1 = &spi1;
  75                 spi2 = &spi2;
  76         };
  77
  78         arm-pmu {
  79                 compatible = "arm,cortex-a12-pmu";
  80                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  84                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  85         };
  86
  87         cpus {
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 enable-method = "rockchip,rk3066-smp";
  91                 rockchip,pmu = <&pmu>;
  92
  93                 cpu0: cpu@500 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a12";
  96                         reg = <0x500>;
  97                         resets = <&cru SRST_CORE0>;
  98                         operating-points-v2 = <&cpu0_opp_table>;
  99                         #cooling-cells = <2>; /* min followed by max */
 100                         clocks = <&cru ARMCLK>;
 101                 };
 102                 cpu1: cpu@501 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a12";
 105                         reg = <0x501>;
 106                         resets = <&cru SRST_CORE1>;
 107                         operating-points-v2 = <&cpu0_opp_table>;
 108                 };
 109                 cpu2: cpu@502 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a12";
 112                         reg = <0x502>;
 113                         resets = <&cru SRST_CORE2>;
 114                         operating-points-v2 = <&cpu0_opp_table>;
 115                 };
 116                 cpu3: cpu@503 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x503>;
 120                         resets = <&cru SRST_CORE3>;
 121                         operating-points-v2 = <&cpu0_opp_table>;
 122                 };
 123         };
 124
 125         cpu0_opp_table: opp_table0 {
 126                 compatible = "operating-points-v2";
 127                 opp-shared;
 128
 129                 opp@126000000 {
 130                         opp-hz = /bits/ 64 <126000000>;
 131                         opp-microvolt = <900000>;
 132                         clock-latency-ns = <40000>;
 133                 };
 134                 opp@216000000 {
 135                         opp-hz = /bits/ 64 <216000000>;
 136                         opp-microvolt = <900000>;
 137                         clock-latency-ns = <40000>;
 138                 };
 139                 opp@408000000 {
 140                         opp-hz = /bits/ 64 <408000000>;
 141                         opp-microvolt = <900000>;
 142                         clock-latency-ns = <40000>;
 143                 };
 144                 opp@600000000 {
 145                         opp-hz = /bits/ 64 <600000000>;
 146                         opp-microvolt = <900000>;
 147                         clock-latency-ns = <40000>;
 148                 };
 149                 opp@696000000 {
 150                         opp-hz = /bits/ 64 <696000000>;
 151                         opp-microvolt = <950000>;
 152                         clock-latency-ns = <40000>;
 153                 };
 154                 opp@816000000 {
 155                         opp-hz = /bits/ 64 <816000000>;
 156                         opp-microvolt = <1000000>;
 157                         clock-latency-ns = <40000>;
 158                         opp-suspend;
 159                 };
 160                 opp@1008000000 {
 161                         opp-hz = /bits/ 64 <1008000000>;
 162                         opp-microvolt = <1050000>;
 163                         clock-latency-ns = <40000>;
 164                 };
 165                 opp@1200000000 {
 166                         opp-hz = /bits/ 64 <1200000000>;
 167                         opp-microvolt = <1100000>;
 168                         clock-latency-ns = <40000>;
 169                 };
 170                 opp@1416000000 {
 171                         opp-hz = /bits/ 64 <1296000000>;
 172                         opp-microvolt = <1200000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp@1512000000 {
 176                         opp-hz = /bits/ 64 <1512000000>;
 177                         opp-microvolt = <1300000>;
 178                         clock-latency-ns = <40000>;
 179                 };
 180                 opp@1608000000 {
 181                         opp-hz = /bits/ 64 <1608000000>;
 182                         opp-microvolt = <1350000>;
 183                         clock-latency-ns = <40000>;
 184                 };
 185         };
 186
 187         amba {
 188                 compatible = "arm,amba-bus";
 189                 #address-cells = <1>;
 190                 #size-cells = <1>;
 191                 ranges;
 192
 193                 dmac_peri: dma-controller@ff250000 {
 194                         compatible = "arm,pl330", "arm,primecell";
 195                         reg = <0xff250000 0x4000>;
 196                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 197                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 198                         #dma-cells = <1>;
 199                         arm,pl330-broken-no-flushp;
 200                         peripherals-req-type-burst;
 201                         clocks = <&cru ACLK_DMAC2>;
 202                         clock-names = "apb_pclk";
 203                 };
 204
 205                 dmac_bus_ns: dma-controller@ff600000 {
 206                         compatible = "arm,pl330", "arm,primecell";
 207                         reg = <0xff600000 0x4000>;
 208                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 209                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 210                         #dma-cells = <1>;
 211                         arm,pl330-broken-no-flushp;
 212                         peripherals-req-type-burst;
 213                         clocks = <&cru ACLK_DMAC1>;
 214                         clock-names = "apb_pclk";
 215                         status = "disabled";
 216                 };
 217
 218                 dmac_bus_s: dma-controller@ffb20000 {
 219                         compatible = "arm,pl330", "arm,primecell";
 220                         reg = <0xffb20000 0x4000>;
 221                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 223                         #dma-cells = <1>;
 224                         arm,pl330-broken-no-flushp;
 225                         peripherals-req-type-burst;
 226                         clocks = <&cru ACLK_DMAC1>;
 227                         clock-names = "apb_pclk";
 228                 };
 229         };
 230
 231         reserved-memory {
 232                 #address-cells = <1>;
 233                 #size-cells = <1>;
 234                 ranges;
 235
 236                 /*
 237                  * The rk3288 cannot use the memory area above 0xfe000000
 238                  * for dma operations for some reason. While there is
 239                  * probably a better solution available somewhere, we
 240                  * haven't found it yet and while devices with 2GB of ram
 241                  * are not affected, this issue prevents 4GB from booting.
 242                  * So to make these devices at least bootable, block
 243                  * this area for the time being until the real solution
 244                  * is found.
 245                  */
 246                 dma-unusable@fe000000 {
 247                         reg = <0xfe000000 0x1000000>;
 248                 };
 249         };
 250
 251         xin24m: oscillator {
 252                 compatible = "fixed-clock";
 253                 clock-frequency = <24000000>;
 254                 clock-output-names = "xin24m";
 255                 #clock-cells = <0>;
 256         };
 257
 258         timer {
 259                 compatible = "arm,armv7-timer";
 260                 arm,cpu-registers-not-fw-configured;
 261                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 262                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 263                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 264                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 265                 clock-frequency = <24000000>;
 266         };
 267
 268         timer: timer@ff810000 {
 269                 compatible = "rockchip,rk3288-timer";
 270                 reg = <0xff810000 0x20>;
 271                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 272                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 273                 clock-names = "timer", "pclk";
 274         };
 275
 276         display-subsystem {
 277                 compatible = "rockchip,display-subsystem";
 278                 ports = <&vopl_out>, <&vopb_out>;
 279         };
 280
 281         sdmmc: dwmmc@ff0c0000 {
 282                 compatible = "rockchip,rk3288-dw-mshc";
 283                 clock-freq-min-max = <400000 150000000>;
 284                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 285                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 286                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 287                 fifo-depth = <0x100>;
 288                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 289                 reg = <0xff0c0000 0x4000>;
 290                 status = "disabled";
 291         };
 292
 293         sdio0: dwmmc@ff0d0000 {
 294                 compatible = "rockchip,rk3288-dw-mshc";
 295                 clock-freq-min-max = <400000 150000000>;
 296                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 297                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 298                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 299                 fifo-depth = <0x100>;
 300                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 301                 reg = <0xff0d0000 0x4000>;
 302                 status = "disabled";
 303         };
 304
 305         sdio1: dwmmc@ff0e0000 {
 306                 compatible = "rockchip,rk3288-dw-mshc";
 307                 clock-freq-min-max = <400000 150000000>;
 308                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 309                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 310                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 311                 fifo-depth = <0x100>;
 312                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 313                 reg = <0xff0e0000 0x4000>;
 314                 status = "disabled";
 315         };
 316
 317         emmc: dwmmc@ff0f0000 {
 318                 compatible = "rockchip,rk3288-dw-mshc";
 319                 clock-freq-min-max = <400000 150000000>;
 320                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 321                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 322                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 323                 fifo-depth = <0x100>;
 324                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 325                 reg = <0xff0f0000 0x4000>;
 326                 status = "disabled";
 327                 supports-emmc;
 328         };
 329
 330         saradc: saradc@ff100000 {
 331                 compatible = "rockchip,saradc";
 332                 reg = <0xff100000 0x100>;
 333                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 334                 #io-channel-cells = <1>;
 335                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 336                 clock-names = "saradc", "apb_pclk";
 337                 resets = <&cru SRST_SARADC>;
 338                 reset-names = "saradc-apb";
 339                 status = "disabled";
 340         };
 341
 342         spi0: spi@ff110000 {
 343                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 344                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 345                 clock-names = "spiclk", "apb_pclk";
 346                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 347                 dma-names = "tx", "rx";
 348                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 351                 reg = <0xff110000 0x1000>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 status = "disabled";
 355         };
 356
 357         spi1: spi@ff120000 {
 358                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 359                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 360                 clock-names = "spiclk", "apb_pclk";
 361                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 362                 dma-names = "tx", "rx";
 363                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 366                 reg = <0xff120000 0x1000>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 status = "disabled";
 370         };
 371
 372         spi2: spi@ff130000 {
 373                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 374                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 377                 dma-names = "tx", "rx";
 378                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 381                 reg = <0xff130000 0x1000>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 status = "disabled";
 385         };
 386
 387         i2c1: i2c@ff140000 {
 388                 compatible = "rockchip,rk3288-i2c";
 389                 reg = <0xff140000 0x1000>;
 390                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 clock-names = "i2c";
 394                 clocks = <&cru PCLK_I2C1>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&i2c1_xfer>;
 397                 status = "disabled";
 398         };
 399
 400         i2c3: i2c@ff150000 {
 401                 compatible = "rockchip,rk3288-i2c";
 402                 reg = <0xff150000 0x1000>;
 403                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clock-names = "i2c";
 407                 clocks = <&cru PCLK_I2C3>;
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&i2c3_xfer>;
 410                 status = "disabled";
 411         };
 412
 413         i2c4: i2c@ff160000 {
 414                 compatible = "rockchip,rk3288-i2c";
 415                 reg = <0xff160000 0x1000>;
 416                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clock-names = "i2c";
 420                 clocks = <&cru PCLK_I2C4>;
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&i2c4_xfer>;
 423                 status = "disabled";
 424         };
 425
 426         i2c5: i2c@ff170000 {
 427                 compatible = "rockchip,rk3288-i2c";
 428                 reg = <0xff170000 0x1000>;
 429                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clock-names = "i2c";
 433                 clocks = <&cru PCLK_I2C5>;
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&i2c5_xfer>;
 436                 status = "disabled";
 437         };
 438
 439         uart0: serial@ff180000 {
 440                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 441                 reg = <0xff180000 0x100>;
 442                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 443                 reg-shift = <2>;
 444                 reg-io-width = <4>;
 445                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 446                 clock-names = "baudclk", "apb_pclk";
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&uart0_xfer>;
 449                 status = "disabled";
 450         };
 451
 452         uart1: serial@ff190000 {
 453                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 454                 reg = <0xff190000 0x100>;
 455                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 456                 reg-shift = <2>;
 457                 reg-io-width = <4>;
 458                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 459                 clock-names = "baudclk", "apb_pclk";
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&uart1_xfer>;
 462                 status = "disabled";
 463         };
 464
 465         uart2: serial@ff690000 {
 466                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 467                 reg = <0xff690000 0x100>;
 468                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 469                 reg-shift = <2>;
 470                 reg-io-width = <4>;
 471                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 472                 clock-names = "baudclk", "apb_pclk";
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart2_xfer>;
 475                 status = "disabled";
 476         };
 477
 478         uart3: serial@ff1b0000 {
 479                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 480                 reg = <0xff1b0000 0x100>;
 481                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 482                 reg-shift = <2>;
 483                 reg-io-width = <4>;
 484                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 485                 clock-names = "baudclk", "apb_pclk";
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&uart3_xfer>;
 488                 status = "disabled";
 489         };
 490
 491         uart4: serial@ff1c0000 {
 492                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 493                 reg = <0xff1c0000 0x100>;
 494                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 495                 reg-shift = <2>;
 496                 reg-io-width = <4>;
 497                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 498                 clock-names = "baudclk", "apb_pclk";
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&uart4_xfer>;
 501                 status = "disabled";
 502         };
 503
 504         thermal-zones {
 505                 reserve_thermal: reserve_thermal {
 506                         polling-delay-passive = <1000>; /* milliseconds */
 507                         polling-delay = <5000>; /* milliseconds */
 508
 509                         thermal-sensors = <&tsadc 0>;
 510                 };
 511
 512                 cpu_thermal: cpu_thermal {
 513                         polling-delay-passive = <100>; /* milliseconds */
 514                         polling-delay = <5000>; /* milliseconds */
 515
 516                         thermal-sensors = <&tsadc 1>;
 517
 518                         trips {
 519                                 cpu_alert0: cpu_alert0 {
 520                                         temperature = <70000>; /* millicelsius */
 521                                         hysteresis = <2000>; /* millicelsius */
 522                                         type = "passive";
 523                                 };
 524                                 cpu_alert1: cpu_alert1 {
 525                                         temperature = <75000>; /* millicelsius */
 526                                         hysteresis = <2000>; /* millicelsius */
 527                                         type = "passive";
 528                                 };
 529                                 cpu_crit: cpu_crit {
 530                                         temperature = <90000>; /* millicelsius */
 531                                         hysteresis = <2000>; /* millicelsius */
 532                                         type = "critical";
 533                                 };
 534                         };
 535
 536                         cooling-maps {
 537                                 map0 {
 538                                         trip = <&cpu_alert0>;
 539                                         cooling-device =
 540                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 541                                 };
 542                                 map1 {
 543                                         trip = <&cpu_alert1>;
 544                                         cooling-device =
 545                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 546                                 };
 547                         };
 548                 };
 549
 550                 gpu_thermal: gpu_thermal {
 551                         polling-delay-passive = <100>; /* milliseconds */
 552                         polling-delay = <5000>; /* milliseconds */
 553
 554                         thermal-sensors = <&tsadc 2>;
 555
 556                         trips {
 557                                 gpu_alert0: gpu_alert0 {
 558                                         temperature = <70000>; /* millicelsius */
 559                                         hysteresis = <2000>; /* millicelsius */
 560                                         type = "passive";
 561                                 };
 562                                 gpu_crit: gpu_crit {
 563                                         temperature = <90000>; /* millicelsius */
 564                                         hysteresis = <2000>; /* millicelsius */
 565                                         type = "critical";
 566                                 };
 567                         };
 568
 569                         cooling-maps {
 570                                 map0 {
 571                                         trip = <&gpu_alert0>;
 572                                         cooling-device =
 573                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 574                                 };
 575                         };
 576                 };
 577         };
 578
 579         tsadc: tsadc@ff280000 {
 580                 compatible = "rockchip,rk3288-tsadc";
 581                 reg = <0xff280000 0x100>;
 582                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 583                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 584                 clock-names = "tsadc", "apb_pclk";
 585                 resets = <&cru SRST_TSADC>;
 586                 reset-names = "tsadc-apb";
 587                 pinctrl-names = "init", "default", "sleep";
 588                 pinctrl-0 = <&otp_gpio>;
 589                 pinctrl-1 = <&otp_out>;
 590                 pinctrl-2 = <&otp_gpio>;
 591                 #thermal-sensor-cells = <1>;
 592                 rockchip,hw-tshut-temp = <95000>;
 593                 status = "disabled";
 594         };
 595
 596         gmac: ethernet@ff290000 {
 597                 compatible = "rockchip,rk3288-gmac";
 598                 reg = <0xff290000 0x10000>;
 599                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 600                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 601                 interrupt-names = "macirq", "eth_wake_irq";
 602                 rockchip,grf = <&grf>;
 603                 clocks = <&cru SCLK_MAC>,
 604                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 605                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 606                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 607                 clock-names = "stmmaceth",
 608                         "mac_clk_rx", "mac_clk_tx",
 609                         "clk_mac_ref", "clk_mac_refout",
 610                         "aclk_mac", "pclk_mac";
 611                 resets = <&cru SRST_MAC>;
 612                 reset-names = "stmmaceth";
 613                 max-speed = <100>;
 614                 status = "disabled";
 615         };
 616
 617         usb_host0_ehci: usb@ff500000 {
 618                 compatible = "generic-ehci";
 619                 reg = <0xff500000 0x100>;
 620                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 621                 clocks = <&cru HCLK_USBHOST0>;
 622                 clock-names = "usbhost";
 623                 phys = <&usbphy1>;
 624                 phy-names = "usb";
 625                 status = "disabled";
 626         };
 627
 628         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 629
 630         usb_host1: usb@ff540000 {
 631                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 632                                 "snps,dwc2";
 633                 reg = <0xff540000 0x40000>;
 634                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&cru HCLK_USBHOST1>;
 636                 clock-names = "otg";
 637                 dr_mode = "host";
 638                 phys = <&usbphy2>;
 639                 phy-names = "usb2-phy";
 640                 status = "disabled";
 641         };
 642
 643         usb_otg: usb@ff580000 {
 644                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 645                                 "snps,dwc2";
 646                 reg = <0xff580000 0x40000>;
 647                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&cru HCLK_OTG0>;
 649                 clock-names = "otg";
 650                 dr_mode = "otg";
 651                 g-np-tx-fifo-size = <16>;
 652                 g-rx-fifo-size = <275>;
 653                 g-tx-fifo-size = <256 128 128 64 64 32>;
 654                 g-use-dma;
 655                 phys = <&usbphy0>;
 656                 phy-names = "usb2-phy";
 657                 status = "disabled";
 658         };
 659
 660         usb_hsic: usb@ff5c0000 {
 661                 compatible = "generic-ehci";
 662                 reg = <0xff5c0000 0x100>;
 663                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 664                 clocks = <&cru HCLK_HSIC>;
 665                 clock-names = "usbhost";
 666                 status = "disabled";
 667         };
 668
 669         i2c0: i2c@ff650000 {
 670                 compatible = "rockchip,rk3288-i2c";
 671                 reg = <0xff650000 0x1000>;
 672                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 673                 #address-cells = <1>;
 674                 #size-cells = <0>;
 675                 clock-names = "i2c";
 676                 clocks = <&cru PCLK_I2C0>;
 677                 pinctrl-names = "default";
 678                 pinctrl-0 = <&i2c0_xfer>;
 679                 status = "disabled";
 680         };
 681
 682         i2c2: i2c@ff660000 {
 683                 compatible = "rockchip,rk3288-i2c";
 684                 reg = <0xff660000 0x1000>;
 685                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 clock-names = "i2c";
 689                 clocks = <&cru PCLK_I2C2>;
 690                 pinctrl-names = "default";
 691                 pinctrl-0 = <&i2c2_xfer>;
 692                 status = "disabled";
 693         };
 694
 695         pwm0: pwm@ff680000 {
 696                 compatible = "rockchip,rk3288-pwm";
 697                 reg = <0xff680000 0x10>;
 698                 #pwm-cells = <3>;
 699                 pinctrl-names = "default";
 700                 pinctrl-0 = <&pwm0_pin>;
 701                 clocks = <&cru PCLK_PWM>;
 702                 clock-names = "pwm";
 703                 status = "disabled";
 704         };
 705
 706         pwm1: pwm@ff680010 {
 707                 compatible = "rockchip,rk3288-pwm";
 708                 reg = <0xff680010 0x10>;
 709                 #pwm-cells = <3>;
 710                 pinctrl-names = "default";
 711                 pinctrl-0 = <&pwm1_pin>;
 712                 clocks = <&cru PCLK_PWM>;
 713                 clock-names = "pwm";
 714                 status = "disabled";
 715         };
 716
 717         pwm2: pwm@ff680020 {
 718                 compatible = "rockchip,rk3288-pwm";
 719                 reg = <0xff680020 0x10>;
 720                 #pwm-cells = <3>;
 721                 pinctrl-names = "default";
 722                 pinctrl-0 = <&pwm2_pin>;
 723                 clocks = <&cru PCLK_PWM>;
 724                 clock-names = "pwm";
 725                 status = "disabled";
 726         };
 727
 728         pwm3: pwm@ff680030 {
 729                 compatible = "rockchip,rk3288-pwm";
 730                 reg = <0xff680030 0x10>;
 731                 #pwm-cells = <2>;
 732                 pinctrl-names = "default";
 733                 pinctrl-0 = <&pwm3_pin>;
 734                 clocks = <&cru PCLK_PWM>;
 735                 clock-names = "pwm";
 736                 status = "disabled";
 737         };
 738
 739         bus_intmem@ff700000 {
 740                 compatible = "mmio-sram";
 741                 reg = <0xff700000 0x18000>;
 742                 #address-cells = <1>;
 743                 #size-cells = <1>;
 744                 ranges = <0 0xff700000 0x18000>;
 745                 smp-sram@0 {
 746                         compatible = "rockchip,rk3066-smp-sram";
 747                         reg = <0x00 0x10>;
 748                 };
 749         };
 750
 751         sram@ff720000 {
 752                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 753                 reg = <0xff720000 0x1000>;
 754         };
 755
 756         qos_gpu_r: qos@ffaa0000 {
 757                 compatible = "syscon";
 758                 reg = <0xffaa0000 0x20>;
 759         };
 760
 761         qos_gpu_w: qos@ffaa0080 {
 762                 compatible = "syscon";
 763                 reg = <0xffaa0080 0x20>;
 764         };
 765
 766         qos_vio1_vop: qos@ffad0000 {
 767                 compatible = "syscon";
 768                 reg = <0xffad0000 0x20>;
 769         };
 770
 771         qos_vio1_isp_w0: qos@ffad0100 {
 772                 compatible = "syscon";
 773                 reg = <0xffad0100 0x20>;
 774         };
 775
 776         qos_vio1_isp_w1: qos@ffad0180 {
 777                 compatible = "syscon";
 778                 reg = <0xffad0180 0x20>;
 779         };
 780
 781         qos_vio0_vop: qos@ffad0400 {
 782                 compatible = "syscon";
 783                 reg = <0xffad0400 0x20>;
 784         };
 785
 786         qos_vio0_vip: qos@ffad0480 {
 787                 compatible = "syscon";
 788                 reg = <0xffad0480 0x20>;
 789         };
 790
 791         qos_vio0_iep: qos@ffad0500 {
 792                 compatible = "syscon";
 793                 reg = <0xffad0500 0x20>;
 794         };
 795
 796         qos_vio2_rga_r: qos@ffad0800 {
 797                 compatible = "syscon";
 798                 reg = <0xffad0800 0x20>;
 799         };
 800
 801         qos_vio2_rga_w: qos@ffad0880 {
 802                 compatible = "syscon";
 803                 reg = <0xffad0880 0x20>;
 804         };
 805
 806         qos_vio1_isp_r: qos@ffad0900 {
 807                 compatible = "syscon";
 808                 reg = <0xffad0900 0x20>;
 809         };
 810
 811         qos_video: qos@ffae0000 {
 812                 compatible = "syscon";
 813                 reg = <0xffae0000 0x20>;
 814         };
 815
 816         qos_hevc_r: qos@ffaf0000 {
 817                 compatible = "syscon";
 818                 reg = <0xffaf0000 0x20>;
 819         };
 820
 821         qos_hevc_w: qos@ffaf0080 {
 822                 compatible = "syscon";
 823                 reg = <0xffaf0080 0x20>;
 824         };
 825
 826         pmu: power-management@ff730000 {
 827                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 828                 reg = <0xff730000 0x100>;
 829
 830                 power: power-controller {
 831                         compatible = "rockchip,rk3288-power-controller";
 832                         #power-domain-cells = <1>;
 833                         #address-cells = <1>;
 834                         #size-cells = <0>;
 835
 836                         /*
 837                          * Note: Although SCLK_* are the working clocks
 838                          * of device without including on the NOC, needed for
 839                          * synchronous reset.
 840                          *
 841                          * The clocks on the which NOC:
 842                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 843                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 844                          * ACLK_RGA is on ACLK_RGA_NIU.
 845                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 846                          *
 847                          * Which clock are device clocks:
 848                          *      clocks          devices
 849                          *      *_IEP           IEP:Image Enhancement Processor
 850                          *      *_ISP           ISP:Image Signal Processing
 851                          *      *_VIP           VIP:Video Input Processor
 852                          *      *_VOP*          VOP:Visual Output Processor
 853                          *      *_RGA           RGA
 854                          *      *_EDP*          EDP
 855                          *      *_LVDS_*        LVDS
 856                          *      *_HDMI          HDMI
 857                          *      *_MIPI_*        MIPI
 858                          */
 859                         pd_vio@RK3288_PD_VIO {
 860                                 reg = <RK3288_PD_VIO>;
 861                                 clocks = <&cru ACLK_IEP>,
 862                                          <&cru ACLK_ISP>,
 863                                          <&cru ACLK_RGA>,
 864                                          <&cru ACLK_VIP>,
 865                                          <&cru ACLK_VOP0>,
 866                                          <&cru ACLK_VOP1>,
 867                                          <&cru DCLK_VOP0>,
 868                                          <&cru DCLK_VOP1>,
 869                                          <&cru HCLK_IEP>,
 870                                          <&cru HCLK_ISP>,
 871                                          <&cru HCLK_RGA>,
 872                                          <&cru HCLK_VIP>,
 873                                          <&cru HCLK_VOP0>,
 874                                          <&cru HCLK_VOP1>,
 875                                          <&cru PCLK_EDP_CTRL>,
 876                                          <&cru PCLK_HDMI_CTRL>,
 877                                          <&cru PCLK_LVDS_PHY>,
 878                                          <&cru PCLK_MIPI_CSI>,
 879                                          <&cru PCLK_MIPI_DSI0>,
 880                                          <&cru PCLK_MIPI_DSI1>,
 881                                          <&cru SCLK_EDP_24M>,
 882                                          <&cru SCLK_EDP>,
 883                                          <&cru SCLK_ISP_JPE>,
 884                                          <&cru SCLK_ISP>,
 885                                          <&cru SCLK_RGA>;
 886                                 pm_qos = <&qos_vio0_iep>,
 887                                          <&qos_vio1_vop>,
 888                                          <&qos_vio1_isp_w0>,
 889                                          <&qos_vio1_isp_w1>,
 890                                          <&qos_vio0_vop>,
 891                                          <&qos_vio0_vip>,
 892                                          <&qos_vio2_rga_r>,
 893                                          <&qos_vio2_rga_w>,
 894                                          <&qos_vio1_isp_r>;
 895                         };
 896
 897                         /*
 898                          * Note: The following 3 are HEVC(H.265) clocks,
 899                          * and on the ACLK_HEVC_NIU (NOC).
 900                          */
 901                         pd_hevc@RK3288_PD_HEVC {
 902                                 reg = <RK3288_PD_HEVC>;
 903                                 clocks = <&cru ACLK_HEVC>,
 904                                          <&cru SCLK_HEVC_CABAC>,
 905                                          <&cru SCLK_HEVC_CORE>;
 906                                 pm_qos = <&qos_hevc_r>,
 907                                          <&qos_hevc_w>;
 908                         };
 909
 910                         /*
 911                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 912                          * (video endecoder & decoder) clocks that on the
 913                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 914                          */
 915                         pd_video@RK3288_PD_VIDEO {
 916                                 reg = <RK3288_PD_VIDEO>;
 917                                 clocks = <&cru ACLK_VCODEC>,
 918                                          <&cru HCLK_VCODEC>;
 919                                 pm_qos = <&qos_video>;
 920                         };
 921
 922                         /*
 923                          * Note: ACLK_GPU is the GPU clock,
 924                          * and on the ACLK_GPU_NIU (NOC).
 925                          */
 926                         pd_gpu@RK3288_PD_GPU {
 927                                 reg = <RK3288_PD_GPU>;
 928                                 clocks = <&cru ACLK_GPU>;
 929                                 pm_qos = <&qos_gpu_r>,
 930                                          <&qos_gpu_w>;
 931                         };
 932                 };
 933
 934                 reboot-mode {
 935                         compatible = "syscon-reboot-mode";
 936                         offset = <0x94>;
 937                         mode-normal = <BOOT_NORMAL>;
 938                         mode-recovery = <BOOT_RECOVERY>;
 939                         mode-bootloader = <BOOT_FASTBOOT>;
 940                         mode-loader = <BOOT_BL_DOWNLOAD>;
 941                         mode-ums = <BOOT_UMS>;
 942                 };
 943         };
 944
 945         sgrf: syscon@ff740000 {
 946                 compatible = "rockchip,rk3288-sgrf", "syscon";
 947                 reg = <0xff740000 0x1000>;
 948         };
 949
 950         cru: clock-controller@ff760000 {
 951                 compatible = "rockchip,rk3288-cru";
 952                 reg = <0xff760000 0x1000>;
 953                 rockchip,grf = <&grf>;
 954                 #clock-cells = <1>;
 955                 #reset-cells = <1>;
 956                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 957                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 958                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 959                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 960                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 961                                   <&cru PCLK_PERI>;
 962                 assigned-clock-rates = <0>, <0>,
 963                                        <594000000>, <400000000>,
 964                                        <500000000>, <300000000>,
 965                                        <150000000>, <75000000>,
 966                                        <300000000>, <150000000>,
 967                                        <75000000>;
 968                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 969         };
 970
 971         grf: syscon@ff770000 {
 972                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 973                 reg = <0xff770000 0x1000>;
 974
 975                 edp_phy: edp-phy {
 976                         compatible = "rockchip,rk3288-dp-phy";
 977                         clocks = <&cru SCLK_EDP_24M>;
 978                         clock-names = "24m";
 979                         #phy-cells = <0>;
 980                         status = "disabled";
 981                 };
 982
 983                 io_domains: io-domains {
 984                         compatible = "rockchip,rk3288-io-voltage-domain";
 985                         status = "disabled";
 986                 };
 987
 988                 usbphy: usbphy {
 989                         compatible = "rockchip,rk3288-usb-phy";
 990                         #address-cells = <1>;
 991                         #size-cells = <0>;
 992                         status = "disabled";
 993
 994                         usbphy0: usb-phy@320 {
 995                                 #phy-cells = <0>;
 996                                 reg = <0x320>;
 997                                 clocks = <&cru SCLK_OTGPHY0>;
 998                                 clock-names = "phyclk";
 999                                 #clock-cells = <0>;
1000                                 resets = <&cru SRST_USBOTG_PHY>;
1001                                 reset-names = "phy-reset";
1002                         };
1003
1004                         usbphy1: usb-phy@334 {
1005                                 #phy-cells = <0>;
1006                                 reg = <0x334>;
1007                                 clocks = <&cru SCLK_OTGPHY1>;
1008                                 clock-names = "phyclk";
1009                                 #clock-cells = <0>;
1010                         };
1011
1012                         usbphy2: usb-phy@348 {
1013                                 #phy-cells = <0>;
1014                                 reg = <0x348>;
1015                                 clocks = <&cru SCLK_OTGPHY2>;
1016                                 clock-names = "phyclk";
1017                                 #clock-cells = <0>;
1018                                 resets = <&cru SRST_USBHOST1_PHY>;
1019                                 reset-names = "phy-reset";
1020                         };
1021                 };
1022         };
1023
1024         wdt: watchdog@ff800000 {
1025                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1026                 reg = <0xff800000 0x100>;
1027                 clocks = <&cru PCLK_WDT>;
1028                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1029                 status = "disabled";
1030         };
1031
1032         spdif: sound@ff88b0000 {
1033                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1034                 reg = <0xff8b0000 0x10000>;
1035                 #sound-dai-cells = <0>;
1036                 clock-names = "hclk", "mclk";
1037                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1038                 dmas = <&dmac_bus_s 3>;
1039                 dma-names = "tx";
1040                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1041                 pinctrl-names = "default";
1042                 pinctrl-0 = <&spdif_tx>;
1043                 rockchip,grf = <&grf>;
1044                 status = "disabled";
1045         };
1046
1047         i2s: i2s@ff890000 {
1048                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1049                 reg = <0xff890000 0x10000>;
1050                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1051                 #address-cells = <1>;
1052                 #size-cells = <0>;
1053                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1054                 dma-names = "tx", "rx";
1055                 clock-names = "i2s_hclk", "i2s_clk";
1056                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1057                 pinctrl-names = "default";
1058                 pinctrl-0 = <&i2s0_bus>;
1059                 rockchip,playback-channels = <8>;
1060                 rockchip,capture-channels = <2>;
1061                 status = "disabled";
1062         };
1063
1064         rga: rga@ff920000 {
1065                 compatible = "rockchip,rk3288-rga";
1066                 reg = <0xff920000 0x180>;
1067                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1068                 interrupt-names = "rga";
1069                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1070                 clock-names = "aclk", "hclk", "sclk";
1071
1072                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1073
1074                 reset-names = "core", "axi", "ahb";
1075                 status = "disabled";
1076         };
1077
1078         vopb: vop@ff930000 {
1079                 compatible = "rockchip,rk3288-vop";
1080                 reg = <0xff930000 0x19c>;
1081                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1082                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1083                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1084                 power-domains = <&power RK3288_PD_VIO>;
1085                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1086                 reset-names = "axi", "ahb", "dclk";
1087                 iommus = <&vopb_mmu>;
1088                 status = "disabled";
1089
1090                 vopb_out: port {
1091                         #address-cells = <1>;
1092                         #size-cells = <0>;
1093
1094                         vopb_out_hdmi: endpoint@0 {
1095                                 reg = <0>;
1096                                 remote-endpoint = <&hdmi_in_vopb>;
1097                         };
1098
1099                         vopb_out_edp: endpoint@1 {
1100                                 reg = <1>;
1101                                 remote-endpoint = <&edp_in_vopb>;
1102                         };
1103
1104                         vopb_out_mipi: endpoint@2 {
1105                                 reg = <2>;
1106                                 remote-endpoint = <&mipi_in_vopb>;
1107                         };
1108
1109                         vopb_out_lvds: endpoint@3 {
1110                                 reg = <3>;
1111                                 remote-endpoint = <&lvds_in_vopb>;
1112                         };
1113                 };
1114         };
1115
1116         vopb_mmu: iommu@ff930300 {
1117                 compatible = "rockchip,iommu";
1118                 reg = <0xff930300 0x100>;
1119                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1120                 interrupt-names = "vopb_mmu";
1121                 power-domains = <&power RK3288_PD_VIO>;
1122                 #iommu-cells = <0>;
1123                 status = "disabled";
1124         };
1125
1126         vopl: vop@ff940000 {
1127                 compatible = "rockchip,rk3288-vop";
1128                 reg = <0xff940000 0x19c>;
1129                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1130                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1131                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1132                 power-domains = <&power RK3288_PD_VIO>;
1133                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1134                 reset-names = "axi", "ahb", "dclk";
1135                 iommus = <&vopl_mmu>;
1136                 status = "disabled";
1137
1138                 vopl_out: port {
1139                         #address-cells = <1>;
1140                         #size-cells = <0>;
1141
1142                         vopl_out_hdmi: endpoint@0 {
1143                                 reg = <0>;
1144                                 remote-endpoint = <&hdmi_in_vopl>;
1145                         };
1146
1147                         vopl_out_edp: endpoint@1 {
1148                                 reg = <1>;
1149                                 remote-endpoint = <&edp_in_vopl>;
1150                         };
1151
1152                         vopl_out_mipi: endpoint@2 {
1153                                 reg = <2>;
1154                                 remote-endpoint = <&mipi_in_vopl>;
1155                         };
1156
1157                         vopl_out_lvds: endpoint@3 {
1158                                 reg = <3>;
1159                                 remote-endpoint = <&lvds_in_vopl>;
1160                         };
1161
1162                 };
1163         };
1164
1165         vopl_mmu: iommu@ff940300 {
1166                 compatible = "rockchip,iommu";
1167                 reg = <0xff940300 0x100>;
1168                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1169                 interrupt-names = "vopl_mmu";
1170                 power-domains = <&power RK3288_PD_VIO>;
1171                 #iommu-cells = <0>;
1172                 status = "disabled";
1173         };
1174
1175         mipi_dsi: mipi@ff960000 {
1176                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1177                 reg = <0xff960000 0x4000>;
1178                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1179                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1180                 clock-names = "ref", "pclk";
1181                 power-domains = <&power RK3288_PD_VIO>;
1182                 rockchip,grf = <&grf>;
1183                 #address-cells = <1>;
1184                 #size-cells = <0>;
1185                 status = "disabled";
1186
1187                 ports {
1188                         mipi_in: port {
1189                                 #address-cells = <1>;
1190                                 #size-cells = <0>;
1191                                 mipi_in_vopb: endpoint@0 {
1192                                         reg = <0>;
1193                                         remote-endpoint = <&vopb_out_mipi>;
1194                                 };
1195                                 mipi_in_vopl: endpoint@1 {
1196                                         reg = <1>;
1197                                         remote-endpoint = <&vopl_out_mipi>;
1198                                 };
1199                         };
1200                 };
1201         };
1202
1203         edp: dp@ff970000 {
1204                 compatible = "rockchip,rk3288-dp";
1205                 reg = <0xff970000 0x4000>;
1206                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1207                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1208                 clock-names = "dp", "pclk";
1209                 phys = <&edp_phy>;
1210                 phy-names = "dp";
1211                 resets = <&cru SRST_EDP>;
1212                 reset-names = "dp";
1213                 rockchip,grf = <&grf>;
1214                 status = "disabled";
1215
1216                 ports {
1217                         #address-cells = <1>;
1218                         #size-cells = <0>;
1219                         edp_in: port@0 {
1220                                 reg = <0>;
1221                                 #address-cells = <1>;
1222                                 #size-cells = <0>;
1223                                 edp_in_vopb: endpoint@0 {
1224                                         reg = <0>;
1225                                         remote-endpoint = <&vopb_out_edp>;
1226                                 };
1227                                 edp_in_vopl: endpoint@1 {
1228                                         reg = <1>;
1229                                         remote-endpoint = <&vopl_out_edp>;
1230                                 };
1231                         };
1232                 };
1233         };
1234
1235         lvds: lvds@ff96c000 {
1236                 compatible = "rockchip,rk3288-lvds";
1237                 reg = <0xff96c000 0x4000>;
1238                 clocks = <&cru PCLK_LVDS_PHY>;
1239                 clock-names = "pclk_lvds";
1240                 pinctrl-names = "default";
1241                 pinctrl-0 = <&lcdc0_ctl>;
1242                 power-domains = <&power RK3288_PD_VIO>;
1243                 rockchip,grf = <&grf>;
1244                 status = "disabled";
1245
1246                 ports {
1247                         #address-cells = <1>;
1248                         #size-cells = <0>;
1249
1250                         lvds_in: port@0 {
1251                                 reg = <0>;
1252
1253                                 #address-cells = <1>;
1254                                 #size-cells = <0>;
1255
1256                                 lvds_in_vopb: endpoint@0 {
1257                                         reg = <0>;
1258                                         remote-endpoint = <&vopb_out_lvds>;
1259                                 };
1260                                 lvds_in_vopl: endpoint@1 {
1261                                         reg = <1>;
1262                                         remote-endpoint = <&vopl_out_lvds>;
1263                                 };
1264                         };
1265                 };
1266         };
1267
1268         hdmi: hdmi@ff980000 {
1269                 compatible = "rockchip,rk3288-dw-hdmi";
1270                 reg = <0xff980000 0x20000>;
1271                 reg-io-width = <4>;
1272                 rockchip,grf = <&grf>;
1273                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1274                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1275                 clock-names = "iahb", "isfr";
1276                 power-domains = <&power RK3288_PD_VIO>;
1277                 status = "disabled";
1278
1279                 ports {
1280                         hdmi_in: port {
1281                                 #address-cells = <1>;
1282                                 #size-cells = <0>;
1283                                 hdmi_in_vopb: endpoint@0 {
1284                                         reg = <0>;
1285                                         remote-endpoint = <&vopb_out_hdmi>;
1286                                 };
1287                                 hdmi_in_vopl: endpoint@1 {
1288                                         reg = <1>;
1289                                         remote-endpoint = <&vopl_out_hdmi>;
1290                                 };
1291                         };
1292                 };
1293         };
1294
1295         gpu: gpu@ffa30000 {
1296                 compatible = "arm,malit764",
1297                              "arm,malit76x",
1298                              "arm,malit7xx",
1299                              "arm,mali-midgard";
1300                 reg = <0xffa30000 0x10000>;
1301                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1302                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1303                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1304                 interrupt-names = "JOB", "MMU", "GPU";
1305                 clocks = <&cru ACLK_GPU>;
1306                 clock-names = "clk_mali";
1307                 operating-points = <
1308                         /* KHz uV */
1309                         600000 1250000
1310                         /* 500000 1200000 - See crosbug.com/p/33857 */
1311                         400000 1100000
1312                         300000 1000000
1313                         200000 950000
1314                         100000 950000
1315                 >;
1316                 #cooling-cells = <2>; /* min followed by max */
1317                 power-domains = <&power RK3288_PD_GPU>;
1318                 status = "disabled";
1319         };
1320
1321         vpu: video-codec@ff9a0000 {
1322                 compatible = "rockchip,rk3288-vpu";
1323                 reg = <0xff9a0000 0x800>;
1324                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1325                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1326                 interrupt-names = "vepu", "vdpu";
1327                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1328                 clock-names = "aclk", "hclk";
1329                 power-domains = <&power RK3288_PD_VIDEO>;
1330                 iommus = <&vpu_mmu>;
1331                 assigned-clocks = <&cru ACLK_VCODEC>;
1332                 assigned-clock-rates = <400000000>;
1333                 status = "disabled";
1334         };
1335
1336         vpu_service: vpu-service@ff9a0000 {
1337                 compatible = "rockchip,vpu_service";
1338                 reg = <0xff9a0000 0x800>;
1339                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1340                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1341                 interrupt-names = "irq_enc", "irq_dec";
1342                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1343                 clock-names = "aclk_vcodec", "hclk_vcodec";
1344                 power-domains = <&power RK3288_PD_VIDEO>;
1345                 rockchip,grf = <&grf>;
1346                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1347                 reset-names = "video_a", "video_h";
1348                 iommus = <&vpu_mmu>;
1349                 iommu_enabled = <1>;
1350                 dev_mode = <0>;
1351                 status = "disabled";
1352                 /* 0 means ion, 1 means drm */
1353                 allocator = <1>;
1354         };
1355
1356         vpu_mmu: iommu@ff9a0800 {
1357                 compatible = "rockchip,iommu";
1358                 reg = <0xff9a0800 0x100>;
1359                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1360                 interrupt-names = "vpu_mmu";
1361                 power-domains = <&power RK3288_PD_VIDEO>;
1362                 #iommu-cells = <0>;
1363         };
1364
1365         hevc_service: hevc-service@ff9c0000 {
1366                 compatible = "rockchip,hevc_service";
1367                 reg = <0xff9c0000 0x400>;
1368                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1369                 interrupt-names = "irq_dec";
1370                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1371                         <&cru SCLK_HEVC_CORE>,
1372                         <&cru SCLK_HEVC_CABAC>;
1373                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1374                         "clk_cabac";
1375                 /*
1376                  * The 4K hevc would also work well with 500/125/300/300,
1377                  * no more err irq and reset request.
1378                  */
1379                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1380                                   <&cru SCLK_HEVC_CORE>,
1381                                   <&cru SCLK_HEVC_CABAC>;
1382                 assigned-clock-rates = <400000000>, <100000000>,
1383                                        <300000000>, <300000000>;
1384
1385                 resets = <&cru SRST_HEVC>;
1386                 reset-names = "video";
1387                 power-domains = <&power RK3288_PD_HEVC>;
1388                 rockchip,grf = <&grf>;
1389                 dev_mode = <1>;
1390                 iommus = <&hevc_mmu>;
1391                 iommu_enabled = <1>;
1392                 status = "disabled";
1393                 /* 0 means ion, 1 means drm */
1394                 allocator = <1>;
1395         };
1396
1397         hevc_mmu: iommu@ff9c0440 {
1398                 compatible = "rockchip,iommu";
1399                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1400                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1401                 interrupt-names = "hevc_mmu";
1402                 power-domains = <&power RK3288_PD_HEVC>;
1403                 #iommu-cells = <0>;
1404         };
1405
1406         gic: interrupt-controller@ffc01000 {
1407                 compatible = "arm,gic-400";
1408                 interrupt-controller;
1409                 #interrupt-cells = <3>;
1410                 #address-cells = <0>;
1411
1412                 reg = <0xffc01000 0x1000>,
1413                       <0xffc02000 0x1000>,
1414                       <0xffc04000 0x2000>,
1415                       <0xffc06000 0x2000>;
1416                 interrupts = <GIC_PPI 9 0xf04>;
1417         };
1418
1419         efuse: efuse@ffb40000 {
1420                 compatible = "rockchip,rockchip-efuse";
1421                 reg = <0xffb40000 0x20>;
1422                 #address-cells = <1>;
1423                 #size-cells = <1>;
1424                 clocks = <&cru PCLK_EFUSE256>;
1425                 clock-names = "pclk_efuse";
1426
1427                 cpu_leakage: cpu_leakage@17 {
1428                         reg = <0x17 0x1>;
1429                 };
1430         };
1431
1432         cif_isp0: cif_isp@ff910000 {
1433                 compatible = "rockchip,rk3288-cif-isp";
1434                 rockchip,grf = <&grf>;
1435                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1436                 reg-names = "register", "csihost-register";
1437                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1438                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1439                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1440                         <&cru SCLK_MIPIDSI_24M>;
1441                 clock-names = "aclk_isp", "hclk_isp",
1442                         "sclk_isp", "sclk_isp_jpe",
1443                         "pclk_mipi_csi", "pclk_isp_in",
1444                         "sclk_mipidsi_24m";
1445                 resets = <&cru SRST_ISP>;
1446                 reset-names = "rst_isp";
1447                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1448                 interrupt-names = "cif_isp10_irq";
1449                 status = "disabled";
1450         };
1451
1452         pinctrl: pinctrl {
1453                 compatible = "rockchip,rk3288-pinctrl";
1454                 rockchip,grf = <&grf>;
1455                 rockchip,pmu = <&pmu>;
1456                 #address-cells = <1>;
1457                 #size-cells = <1>;
1458                 ranges;
1459
1460                 gpio0: gpio0@ff750000 {
1461                         compatible = "rockchip,gpio-bank";
1462                         reg =   <0xff750000 0x100>;
1463                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1464                         clocks = <&cru PCLK_GPIO0>;
1465
1466                         gpio-controller;
1467                         #gpio-cells = <2>;
1468
1469                         interrupt-controller;
1470                         #interrupt-cells = <2>;
1471                 };
1472
1473                 gpio1: gpio1@ff780000 {
1474                         compatible = "rockchip,gpio-bank";
1475                         reg = <0xff780000 0x100>;
1476                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1477                         clocks = <&cru PCLK_GPIO1>;
1478
1479                         gpio-controller;
1480                         #gpio-cells = <2>;
1481
1482                         interrupt-controller;
1483                         #interrupt-cells = <2>;
1484                 };
1485
1486                 gpio2: gpio2@ff790000 {
1487                         compatible = "rockchip,gpio-bank";
1488                         reg = <0xff790000 0x100>;
1489                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1490                         clocks = <&cru PCLK_GPIO2>;
1491
1492                         gpio-controller;
1493                         #gpio-cells = <2>;
1494
1495                         interrupt-controller;
1496                         #interrupt-cells = <2>;
1497                 };
1498
1499                 gpio3: gpio3@ff7a0000 {
1500                         compatible = "rockchip,gpio-bank";
1501                         reg = <0xff7a0000 0x100>;
1502                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1503                         clocks = <&cru PCLK_GPIO3>;
1504
1505                         gpio-controller;
1506                         #gpio-cells = <2>;
1507
1508                         interrupt-controller;
1509                         #interrupt-cells = <2>;
1510                 };
1511
1512                 gpio4: gpio4@ff7b0000 {
1513                         compatible = "rockchip,gpio-bank";
1514                         reg = <0xff7b0000 0x100>;
1515                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1516                         clocks = <&cru PCLK_GPIO4>;
1517
1518                         gpio-controller;
1519                         #gpio-cells = <2>;
1520
1521                         interrupt-controller;
1522                         #interrupt-cells = <2>;
1523                 };
1524
1525                 gpio5: gpio5@ff7c0000 {
1526                         compatible = "rockchip,gpio-bank";
1527                         reg = <0xff7c0000 0x100>;
1528                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1529                         clocks = <&cru PCLK_GPIO5>;
1530
1531                         gpio-controller;
1532                         #gpio-cells = <2>;
1533
1534                         interrupt-controller;
1535                         #interrupt-cells = <2>;
1536                 };
1537
1538                 gpio6: gpio6@ff7d0000 {
1539                         compatible = "rockchip,gpio-bank";
1540                         reg = <0xff7d0000 0x100>;
1541                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1542                         clocks = <&cru PCLK_GPIO6>;
1543
1544                         gpio-controller;
1545                         #gpio-cells = <2>;
1546
1547                         interrupt-controller;
1548                         #interrupt-cells = <2>;
1549                 };
1550
1551                 gpio7: gpio7@ff7e0000 {
1552                         compatible = "rockchip,gpio-bank";
1553                         reg = <0xff7e0000 0x100>;
1554                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1555                         clocks = <&cru PCLK_GPIO7>;
1556
1557                         gpio-controller;
1558                         #gpio-cells = <2>;
1559
1560                         interrupt-controller;
1561                         #interrupt-cells = <2>;
1562                 };
1563
1564                 gpio8: gpio8@ff7f0000 {
1565                         compatible = "rockchip,gpio-bank";
1566                         reg = <0xff7f0000 0x100>;
1567                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1568                         clocks = <&cru PCLK_GPIO8>;
1569
1570                         gpio-controller;
1571                         #gpio-cells = <2>;
1572
1573                         interrupt-controller;
1574                         #interrupt-cells = <2>;
1575                 };
1576
1577                 hdmi {
1578                         hdmi_ddc: hdmi-ddc {
1579                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1580                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1581                         };
1582                 };
1583
1584                 pcfg_pull_up: pcfg-pull-up {
1585                         bias-pull-up;
1586                 };
1587
1588                 pcfg_pull_down: pcfg-pull-down {
1589                         bias-pull-down;
1590                 };
1591
1592                 pcfg_pull_none: pcfg-pull-none {
1593                         bias-disable;
1594                 };
1595
1596                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1597                         bias-disable;
1598                         drive-strength = <12>;
1599                 };
1600
1601                 sleep {
1602                         global_pwroff: global-pwroff {
1603                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605
1606                         ddrio_pwroff: ddrio-pwroff {
1607                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1608                         };
1609
1610                         ddr0_retention: ddr0-retention {
1611                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1612                         };
1613
1614                         ddr1_retention: ddr1-retention {
1615                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1616                         };
1617                 };
1618
1619                 edp {
1620                         edp_hpd: edp-hpd {
1621                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1622                         };
1623                 };
1624
1625                 i2c0 {
1626                         i2c0_xfer: i2c0-xfer {
1627                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1628                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1629                         };
1630                 };
1631
1632                 i2c1 {
1633                         i2c1_xfer: i2c1-xfer {
1634                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1635                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1636                         };
1637                 };
1638
1639                 i2c2 {
1640                         i2c2_xfer: i2c2-xfer {
1641                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1642                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1643                         };
1644                 };
1645
1646                 i2c3 {
1647                         i2c3_xfer: i2c3-xfer {
1648                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1649                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1650                         };
1651                 };
1652
1653                 i2c4 {
1654                         i2c4_xfer: i2c4-xfer {
1655                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1656                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1657                         };
1658                 };
1659
1660                 i2c5 {
1661                         i2c5_xfer: i2c5-xfer {
1662                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1663                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1664                         };
1665                 };
1666
1667                 i2s0 {
1668                         i2s0_bus: i2s0-bus {
1669                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1670                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1671                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1672                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1673                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1674                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1675                         };
1676                 };
1677
1678                 lcdc0 {
1679                         lcdc0_ctl: lcdc0-ctl {
1680                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1681                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1682                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1683                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1684                         };
1685                 };
1686
1687                 sdmmc {
1688                         sdmmc_clk: sdmmc-clk {
1689                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1690                         };
1691
1692                         sdmmc_cmd: sdmmc-cmd {
1693                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1694                         };
1695
1696                         sdmmc_cd: sdmcc-cd {
1697                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1698                         };
1699
1700                         sdmmc_bus1: sdmmc-bus1 {
1701                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1702                         };
1703
1704                         sdmmc_bus4: sdmmc-bus4 {
1705                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1706                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1707                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1708                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1709                         };
1710                 };
1711
1712                 sdio0 {
1713                         sdio0_bus1: sdio0-bus1 {
1714                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1715                         };
1716
1717                         sdio0_bus4: sdio0-bus4 {
1718                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1719                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1720                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1721                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1722                         };
1723
1724                         sdio0_cmd: sdio0-cmd {
1725                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1726                         };
1727
1728                         sdio0_clk: sdio0-clk {
1729                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1730                         };
1731
1732                         sdio0_cd: sdio0-cd {
1733                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1734                         };
1735
1736                         sdio0_wp: sdio0-wp {
1737                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1738                         };
1739
1740                         sdio0_pwr: sdio0-pwr {
1741                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1742                         };
1743
1744                         sdio0_bkpwr: sdio0-bkpwr {
1745                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1746                         };
1747
1748                         sdio0_int: sdio0-int {
1749                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1750                         };
1751                 };
1752
1753                 sdio1 {
1754                         sdio1_bus1: sdio1-bus1 {
1755                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1756                         };
1757
1758                         sdio1_bus4: sdio1-bus4 {
1759                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1760                                                 <3 25 4 &pcfg_pull_up>,
1761                                                 <3 26 4 &pcfg_pull_up>,
1762                                                 <3 27 4 &pcfg_pull_up>;
1763                         };
1764
1765                         sdio1_cd: sdio1-cd {
1766                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1767                         };
1768
1769                         sdio1_wp: sdio1-wp {
1770                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1771                         };
1772
1773                         sdio1_bkpwr: sdio1-bkpwr {
1774                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1775                         };
1776
1777                         sdio1_int: sdio1-int {
1778                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1779                         };
1780
1781                         sdio1_cmd: sdio1-cmd {
1782                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1783                         };
1784
1785                         sdio1_clk: sdio1-clk {
1786                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1787                         };
1788
1789                         sdio1_pwr: sdio1-pwr {
1790                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1791                         };
1792                 };
1793
1794                 emmc {
1795                         emmc_clk: emmc-clk {
1796                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1797                         };
1798
1799                         emmc_cmd: emmc-cmd {
1800                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1801                         };
1802
1803                         emmc_pwr: emmc-pwr {
1804                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1805                         };
1806
1807                         emmc_bus1: emmc-bus1 {
1808                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1809                         };
1810
1811                         emmc_bus4: emmc-bus4 {
1812                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1813                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1814                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1815                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1816                         };
1817
1818                         emmc_bus8: emmc-bus8 {
1819                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1820                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1821                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1822                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1823                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1824                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1825                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1826                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1827                         };
1828                 };
1829
1830                 spi0 {
1831                         spi0_clk: spi0-clk {
1832                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1833                         };
1834                         spi0_cs0: spi0-cs0 {
1835                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1836                         };
1837                         spi0_tx: spi0-tx {
1838                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1839                         };
1840                         spi0_rx: spi0-rx {
1841                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1842                         };
1843                         spi0_cs1: spi0-cs1 {
1844                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1845                         };
1846                 };
1847                 spi1 {
1848                         spi1_clk: spi1-clk {
1849                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1850                         };
1851                         spi1_cs0: spi1-cs0 {
1852                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1853                         };
1854                         spi1_rx: spi1-rx {
1855                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1856                         };
1857                         spi1_tx: spi1-tx {
1858                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1859                         };
1860                 };
1861
1862                 spi2 {
1863                         spi2_cs1: spi2-cs1 {
1864                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1865                         };
1866                         spi2_clk: spi2-clk {
1867                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1868                         };
1869                         spi2_cs0: spi2-cs0 {
1870                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1871                         };
1872                         spi2_rx: spi2-rx {
1873                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1874                         };
1875                         spi2_tx: spi2-tx {
1876                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1877                         };
1878                 };
1879
1880                 uart0 {
1881                         uart0_xfer: uart0-xfer {
1882                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1883                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1884                         };
1885
1886                         uart0_cts: uart0-cts {
1887                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1888                         };
1889
1890                         uart0_rts: uart0-rts {
1891                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1892                         };
1893                 };
1894
1895                 uart1 {
1896                         uart1_xfer: uart1-xfer {
1897                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1898                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1899                         };
1900
1901                         uart1_cts: uart1-cts {
1902                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1903                         };
1904
1905                         uart1_rts: uart1-rts {
1906                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1907                         };
1908                 };
1909
1910                 uart2 {
1911                         uart2_xfer: uart2-xfer {
1912                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1913                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1914                         };
1915                         /* no rts / cts for uart2 */
1916                 };
1917
1918                 uart3 {
1919                         uart3_xfer: uart3-xfer {
1920                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1921                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1922                         };
1923
1924                         uart3_cts: uart3-cts {
1925                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1926                         };
1927
1928                         uart3_rts: uart3-rts {
1929                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1930                         };
1931                 };
1932
1933                 uart4 {
1934                         uart4_xfer: uart4-xfer {
1935                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1936                                                 <5 13 3 &pcfg_pull_none>;
1937                         };
1938
1939                         uart4_cts: uart4-cts {
1940                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1941                         };
1942
1943                         uart4_rts: uart4-rts {
1944                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1945                         };
1946                 };
1947
1948                 tsadc {
1949                         otp_gpio: otp-gpio {
1950                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1951                         };
1952
1953                         otp_out: otp-out {
1954                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1955                         };
1956                 };
1957
1958                 pwm0 {
1959                         pwm0_pin: pwm0-pin {
1960                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1961                         };
1962                 };
1963
1964                 pwm1 {
1965                         pwm1_pin: pwm1-pin {
1966                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1967                         };
1968                 };
1969
1970                 pwm2 {
1971                         pwm2_pin: pwm2-pin {
1972                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1973                         };
1974                 };
1975
1976                 pwm3 {
1977                         pwm3_pin: pwm3-pin {
1978                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1979                         };
1980                 };
1981
1982                 gmac {
1983                         rgmii_pins: rgmii-pins {
1984                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1985                                                 <3 31 3 &pcfg_pull_none>,
1986                                                 <3 26 3 &pcfg_pull_none>,
1987                                                 <3 27 3 &pcfg_pull_none>,
1988                                                 <3 28 3 &pcfg_pull_none_12ma>,
1989                                                 <3 29 3 &pcfg_pull_none_12ma>,
1990                                                 <3 24 3 &pcfg_pull_none_12ma>,
1991                                                 <3 25 3 &pcfg_pull_none_12ma>,
1992                                                 <4 0 3 &pcfg_pull_none>,
1993                                                 <4 5 3 &pcfg_pull_none>,
1994                                                 <4 6 3 &pcfg_pull_none>,
1995                                                 <4 9 3 &pcfg_pull_none_12ma>,
1996                                                 <4 4 3 &pcfg_pull_none_12ma>,
1997                                                 <4 1 3 &pcfg_pull_none>,
1998                                                 <4 3 3 &pcfg_pull_none>;
1999                         };
2000
2001                         rmii_pins: rmii-pins {
2002                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2003                                                 <3 31 3 &pcfg_pull_none>,
2004                                                 <3 28 3 &pcfg_pull_none>,
2005                                                 <3 29 3 &pcfg_pull_none>,
2006                                                 <4 0 3 &pcfg_pull_none>,
2007                                                 <4 5 3 &pcfg_pull_none>,
2008                                                 <4 4 3 &pcfg_pull_none>,
2009                                                 <4 1 3 &pcfg_pull_none>,
2010                                                 <4 2 3 &pcfg_pull_none>,
2011                                                 <4 3 3 &pcfg_pull_none>;
2012                         };
2013                 };
2014
2015                 spdif {
2016                         spdif_tx: spdif-tx {
2017                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2018                         };
2019                 };
2020
2021                 cif {
2022                         cif_dvp_d2d9: cif-dvp-d2d9 {
2023                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2024                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2025                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2026                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2027                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2028                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2029                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2030                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2031                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2032                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2033                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2034                         };
2035                 };
2036         };
2037 };