2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include "skeleton.dtsi"
52 compatible = "rockchip,rk3288";
54 interrupt-parent = <&gic>;
79 compatible = "arm,cortex-a12-pmu";
80 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
90 enable-method = "rockchip,rk3066-smp";
91 rockchip,pmu = <&pmu>;
95 compatible = "arm,cortex-a12";
97 resets = <&cru SRST_CORE0>;
98 operating-points-v2 = <&cpu0_opp_table>;
99 #cooling-cells = <2>; /* min followed by max */
100 clocks = <&cru ARMCLK>;
104 compatible = "arm,cortex-a12";
106 resets = <&cru SRST_CORE1>;
107 operating-points-v2 = <&cpu0_opp_table>;
111 compatible = "arm,cortex-a12";
113 resets = <&cru SRST_CORE2>;
114 operating-points-v2 = <&cpu0_opp_table>;
118 compatible = "arm,cortex-a12";
120 resets = <&cru SRST_CORE3>;
121 operating-points-v2 = <&cpu0_opp_table>;
125 cpu0_opp_table: opp_table0 {
126 compatible = "operating-points-v2";
130 opp-hz = /bits/ 64 <126000000>;
131 opp-microvolt = <900000>;
132 clock-latency-ns = <40000>;
135 opp-hz = /bits/ 64 <216000000>;
136 opp-microvolt = <900000>;
137 clock-latency-ns = <40000>;
140 opp-hz = /bits/ 64 <408000000>;
141 opp-microvolt = <900000>;
142 clock-latency-ns = <40000>;
145 opp-hz = /bits/ 64 <600000000>;
146 opp-microvolt = <900000>;
147 clock-latency-ns = <40000>;
150 opp-hz = /bits/ 64 <696000000>;
151 opp-microvolt = <950000>;
152 clock-latency-ns = <40000>;
155 opp-hz = /bits/ 64 <816000000>;
156 opp-microvolt = <1000000>;
157 clock-latency-ns = <40000>;
161 opp-hz = /bits/ 64 <1008000000>;
162 opp-microvolt = <1050000>;
163 clock-latency-ns = <40000>;
166 opp-hz = /bits/ 64 <1200000000>;
167 opp-microvolt = <1100000>;
168 clock-latency-ns = <40000>;
171 opp-hz = /bits/ 64 <1416000000>;
172 opp-microvolt = <1200000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <1512000000>;
177 opp-microvolt = <1300000>;
178 clock-latency-ns = <40000>;
181 opp-hz = /bits/ 64 <1608000000>;
182 opp-microvolt = <1350000>;
183 clock-latency-ns = <40000>;
188 compatible = "arm,amba-bus";
189 #address-cells = <1>;
193 dmac_peri: dma-controller@ff250000 {
194 compatible = "arm,pl330", "arm,primecell";
195 reg = <0xff250000 0x4000>;
196 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
199 arm,pl330-broken-no-flushp;
200 peripherals-req-type-burst;
201 clocks = <&cru ACLK_DMAC2>;
202 clock-names = "apb_pclk";
205 dmac_bus_ns: dma-controller@ff600000 {
206 compatible = "arm,pl330", "arm,primecell";
207 reg = <0xff600000 0x4000>;
208 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
211 arm,pl330-broken-no-flushp;
212 peripherals-req-type-burst;
213 clocks = <&cru ACLK_DMAC1>;
214 clock-names = "apb_pclk";
218 dmac_bus_s: dma-controller@ffb20000 {
219 compatible = "arm,pl330", "arm,primecell";
220 reg = <0xffb20000 0x4000>;
221 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
224 arm,pl330-broken-no-flushp;
225 peripherals-req-type-burst;
226 clocks = <&cru ACLK_DMAC1>;
227 clock-names = "apb_pclk";
232 #address-cells = <1>;
237 * The rk3288 cannot use the memory area above 0xfe000000
238 * for dma operations for some reason. While there is
239 * probably a better solution available somewhere, we
240 * haven't found it yet and while devices with 2GB of ram
241 * are not affected, this issue prevents 4GB from booting.
242 * So to make these devices at least bootable, block
243 * this area for the time being until the real solution
246 dma-unusable@fe000000 {
247 reg = <0xfe000000 0x1000000>;
252 compatible = "fixed-clock";
253 clock-frequency = <24000000>;
254 clock-output-names = "xin24m";
259 compatible = "arm,armv7-timer";
260 arm,cpu-registers-not-fw-configured;
261 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
262 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
263 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
264 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
265 clock-frequency = <24000000>;
268 timer: timer@ff810000 {
269 compatible = "rockchip,rk3288-timer";
270 reg = <0xff810000 0x20>;
271 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&xin24m>, <&cru PCLK_TIMER>;
273 clock-names = "timer", "pclk";
277 compatible = "rockchip,display-subsystem";
278 ports = <&vopl_out>, <&vopb_out>;
281 sdmmc: dwmmc@ff0c0000 {
282 compatible = "rockchip,rk3288-dw-mshc";
283 clock-freq-min-max = <400000 150000000>;
284 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
285 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
287 fifo-depth = <0x100>;
288 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
289 reg = <0xff0c0000 0x4000>;
293 sdio0: dwmmc@ff0d0000 {
294 compatible = "rockchip,rk3288-dw-mshc";
295 clock-freq-min-max = <400000 150000000>;
296 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
297 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
298 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
299 fifo-depth = <0x100>;
300 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
301 reg = <0xff0d0000 0x4000>;
305 sdio1: dwmmc@ff0e0000 {
306 compatible = "rockchip,rk3288-dw-mshc";
307 clock-freq-min-max = <400000 150000000>;
308 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
309 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
310 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
311 fifo-depth = <0x100>;
312 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
313 reg = <0xff0e0000 0x4000>;
317 emmc: dwmmc@ff0f0000 {
318 compatible = "rockchip,rk3288-dw-mshc";
319 clock-freq-min-max = <400000 150000000>;
320 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
321 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
322 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
323 fifo-depth = <0x100>;
324 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
325 reg = <0xff0f0000 0x4000>;
330 saradc: saradc@ff100000 {
331 compatible = "rockchip,saradc";
332 reg = <0xff100000 0x100>;
333 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
334 #io-channel-cells = <1>;
335 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
336 clock-names = "saradc", "apb_pclk";
337 resets = <&cru SRST_SARADC>;
338 reset-names = "saradc-apb";
343 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
344 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
345 clock-names = "spiclk", "apb_pclk";
346 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
347 dma-names = "tx", "rx";
348 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
351 reg = <0xff110000 0x1000>;
352 #address-cells = <1>;
358 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
359 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
360 clock-names = "spiclk", "apb_pclk";
361 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
362 dma-names = "tx", "rx";
363 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
366 reg = <0xff120000 0x1000>;
367 #address-cells = <1>;
373 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
374 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
375 clock-names = "spiclk", "apb_pclk";
376 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
377 dma-names = "tx", "rx";
378 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
381 reg = <0xff130000 0x1000>;
382 #address-cells = <1>;
388 compatible = "rockchip,rk3288-i2c";
389 reg = <0xff140000 0x1000>;
390 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
391 #address-cells = <1>;
394 clocks = <&cru PCLK_I2C1>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c1_xfer>;
401 compatible = "rockchip,rk3288-i2c";
402 reg = <0xff150000 0x1000>;
403 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
407 clocks = <&cru PCLK_I2C3>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c3_xfer>;
414 compatible = "rockchip,rk3288-i2c";
415 reg = <0xff160000 0x1000>;
416 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
420 clocks = <&cru PCLK_I2C4>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c4_xfer>;
427 compatible = "rockchip,rk3288-i2c";
428 reg = <0xff170000 0x1000>;
429 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
433 clocks = <&cru PCLK_I2C5>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c5_xfer>;
439 uart0: serial@ff180000 {
440 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
441 reg = <0xff180000 0x100>;
442 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
446 clock-names = "baudclk", "apb_pclk";
447 pinctrl-names = "default";
448 pinctrl-0 = <&uart0_xfer>;
452 uart1: serial@ff190000 {
453 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
454 reg = <0xff190000 0x100>;
455 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
459 clock-names = "baudclk", "apb_pclk";
460 pinctrl-names = "default";
461 pinctrl-0 = <&uart1_xfer>;
465 uart2: serial@ff690000 {
466 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
467 reg = <0xff690000 0x100>;
468 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
472 clock-names = "baudclk", "apb_pclk";
473 pinctrl-names = "default";
474 pinctrl-0 = <&uart2_xfer>;
478 uart3: serial@ff1b0000 {
479 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
480 reg = <0xff1b0000 0x100>;
481 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
485 clock-names = "baudclk", "apb_pclk";
486 pinctrl-names = "default";
487 pinctrl-0 = <&uart3_xfer>;
491 uart4: serial@ff1c0000 {
492 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
493 reg = <0xff1c0000 0x100>;
494 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
498 clock-names = "baudclk", "apb_pclk";
499 pinctrl-names = "default";
500 pinctrl-0 = <&uart4_xfer>;
505 reserve_thermal: reserve_thermal {
506 polling-delay-passive = <1000>; /* milliseconds */
507 polling-delay = <5000>; /* milliseconds */
509 thermal-sensors = <&tsadc 0>;
512 cpu_thermal: cpu_thermal {
513 polling-delay-passive = <250>; /* milliseconds */
514 polling-delay = <5000>; /* milliseconds */
516 thermal-sensors = <&tsadc 1>;
519 cpu_alert0: cpu_alert0 {
520 temperature = <70000>; /* millicelsius */
521 hysteresis = <2000>; /* millicelsius */
524 cpu_alert1: cpu_alert1 {
525 temperature = <80000>; /* millicelsius */
526 hysteresis = <2000>; /* millicelsius */
530 temperature = <90000>; /* millicelsius */
531 hysteresis = <2000>; /* millicelsius */
538 trip = <&cpu_alert0>;
540 <&cpu0 THERMAL_NO_LIMIT 6>;
543 trip = <&cpu_alert1>;
545 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
550 gpu_thermal: gpu_thermal {
551 polling-delay-passive = <250>; /* milliseconds */
552 polling-delay = <5000>; /* milliseconds */
554 thermal-sensors = <&tsadc 2>;
557 gpu_alert0: gpu_alert0 {
558 temperature = <80000>; /* millicelsius */
559 hysteresis = <2000>; /* millicelsius */
563 temperature = <90000>; /* millicelsius */
564 hysteresis = <2000>; /* millicelsius */
571 trip = <&gpu_alert0>;
573 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
579 tsadc: tsadc@ff280000 {
580 compatible = "rockchip,rk3288-tsadc";
581 reg = <0xff280000 0x100>;
582 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
584 clock-names = "tsadc", "apb_pclk";
585 resets = <&cru SRST_TSADC>;
586 reset-names = "tsadc-apb";
587 pinctrl-names = "init", "default", "sleep";
588 pinctrl-0 = <&otp_gpio>;
589 pinctrl-1 = <&otp_out>;
590 pinctrl-2 = <&otp_gpio>;
591 #thermal-sensor-cells = <1>;
592 rockchip,hw-tshut-temp = <95000>;
596 gmac: ethernet@ff290000 {
597 compatible = "rockchip,rk3288-gmac";
598 reg = <0xff290000 0x10000>;
599 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
601 interrupt-names = "macirq", "eth_wake_irq";
602 rockchip,grf = <&grf>;
603 clocks = <&cru SCLK_MAC>,
604 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
605 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
606 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
607 clock-names = "stmmaceth",
608 "mac_clk_rx", "mac_clk_tx",
609 "clk_mac_ref", "clk_mac_refout",
610 "aclk_mac", "pclk_mac";
611 resets = <&cru SRST_MAC>;
612 reset-names = "stmmaceth";
617 usb_host0_ehci: usb@ff500000 {
618 compatible = "generic-ehci";
619 reg = <0xff500000 0x100>;
620 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cru HCLK_USBHOST0>;
622 clock-names = "usbhost";
628 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
630 usb_host1: usb@ff540000 {
631 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
633 reg = <0xff540000 0x40000>;
634 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cru HCLK_USBHOST1>;
639 phy-names = "usb2-phy";
643 usb_otg: usb@ff580000 {
644 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
646 reg = <0xff580000 0x40000>;
647 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&cru HCLK_OTG0>;
651 g-np-tx-fifo-size = <16>;
652 g-rx-fifo-size = <275>;
653 g-tx-fifo-size = <256 128 128 64 64 32>;
656 phy-names = "usb2-phy";
660 usb_hsic: usb@ff5c0000 {
661 compatible = "generic-ehci";
662 reg = <0xff5c0000 0x100>;
663 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cru HCLK_HSIC>;
665 clock-names = "usbhost";
670 compatible = "rockchip,rk3288-i2c";
671 reg = <0xff650000 0x1000>;
672 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
673 #address-cells = <1>;
676 clocks = <&cru PCLK_I2C0>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&i2c0_xfer>;
683 compatible = "rockchip,rk3288-i2c";
684 reg = <0xff660000 0x1000>;
685 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
686 #address-cells = <1>;
689 clocks = <&cru PCLK_I2C2>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&i2c2_xfer>;
696 compatible = "rockchip,rk3288-pwm";
697 reg = <0xff680000 0x10>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pwm0_pin>;
701 clocks = <&cru PCLK_PWM>;
707 compatible = "rockchip,rk3288-pwm";
708 reg = <0xff680010 0x10>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&pwm1_pin>;
712 clocks = <&cru PCLK_PWM>;
718 compatible = "rockchip,rk3288-pwm";
719 reg = <0xff680020 0x10>;
721 pinctrl-names = "default";
722 pinctrl-0 = <&pwm2_pin>;
723 clocks = <&cru PCLK_PWM>;
729 compatible = "rockchip,rk3288-pwm";
730 reg = <0xff680030 0x10>;
732 pinctrl-names = "default";
733 pinctrl-0 = <&pwm3_pin>;
734 clocks = <&cru PCLK_PWM>;
739 bus_intmem@ff700000 {
740 compatible = "mmio-sram";
741 reg = <0xff700000 0x18000>;
742 #address-cells = <1>;
744 ranges = <0 0xff700000 0x18000>;
746 compatible = "rockchip,rk3066-smp-sram";
752 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
753 reg = <0xff720000 0x1000>;
756 qos_gpu_r: qos@ffaa0000 {
757 compatible = "syscon";
758 reg = <0xffaa0000 0x20>;
761 qos_gpu_w: qos@ffaa0080 {
762 compatible = "syscon";
763 reg = <0xffaa0080 0x20>;
766 qos_vio1_vop: qos@ffad0000 {
767 compatible = "syscon";
768 reg = <0xffad0000 0x20>;
771 qos_vio1_isp_w0: qos@ffad0100 {
772 compatible = "syscon";
773 reg = <0xffad0100 0x20>;
776 qos_vio1_isp_w1: qos@ffad0180 {
777 compatible = "syscon";
778 reg = <0xffad0180 0x20>;
781 qos_vio0_vop: qos@ffad0400 {
782 compatible = "syscon";
783 reg = <0xffad0400 0x20>;
786 qos_vio0_vip: qos@ffad0480 {
787 compatible = "syscon";
788 reg = <0xffad0480 0x20>;
791 qos_vio0_iep: qos@ffad0500 {
792 compatible = "syscon";
793 reg = <0xffad0500 0x20>;
796 qos_vio2_rga_r: qos@ffad0800 {
797 compatible = "syscon";
798 reg = <0xffad0800 0x20>;
801 qos_vio2_rga_w: qos@ffad0880 {
802 compatible = "syscon";
803 reg = <0xffad0880 0x20>;
806 qos_vio1_isp_r: qos@ffad0900 {
807 compatible = "syscon";
808 reg = <0xffad0900 0x20>;
811 qos_video: qos@ffae0000 {
812 compatible = "syscon";
813 reg = <0xffae0000 0x20>;
816 qos_hevc_r: qos@ffaf0000 {
817 compatible = "syscon";
818 reg = <0xffaf0000 0x20>;
821 qos_hevc_w: qos@ffaf0080 {
822 compatible = "syscon";
823 reg = <0xffaf0080 0x20>;
826 pmu: power-management@ff730000 {
827 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
828 reg = <0xff730000 0x100>;
830 power: power-controller {
831 compatible = "rockchip,rk3288-power-controller";
832 #power-domain-cells = <1>;
833 #address-cells = <1>;
837 * Note: Although SCLK_* are the working clocks
838 * of device without including on the NOC, needed for
841 * The clocks on the which NOC:
842 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
843 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
844 * ACLK_RGA is on ACLK_RGA_NIU.
845 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
847 * Which clock are device clocks:
849 * *_IEP IEP:Image Enhancement Processor
850 * *_ISP ISP:Image Signal Processing
851 * *_VIP VIP:Video Input Processor
852 * *_VOP* VOP:Visual Output Processor
859 pd_vio@RK3288_PD_VIO {
860 reg = <RK3288_PD_VIO>;
861 clocks = <&cru ACLK_IEP>,
875 <&cru PCLK_EDP_CTRL>,
876 <&cru PCLK_HDMI_CTRL>,
877 <&cru PCLK_LVDS_PHY>,
878 <&cru PCLK_MIPI_CSI>,
879 <&cru PCLK_MIPI_DSI0>,
880 <&cru PCLK_MIPI_DSI1>,
886 pm_qos = <&qos_vio0_iep>,
898 * Note: The following 3 are HEVC(H.265) clocks,
899 * and on the ACLK_HEVC_NIU (NOC).
901 pd_hevc@RK3288_PD_HEVC {
902 reg = <RK3288_PD_HEVC>;
903 clocks = <&cru ACLK_HEVC>,
904 <&cru SCLK_HEVC_CABAC>,
905 <&cru SCLK_HEVC_CORE>;
906 pm_qos = <&qos_hevc_r>,
911 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
912 * (video endecoder & decoder) clocks that on the
913 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
915 pd_video@RK3288_PD_VIDEO {
916 reg = <RK3288_PD_VIDEO>;
917 clocks = <&cru ACLK_VCODEC>,
919 pm_qos = <&qos_video>;
923 * Note: ACLK_GPU is the GPU clock,
924 * and on the ACLK_GPU_NIU (NOC).
926 pd_gpu@RK3288_PD_GPU {
927 reg = <RK3288_PD_GPU>;
928 clocks = <&cru ACLK_GPU>;
929 pm_qos = <&qos_gpu_r>,
935 compatible = "syscon-reboot-mode";
937 mode-normal = <BOOT_NORMAL>;
938 mode-recovery = <BOOT_RECOVERY>;
939 mode-bootloader = <BOOT_FASTBOOT>;
940 mode-loader = <BOOT_BL_DOWNLOAD>;
941 mode-ums = <BOOT_UMS>;
945 sgrf: syscon@ff740000 {
946 compatible = "rockchip,rk3288-sgrf", "syscon";
947 reg = <0xff740000 0x1000>;
950 cru: clock-controller@ff760000 {
951 compatible = "rockchip,rk3288-cru";
952 reg = <0xff760000 0x1000>;
953 rockchip,grf = <&grf>;
956 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
957 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
958 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
959 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
960 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
962 assigned-clock-rates = <0>, <0>,
963 <594000000>, <400000000>,
964 <500000000>, <300000000>,
965 <150000000>, <75000000>,
966 <300000000>, <150000000>,
968 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
971 grf: syscon@ff770000 {
972 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
973 reg = <0xff770000 0x1000>;
976 compatible = "rockchip,rk3288-dp-phy";
977 clocks = <&cru SCLK_EDP_24M>;
983 io_domains: io-domains {
984 compatible = "rockchip,rk3288-io-voltage-domain";
989 compatible = "rockchip,rk3288-usb-phy";
990 #address-cells = <1>;
994 usbphy0: usb-phy@320 {
997 clocks = <&cru SCLK_OTGPHY0>;
998 clock-names = "phyclk";
1000 resets = <&cru SRST_USBOTG_PHY>;
1001 reset-names = "phy-reset";
1004 usbphy1: usb-phy@334 {
1007 clocks = <&cru SCLK_OTGPHY1>;
1008 clock-names = "phyclk";
1012 usbphy2: usb-phy@348 {
1015 clocks = <&cru SCLK_OTGPHY2>;
1016 clock-names = "phyclk";
1018 resets = <&cru SRST_USBHOST1_PHY>;
1019 reset-names = "phy-reset";
1024 wdt: watchdog@ff800000 {
1025 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1026 reg = <0xff800000 0x100>;
1027 clocks = <&cru PCLK_WDT>;
1028 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1029 status = "disabled";
1032 spdif: sound@ff88b0000 {
1033 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1034 reg = <0xff8b0000 0x10000>;
1035 #sound-dai-cells = <0>;
1036 clock-names = "hclk", "mclk";
1037 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1038 dmas = <&dmac_bus_s 3>;
1040 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&spdif_tx>;
1043 rockchip,grf = <&grf>;
1044 status = "disabled";
1048 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1049 reg = <0xff890000 0x10000>;
1050 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1051 #address-cells = <1>;
1053 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1054 dma-names = "tx", "rx";
1055 clock-names = "i2s_hclk", "i2s_clk";
1056 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1057 pinctrl-names = "default";
1058 pinctrl-0 = <&i2s0_bus>;
1059 rockchip,playback-channels = <8>;
1060 rockchip,capture-channels = <2>;
1061 status = "disabled";
1065 compatible = "rockchip,rk3288-rga";
1066 reg = <0xff920000 0x180>;
1067 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1068 interrupt-names = "rga";
1069 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1070 clock-names = "aclk", "hclk", "sclk";
1072 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1074 reset-names = "core", "axi", "ahb";
1075 status = "disabled";
1078 vopb: vop@ff930000 {
1079 compatible = "rockchip,rk3288-vop";
1080 reg = <0xff930000 0x19c>;
1081 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1082 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1083 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1084 power-domains = <&power RK3288_PD_VIO>;
1085 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1086 reset-names = "axi", "ahb", "dclk";
1087 iommus = <&vopb_mmu>;
1088 status = "disabled";
1091 #address-cells = <1>;
1094 vopb_out_hdmi: endpoint@0 {
1096 remote-endpoint = <&hdmi_in_vopb>;
1099 vopb_out_edp: endpoint@1 {
1101 remote-endpoint = <&edp_in_vopb>;
1104 vopb_out_mipi: endpoint@2 {
1106 remote-endpoint = <&mipi_in_vopb>;
1109 vopb_out_lvds: endpoint@3 {
1111 remote-endpoint = <&lvds_in_vopb>;
1116 vopb_mmu: iommu@ff930300 {
1117 compatible = "rockchip,iommu";
1118 reg = <0xff930300 0x100>;
1119 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1120 interrupt-names = "vopb_mmu";
1121 power-domains = <&power RK3288_PD_VIO>;
1123 status = "disabled";
1126 vopl: vop@ff940000 {
1127 compatible = "rockchip,rk3288-vop";
1128 reg = <0xff940000 0x19c>;
1129 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1131 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1132 power-domains = <&power RK3288_PD_VIO>;
1133 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1134 reset-names = "axi", "ahb", "dclk";
1135 iommus = <&vopl_mmu>;
1136 status = "disabled";
1139 #address-cells = <1>;
1142 vopl_out_hdmi: endpoint@0 {
1144 remote-endpoint = <&hdmi_in_vopl>;
1147 vopl_out_edp: endpoint@1 {
1149 remote-endpoint = <&edp_in_vopl>;
1152 vopl_out_mipi: endpoint@2 {
1154 remote-endpoint = <&mipi_in_vopl>;
1157 vopl_out_lvds: endpoint@3 {
1159 remote-endpoint = <&lvds_in_vopl>;
1165 vopl_mmu: iommu@ff940300 {
1166 compatible = "rockchip,iommu";
1167 reg = <0xff940300 0x100>;
1168 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1169 interrupt-names = "vopl_mmu";
1170 power-domains = <&power RK3288_PD_VIO>;
1172 status = "disabled";
1175 mipi_dsi: mipi@ff960000 {
1176 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1177 reg = <0xff960000 0x4000>;
1178 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1179 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1180 clock-names = "ref", "pclk";
1181 power-domains = <&power RK3288_PD_VIO>;
1182 rockchip,grf = <&grf>;
1183 #address-cells = <1>;
1185 status = "disabled";
1189 #address-cells = <1>;
1191 mipi_in_vopb: endpoint@0 {
1193 remote-endpoint = <&vopb_out_mipi>;
1195 mipi_in_vopl: endpoint@1 {
1197 remote-endpoint = <&vopl_out_mipi>;
1204 compatible = "rockchip,rk3288-dp";
1205 reg = <0xff970000 0x4000>;
1206 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1208 clock-names = "dp", "pclk";
1211 resets = <&cru SRST_EDP>;
1213 rockchip,grf = <&grf>;
1214 status = "disabled";
1217 #address-cells = <1>;
1221 #address-cells = <1>;
1223 edp_in_vopb: endpoint@0 {
1225 remote-endpoint = <&vopb_out_edp>;
1227 edp_in_vopl: endpoint@1 {
1229 remote-endpoint = <&vopl_out_edp>;
1235 lvds: lvds@ff96c000 {
1236 compatible = "rockchip,rk3288-lvds";
1237 reg = <0xff96c000 0x4000>;
1238 clocks = <&cru PCLK_LVDS_PHY>;
1239 clock-names = "pclk_lvds";
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&lcdc0_ctl>;
1242 power-domains = <&power RK3288_PD_VIO>;
1243 rockchip,grf = <&grf>;
1244 status = "disabled";
1247 #address-cells = <1>;
1253 #address-cells = <1>;
1256 lvds_in_vopb: endpoint@0 {
1258 remote-endpoint = <&vopb_out_lvds>;
1260 lvds_in_vopl: endpoint@1 {
1262 remote-endpoint = <&vopl_out_lvds>;
1268 hdmi: hdmi@ff980000 {
1269 compatible = "rockchip,rk3288-dw-hdmi";
1270 reg = <0xff980000 0x20000>;
1272 rockchip,grf = <&grf>;
1273 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1274 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1275 clock-names = "iahb", "isfr";
1276 power-domains = <&power RK3288_PD_VIO>;
1277 status = "disabled";
1281 #address-cells = <1>;
1283 hdmi_in_vopb: endpoint@0 {
1285 remote-endpoint = <&vopb_out_hdmi>;
1287 hdmi_in_vopl: endpoint@1 {
1289 remote-endpoint = <&vopl_out_hdmi>;
1296 compatible = "arm,malit764",
1300 reg = <0xffa30000 0x10000>;
1301 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1302 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1304 interrupt-names = "JOB", "MMU", "GPU";
1305 clocks = <&cru ACLK_GPU>;
1306 clock-names = "clk_mali";
1307 operating-points-v2 = <&gpu_opp_table>;
1308 #cooling-cells = <2>; /* min followed by max */
1309 power-domains = <&power RK3288_PD_GPU>;
1310 status = "disabled";
1312 gpu_power_model: power_model {
1313 compatible = "arm,mali-simple-power-model";
1316 static-power = <300>;
1317 dynamic-power = <396>;
1318 ts = <32000 4700 (-80) 2>;
1319 thermal-zone = "gpu_thermal";
1323 gpu_opp_table: opp-table1 {
1324 compatible = "operating-points-v2";
1327 opp-hz = /bits/ 64 <100000000>;
1328 opp-microvolt = <950000>;
1331 opp-hz = /bits/ 64 <200000000>;
1332 opp-microvolt = <950000>;
1335 opp-hz = /bits/ 64 <300000000>;
1336 opp-microvolt = <1000000>;
1339 opp-hz = /bits/ 64 <400000000>;
1340 opp-microvolt = <1100000>;
1343 opp-hz = /bits/ 64 <600000000>;
1344 opp-microvolt = <1250000>;
1348 vpu: video-codec@ff9a0000 {
1349 compatible = "rockchip,rk3288-vpu";
1350 reg = <0xff9a0000 0x800>;
1351 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1353 interrupt-names = "vepu", "vdpu";
1354 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1355 clock-names = "aclk", "hclk";
1356 power-domains = <&power RK3288_PD_VIDEO>;
1357 iommus = <&vpu_mmu>;
1358 assigned-clocks = <&cru ACLK_VCODEC>;
1359 assigned-clock-rates = <400000000>;
1360 status = "disabled";
1363 vpu_service: vpu-service@ff9a0000 {
1364 compatible = "rockchip,vpu_service";
1365 reg = <0xff9a0000 0x800>;
1366 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1368 interrupt-names = "irq_enc", "irq_dec";
1369 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1370 clock-names = "aclk_vcodec", "hclk_vcodec";
1371 power-domains = <&power RK3288_PD_VIDEO>;
1372 rockchip,grf = <&grf>;
1373 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1374 reset-names = "video_a", "video_h";
1375 iommus = <&vpu_mmu>;
1376 iommu_enabled = <1>;
1378 status = "disabled";
1379 /* 0 means ion, 1 means drm */
1383 vpu_mmu: iommu@ff9a0800 {
1384 compatible = "rockchip,iommu";
1385 reg = <0xff9a0800 0x100>;
1386 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1387 interrupt-names = "vpu_mmu";
1388 power-domains = <&power RK3288_PD_VIDEO>;
1392 hevc_service: hevc-service@ff9c0000 {
1393 compatible = "rockchip,hevc_service";
1394 reg = <0xff9c0000 0x400>;
1395 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1396 interrupt-names = "irq_dec";
1397 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1398 <&cru SCLK_HEVC_CORE>,
1399 <&cru SCLK_HEVC_CABAC>;
1400 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1403 * The 4K hevc would also work well with 500/125/300/300,
1404 * no more err irq and reset request.
1406 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1407 <&cru SCLK_HEVC_CORE>,
1408 <&cru SCLK_HEVC_CABAC>;
1409 assigned-clock-rates = <400000000>, <100000000>,
1410 <300000000>, <300000000>;
1412 resets = <&cru SRST_HEVC>;
1413 reset-names = "video";
1414 power-domains = <&power RK3288_PD_HEVC>;
1415 rockchip,grf = <&grf>;
1417 iommus = <&hevc_mmu>;
1418 iommu_enabled = <1>;
1419 status = "disabled";
1420 /* 0 means ion, 1 means drm */
1424 hevc_mmu: iommu@ff9c0440 {
1425 compatible = "rockchip,iommu";
1426 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1427 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1428 interrupt-names = "hevc_mmu";
1429 power-domains = <&power RK3288_PD_HEVC>;
1433 gic: interrupt-controller@ffc01000 {
1434 compatible = "arm,gic-400";
1435 interrupt-controller;
1436 #interrupt-cells = <3>;
1437 #address-cells = <0>;
1439 reg = <0xffc01000 0x1000>,
1440 <0xffc02000 0x1000>,
1441 <0xffc04000 0x2000>,
1442 <0xffc06000 0x2000>;
1443 interrupts = <GIC_PPI 9 0xf04>;
1446 efuse: efuse@ffb40000 {
1447 compatible = "rockchip,rockchip-efuse";
1448 reg = <0xffb40000 0x20>;
1449 #address-cells = <1>;
1451 clocks = <&cru PCLK_EFUSE256>;
1452 clock-names = "pclk_efuse";
1454 cpu_leakage: cpu_leakage@17 {
1459 cif_isp0: cif_isp@ff910000 {
1460 compatible = "rockchip,rk3288-cif-isp";
1461 rockchip,grf = <&grf>;
1462 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1463 reg-names = "register", "csihost-register";
1464 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1465 <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1466 <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1467 <&cru SCLK_MIPIDSI_24M>;
1468 clock-names = "aclk_isp", "hclk_isp",
1469 "sclk_isp", "sclk_isp_jpe",
1470 "pclk_mipi_csi", "pclk_isp_in",
1472 resets = <&cru SRST_ISP>;
1473 reset-names = "rst_isp";
1474 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1475 interrupt-names = "cif_isp10_irq";
1476 status = "disabled";
1480 compatible = "rockchip,rk3288-pinctrl";
1481 rockchip,grf = <&grf>;
1482 rockchip,pmu = <&pmu>;
1483 #address-cells = <1>;
1487 gpio0: gpio0@ff750000 {
1488 compatible = "rockchip,gpio-bank";
1489 reg = <0xff750000 0x100>;
1490 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1491 clocks = <&cru PCLK_GPIO0>;
1496 interrupt-controller;
1497 #interrupt-cells = <2>;
1500 gpio1: gpio1@ff780000 {
1501 compatible = "rockchip,gpio-bank";
1502 reg = <0xff780000 0x100>;
1503 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1504 clocks = <&cru PCLK_GPIO1>;
1509 interrupt-controller;
1510 #interrupt-cells = <2>;
1513 gpio2: gpio2@ff790000 {
1514 compatible = "rockchip,gpio-bank";
1515 reg = <0xff790000 0x100>;
1516 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1517 clocks = <&cru PCLK_GPIO2>;
1522 interrupt-controller;
1523 #interrupt-cells = <2>;
1526 gpio3: gpio3@ff7a0000 {
1527 compatible = "rockchip,gpio-bank";
1528 reg = <0xff7a0000 0x100>;
1529 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1530 clocks = <&cru PCLK_GPIO3>;
1535 interrupt-controller;
1536 #interrupt-cells = <2>;
1539 gpio4: gpio4@ff7b0000 {
1540 compatible = "rockchip,gpio-bank";
1541 reg = <0xff7b0000 0x100>;
1542 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1543 clocks = <&cru PCLK_GPIO4>;
1548 interrupt-controller;
1549 #interrupt-cells = <2>;
1552 gpio5: gpio5@ff7c0000 {
1553 compatible = "rockchip,gpio-bank";
1554 reg = <0xff7c0000 0x100>;
1555 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1556 clocks = <&cru PCLK_GPIO5>;
1561 interrupt-controller;
1562 #interrupt-cells = <2>;
1565 gpio6: gpio6@ff7d0000 {
1566 compatible = "rockchip,gpio-bank";
1567 reg = <0xff7d0000 0x100>;
1568 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1569 clocks = <&cru PCLK_GPIO6>;
1574 interrupt-controller;
1575 #interrupt-cells = <2>;
1578 gpio7: gpio7@ff7e0000 {
1579 compatible = "rockchip,gpio-bank";
1580 reg = <0xff7e0000 0x100>;
1581 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1582 clocks = <&cru PCLK_GPIO7>;
1587 interrupt-controller;
1588 #interrupt-cells = <2>;
1591 gpio8: gpio8@ff7f0000 {
1592 compatible = "rockchip,gpio-bank";
1593 reg = <0xff7f0000 0x100>;
1594 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1595 clocks = <&cru PCLK_GPIO8>;
1600 interrupt-controller;
1601 #interrupt-cells = <2>;
1605 hdmi_ddc: hdmi-ddc {
1606 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1607 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1611 pcfg_pull_up: pcfg-pull-up {
1615 pcfg_pull_down: pcfg-pull-down {
1619 pcfg_pull_none: pcfg-pull-none {
1623 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1625 drive-strength = <12>;
1629 global_pwroff: global-pwroff {
1630 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1633 ddrio_pwroff: ddrio-pwroff {
1634 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1637 ddr0_retention: ddr0-retention {
1638 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1641 ddr1_retention: ddr1-retention {
1642 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1648 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1653 i2c0_xfer: i2c0-xfer {
1654 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1655 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1660 i2c1_xfer: i2c1-xfer {
1661 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1662 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1667 i2c2_xfer: i2c2-xfer {
1668 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1669 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1674 i2c3_xfer: i2c3-xfer {
1675 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1676 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1681 i2c4_xfer: i2c4-xfer {
1682 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1683 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1688 i2c5_xfer: i2c5-xfer {
1689 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1690 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1695 i2s0_bus: i2s0-bus {
1696 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1697 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1698 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1699 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1700 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1701 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1706 lcdc0_ctl: lcdc0-ctl {
1707 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1708 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1709 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1710 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1715 sdmmc_clk: sdmmc-clk {
1716 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1719 sdmmc_cmd: sdmmc-cmd {
1720 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1723 sdmmc_cd: sdmcc-cd {
1724 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1727 sdmmc_bus1: sdmmc-bus1 {
1728 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1731 sdmmc_bus4: sdmmc-bus4 {
1732 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1733 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1734 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1735 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1740 sdio0_bus1: sdio0-bus1 {
1741 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1744 sdio0_bus4: sdio0-bus4 {
1745 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1746 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1747 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1748 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1751 sdio0_cmd: sdio0-cmd {
1752 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1755 sdio0_clk: sdio0-clk {
1756 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1759 sdio0_cd: sdio0-cd {
1760 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1763 sdio0_wp: sdio0-wp {
1764 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1767 sdio0_pwr: sdio0-pwr {
1768 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1771 sdio0_bkpwr: sdio0-bkpwr {
1772 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1775 sdio0_int: sdio0-int {
1776 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1781 sdio1_bus1: sdio1-bus1 {
1782 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1785 sdio1_bus4: sdio1-bus4 {
1786 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1787 <3 25 4 &pcfg_pull_up>,
1788 <3 26 4 &pcfg_pull_up>,
1789 <3 27 4 &pcfg_pull_up>;
1792 sdio1_cd: sdio1-cd {
1793 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1796 sdio1_wp: sdio1-wp {
1797 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1800 sdio1_bkpwr: sdio1-bkpwr {
1801 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1804 sdio1_int: sdio1-int {
1805 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1808 sdio1_cmd: sdio1-cmd {
1809 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1812 sdio1_clk: sdio1-clk {
1813 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1816 sdio1_pwr: sdio1-pwr {
1817 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1822 emmc_clk: emmc-clk {
1823 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1826 emmc_cmd: emmc-cmd {
1827 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1830 emmc_pwr: emmc-pwr {
1831 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1834 emmc_bus1: emmc-bus1 {
1835 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1838 emmc_bus4: emmc-bus4 {
1839 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1840 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1841 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1842 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1845 emmc_bus8: emmc-bus8 {
1846 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1847 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1848 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1849 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1850 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1851 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1852 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1853 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1858 spi0_clk: spi0-clk {
1859 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1861 spi0_cs0: spi0-cs0 {
1862 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1865 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1868 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1870 spi0_cs1: spi0-cs1 {
1871 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1875 spi1_clk: spi1-clk {
1876 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1878 spi1_cs0: spi1-cs0 {
1879 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1882 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1885 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1890 spi2_cs1: spi2-cs1 {
1891 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1893 spi2_clk: spi2-clk {
1894 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1896 spi2_cs0: spi2-cs0 {
1897 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1900 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1903 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1908 uart0_xfer: uart0-xfer {
1909 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1910 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1913 uart0_cts: uart0-cts {
1914 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1917 uart0_rts: uart0-rts {
1918 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1923 uart1_xfer: uart1-xfer {
1924 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1925 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1928 uart1_cts: uart1-cts {
1929 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1932 uart1_rts: uart1-rts {
1933 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1938 uart2_xfer: uart2-xfer {
1939 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1940 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1942 /* no rts / cts for uart2 */
1946 uart3_xfer: uart3-xfer {
1947 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1948 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1951 uart3_cts: uart3-cts {
1952 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1955 uart3_rts: uart3-rts {
1956 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1961 uart4_xfer: uart4-xfer {
1962 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1963 <5 13 3 &pcfg_pull_none>;
1966 uart4_cts: uart4-cts {
1967 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1970 uart4_rts: uart4-rts {
1971 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1976 otp_gpio: otp-gpio {
1977 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1981 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1986 pwm0_pin: pwm0-pin {
1987 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1992 pwm1_pin: pwm1-pin {
1993 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1998 pwm2_pin: pwm2-pin {
1999 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2004 pwm3_pin: pwm3-pin {
2005 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2010 rgmii_pins: rgmii-pins {
2011 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2012 <3 31 3 &pcfg_pull_none>,
2013 <3 26 3 &pcfg_pull_none>,
2014 <3 27 3 &pcfg_pull_none>,
2015 <3 28 3 &pcfg_pull_none_12ma>,
2016 <3 29 3 &pcfg_pull_none_12ma>,
2017 <3 24 3 &pcfg_pull_none_12ma>,
2018 <3 25 3 &pcfg_pull_none_12ma>,
2019 <4 0 3 &pcfg_pull_none>,
2020 <4 5 3 &pcfg_pull_none>,
2021 <4 6 3 &pcfg_pull_none>,
2022 <4 9 3 &pcfg_pull_none_12ma>,
2023 <4 4 3 &pcfg_pull_none_12ma>,
2024 <4 1 3 &pcfg_pull_none>,
2025 <4 3 3 &pcfg_pull_none>;
2028 rmii_pins: rmii-pins {
2029 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2030 <3 31 3 &pcfg_pull_none>,
2031 <3 28 3 &pcfg_pull_none>,
2032 <3 29 3 &pcfg_pull_none>,
2033 <4 0 3 &pcfg_pull_none>,
2034 <4 5 3 &pcfg_pull_none>,
2035 <4 4 3 &pcfg_pull_none>,
2036 <4 1 3 &pcfg_pull_none>,
2037 <4 2 3 &pcfg_pull_none>,
2038 <4 3 3 &pcfg_pull_none>;
2043 spdif_tx: spdif-tx {
2044 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2049 cif_dvp_d2d9: cif-dvp-d2d9 {
2050 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2051 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2052 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2053 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2054 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2055 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2056 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2057 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2058 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2059 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2060 <2 11 RK_FUNC_1 &pcfg_pull_none>;