2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip_boot-mode.h>
49 #include "skeleton.dtsi"
52 compatible = "rockchip,rk3288";
54 interrupt-parent = <&gic>;
78 compatible = "arm,cortex-a12-pmu";
79 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
89 enable-method = "rockchip,rk3066-smp";
90 rockchip,pmu = <&pmu>;
94 compatible = "arm,cortex-a12";
96 resets = <&cru SRST_CORE0>;
112 #cooling-cells = <2>; /* min followed by max */
113 clock-latency = <40000>;
114 clocks = <&cru ARMCLK>;
118 compatible = "arm,cortex-a12";
120 resets = <&cru SRST_CORE1>;
124 compatible = "arm,cortex-a12";
126 resets = <&cru SRST_CORE2>;
130 compatible = "arm,cortex-a12";
132 resets = <&cru SRST_CORE3>;
137 compatible = "arm,amba-bus";
138 #address-cells = <1>;
142 dmac_peri: dma-controller@ff250000 {
143 compatible = "arm,pl330", "arm,primecell";
144 reg = <0xff250000 0x4000>;
145 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
148 arm,pl330-broken-no-flushp;
149 peripherals-req-type-burst;
150 clocks = <&cru ACLK_DMAC2>;
151 clock-names = "apb_pclk";
154 dmac_bus_ns: dma-controller@ff600000 {
155 compatible = "arm,pl330", "arm,primecell";
156 reg = <0xff600000 0x4000>;
157 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
160 arm,pl330-broken-no-flushp;
161 peripherals-req-type-burst;
162 clocks = <&cru ACLK_DMAC1>;
163 clock-names = "apb_pclk";
167 dmac_bus_s: dma-controller@ffb20000 {
168 compatible = "arm,pl330", "arm,primecell";
169 reg = <0xffb20000 0x4000>;
170 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 arm,pl330-broken-no-flushp;
174 peripherals-req-type-burst;
175 clocks = <&cru ACLK_DMAC1>;
176 clock-names = "apb_pclk";
181 #address-cells = <1>;
186 * The rk3288 cannot use the memory area above 0xfe000000
187 * for dma operations for some reason. While there is
188 * probably a better solution available somewhere, we
189 * haven't found it yet and while devices with 2GB of ram
190 * are not affected, this issue prevents 4GB from booting.
191 * So to make these devices at least bootable, block
192 * this area for the time being until the real solution
195 dma-unusable@fe000000 {
196 reg = <0xfe000000 0x1000000>;
201 compatible = "fixed-clock";
202 clock-frequency = <24000000>;
203 clock-output-names = "xin24m";
208 compatible = "rockchip,rk3288-dp-phy";
209 clocks = <&cru SCLK_EDP_24M>;
211 rockchip,grf = <&grf>;
217 compatible = "arm,armv7-timer";
218 arm,cpu-registers-not-fw-configured;
219 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
221 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
222 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
223 clock-frequency = <24000000>;
226 timer: timer@ff810000 {
227 compatible = "rockchip,rk3288-timer";
228 reg = <0xff810000 0x20>;
229 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&xin24m>, <&cru PCLK_TIMER>;
231 clock-names = "timer", "pclk";
235 compatible = "rockchip,display-subsystem";
236 ports = <&vopl_out>, <&vopb_out>;
239 sdmmc: dwmmc@ff0c0000 {
240 compatible = "rockchip,rk3288-dw-mshc";
241 clock-freq-min-max = <400000 150000000>;
242 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
243 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
244 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
245 fifo-depth = <0x100>;
246 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
247 reg = <0xff0c0000 0x4000>;
251 sdio0: dwmmc@ff0d0000 {
252 compatible = "rockchip,rk3288-dw-mshc";
253 clock-freq-min-max = <400000 150000000>;
254 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
255 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
256 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
257 fifo-depth = <0x100>;
258 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
259 reg = <0xff0d0000 0x4000>;
263 sdio1: dwmmc@ff0e0000 {
264 compatible = "rockchip,rk3288-dw-mshc";
265 clock-freq-min-max = <400000 150000000>;
266 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
267 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
268 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
269 fifo-depth = <0x100>;
270 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
271 reg = <0xff0e0000 0x4000>;
275 emmc: dwmmc@ff0f0000 {
276 compatible = "rockchip,rk3288-dw-mshc";
277 clock-freq-min-max = <400000 150000000>;
278 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
279 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
280 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
281 fifo-depth = <0x100>;
282 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
283 reg = <0xff0f0000 0x4000>;
288 saradc: saradc@ff100000 {
289 compatible = "rockchip,saradc";
290 reg = <0xff100000 0x100>;
291 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
292 #io-channel-cells = <1>;
293 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
294 clock-names = "saradc", "apb_pclk";
299 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
300 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
301 clock-names = "spiclk", "apb_pclk";
302 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
303 dma-names = "tx", "rx";
304 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
307 reg = <0xff110000 0x1000>;
308 #address-cells = <1>;
314 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
315 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
316 clock-names = "spiclk", "apb_pclk";
317 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
318 dma-names = "tx", "rx";
319 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
322 reg = <0xff120000 0x1000>;
323 #address-cells = <1>;
329 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
330 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
331 clock-names = "spiclk", "apb_pclk";
332 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
333 dma-names = "tx", "rx";
334 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
337 reg = <0xff130000 0x1000>;
338 #address-cells = <1>;
344 compatible = "rockchip,rk3288-i2c";
345 reg = <0xff140000 0x1000>;
346 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
350 clocks = <&cru PCLK_I2C1>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c1_xfer>;
357 compatible = "rockchip,rk3288-i2c";
358 reg = <0xff150000 0x1000>;
359 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
363 clocks = <&cru PCLK_I2C3>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c3_xfer>;
370 compatible = "rockchip,rk3288-i2c";
371 reg = <0xff160000 0x1000>;
372 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
373 #address-cells = <1>;
376 clocks = <&cru PCLK_I2C4>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c4_xfer>;
383 compatible = "rockchip,rk3288-i2c";
384 reg = <0xff170000 0x1000>;
385 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
386 #address-cells = <1>;
389 clocks = <&cru PCLK_I2C5>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&i2c5_xfer>;
395 uart0: serial@ff180000 {
396 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
397 reg = <0xff180000 0x100>;
398 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
402 clock-names = "baudclk", "apb_pclk";
403 pinctrl-names = "default";
404 pinctrl-0 = <&uart0_xfer>;
408 uart1: serial@ff190000 {
409 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
410 reg = <0xff190000 0x100>;
411 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
415 clock-names = "baudclk", "apb_pclk";
416 pinctrl-names = "default";
417 pinctrl-0 = <&uart1_xfer>;
421 uart2: serial@ff690000 {
422 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
423 reg = <0xff690000 0x100>;
424 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
428 clock-names = "baudclk", "apb_pclk";
429 pinctrl-names = "default";
430 pinctrl-0 = <&uart2_xfer>;
434 uart3: serial@ff1b0000 {
435 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
436 reg = <0xff1b0000 0x100>;
437 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
441 clock-names = "baudclk", "apb_pclk";
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart3_xfer>;
447 uart4: serial@ff1c0000 {
448 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
449 reg = <0xff1c0000 0x100>;
450 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
454 clock-names = "baudclk", "apb_pclk";
455 pinctrl-names = "default";
456 pinctrl-0 = <&uart4_xfer>;
461 #include "rk3288-thermal.dtsi"
464 tsadc: tsadc@ff280000 {
465 compatible = "rockchip,rk3288-tsadc";
466 reg = <0xff280000 0x100>;
467 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
469 clock-names = "tsadc", "apb_pclk";
470 resets = <&cru SRST_TSADC>;
471 reset-names = "tsadc-apb";
472 pinctrl-names = "init", "default", "sleep";
473 pinctrl-0 = <&otp_gpio>;
474 pinctrl-1 = <&otp_out>;
475 pinctrl-2 = <&otp_gpio>;
476 #thermal-sensor-cells = <1>;
477 rockchip,hw-tshut-temp = <95000>;
481 gmac: ethernet@ff290000 {
482 compatible = "rockchip,rk3288-gmac";
483 reg = <0xff290000 0x10000>;
484 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-names = "macirq";
486 rockchip,grf = <&grf>;
487 clocks = <&cru SCLK_MAC>,
488 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
491 clock-names = "stmmaceth",
492 "mac_clk_rx", "mac_clk_tx",
493 "clk_mac_ref", "clk_mac_refout",
494 "aclk_mac", "pclk_mac";
495 resets = <&cru SRST_MAC>;
496 reset-names = "stmmaceth";
501 usb_host0_ehci: usb@ff500000 {
502 compatible = "generic-ehci";
503 reg = <0xff500000 0x100>;
504 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&cru HCLK_USBHOST0>;
506 clock-names = "usbhost";
512 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
514 usb_host1: usb@ff540000 {
515 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
517 reg = <0xff540000 0x40000>;
518 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&cru HCLK_USBHOST1>;
523 phy-names = "usb2-phy";
527 usb_otg: usb@ff580000 {
528 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
530 reg = <0xff580000 0x40000>;
531 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cru HCLK_OTG0>;
535 g-np-tx-fifo-size = <16>;
536 g-rx-fifo-size = <275>;
537 g-tx-fifo-size = <256 128 128 64 64 32>;
540 phy-names = "usb2-phy";
544 usb_hsic: usb@ff5c0000 {
545 compatible = "generic-ehci";
546 reg = <0xff5c0000 0x100>;
547 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru HCLK_HSIC>;
549 clock-names = "usbhost";
554 compatible = "rockchip,rk3288-i2c";
555 reg = <0xff650000 0x1000>;
556 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
557 #address-cells = <1>;
560 clocks = <&cru PCLK_I2C0>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&i2c0_xfer>;
567 compatible = "rockchip,rk3288-i2c";
568 reg = <0xff660000 0x1000>;
569 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
570 #address-cells = <1>;
573 clocks = <&cru PCLK_I2C2>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&i2c2_xfer>;
580 compatible = "rockchip,rk3288-pwm";
581 reg = <0xff680000 0x10>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&pwm0_pin>;
585 clocks = <&cru PCLK_PWM>;
591 compatible = "rockchip,rk3288-pwm";
592 reg = <0xff680010 0x10>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&pwm1_pin>;
596 clocks = <&cru PCLK_PWM>;
602 compatible = "rockchip,rk3288-pwm";
603 reg = <0xff680020 0x10>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&pwm2_pin>;
607 clocks = <&cru PCLK_PWM>;
613 compatible = "rockchip,rk3288-pwm";
614 reg = <0xff680030 0x10>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&pwm3_pin>;
618 clocks = <&cru PCLK_PWM>;
623 bus_intmem@ff700000 {
624 compatible = "mmio-sram";
625 reg = <0xff700000 0x18000>;
626 #address-cells = <1>;
628 ranges = <0 0xff700000 0x18000>;
630 compatible = "rockchip,rk3066-smp-sram";
636 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
637 reg = <0xff720000 0x1000>;
640 pmu: power-management@ff730000 {
641 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
642 reg = <0xff730000 0x100>;
644 power: power-controller {
645 compatible = "rockchip,rk3288-power-controller";
646 #power-domain-cells = <1>;
647 #address-cells = <1>;
651 * Note: Although SCLK_* are the working clocks
652 * of device without including on the NOC, needed for
655 * The clocks on the which NOC:
656 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
657 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
658 * ACLK_RGA is on ACLK_RGA_NIU.
659 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
661 * Which clock are device clocks:
663 * *_IEP IEP:Image Enhancement Processor
664 * *_ISP ISP:Image Signal Processing
665 * *_VIP VIP:Video Input Processor
666 * *_VOP* VOP:Visual Output Processor
674 reg = <RK3288_PD_VIO>;
675 clocks = <&cru ACLK_IEP>,
689 <&cru PCLK_EDP_CTRL>,
690 <&cru PCLK_HDMI_CTRL>,
691 <&cru PCLK_LVDS_PHY>,
692 <&cru PCLK_MIPI_CSI>,
693 <&cru PCLK_MIPI_DSI0>,
694 <&cru PCLK_MIPI_DSI1>,
703 * Note: The following 3 are HEVC(H.265) clocks,
704 * and on the ACLK_HEVC_NIU (NOC).
707 reg = <RK3288_PD_HEVC>;
708 clocks = <&cru ACLK_HEVC>,
709 <&cru SCLK_HEVC_CABAC>,
710 <&cru SCLK_HEVC_CORE>;
714 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
715 * (video endecoder & decoder) clocks that on the
716 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
719 reg = <RK3288_PD_VIDEO>;
720 clocks = <&cru ACLK_VCODEC>,
725 * Note: ACLK_GPU is the GPU clock,
726 * and on the ACLK_GPU_NIU (NOC).
729 reg = <RK3288_PD_GPU>;
730 clocks = <&cru ACLK_GPU>;
735 compatible = "syscon-reboot-mode";
737 mode-normal = <BOOT_NORMAL>;
738 mode-recovery = <BOOT_RECOVERY>;
739 mode-bootloader = <BOOT_FASTBOOT>;
740 mode-loader = <BOOT_LOADER>;
741 mode-ums = <BOOT_UMS>;
745 sgrf: syscon@ff740000 {
746 compatible = "rockchip,rk3288-sgrf", "syscon";
747 reg = <0xff740000 0x1000>;
750 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3288-cru";
752 reg = <0xff760000 0x1000>;
753 rockchip,grf = <&grf>;
756 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
757 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
758 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
759 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
760 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
762 assigned-clock-rates = <0>, <0>,
763 <594000000>, <400000000>,
764 <500000000>, <300000000>,
765 <150000000>, <75000000>,
766 <300000000>, <150000000>,
768 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
771 grf: syscon@ff770000 {
772 compatible = "rockchip,rk3288-grf", "syscon";
773 reg = <0xff770000 0x1000>;
776 wdt: watchdog@ff800000 {
777 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
778 reg = <0xff800000 0x100>;
779 clocks = <&cru PCLK_WDT>;
780 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
784 spdif: sound@ff88b0000 {
785 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
786 reg = <0xff8b0000 0x10000>;
787 #sound-dai-cells = <0>;
788 clock-names = "hclk", "mclk";
789 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
790 dmas = <&dmac_bus_s 3>;
792 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
793 pinctrl-names = "default";
794 pinctrl-0 = <&spdif_tx>;
795 rockchip,grf = <&grf>;
800 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
801 reg = <0xff890000 0x10000>;
802 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>;
805 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
806 dma-names = "tx", "rx";
807 clock-names = "i2s_hclk", "i2s_clk";
808 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
809 pinctrl-names = "default";
810 pinctrl-0 = <&i2s0_bus>;
815 compatible = "rockchip,rk3288-vop";
816 reg = <0xff930000 0x19c>;
817 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
819 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
820 power-domains = <&power RK3288_PD_VIO>;
821 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
822 reset-names = "axi", "ahb", "dclk";
823 iommus = <&vopb_mmu>;
827 #address-cells = <1>;
830 vopb_out_hdmi: endpoint@0 {
832 remote-endpoint = <&hdmi_in_vopb>;
835 vopb_out_edp: endpoint@1 {
837 remote-endpoint = <&edp_in_vopb>;
840 vopb_out_mipi: endpoint@2 {
842 remote-endpoint = <&mipi_in_vopb>;
845 vopb_out_lvds: endpoint@3 {
847 remote-endpoint = <&lvds_in_vopb>;
852 vopb_mmu: iommu@ff930300 {
853 compatible = "rockchip,iommu";
854 reg = <0xff930300 0x100>;
855 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
856 interrupt-names = "vopb_mmu";
857 power-domains = <&power RK3288_PD_VIO>;
863 compatible = "rockchip,rk3288-vop";
864 reg = <0xff940000 0x19c>;
865 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
867 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
868 power-domains = <&power RK3288_PD_VIO>;
869 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
870 reset-names = "axi", "ahb", "dclk";
871 iommus = <&vopl_mmu>;
875 #address-cells = <1>;
878 vopl_out_hdmi: endpoint@0 {
880 remote-endpoint = <&hdmi_in_vopl>;
883 vopl_out_edp: endpoint@1 {
885 remote-endpoint = <&edp_in_vopl>;
888 vopl_out_mipi: endpoint@2 {
890 remote-endpoint = <&mipi_in_vopl>;
893 vopl_out_lvds: endpoint@3 {
895 remote-endpoint = <&lvds_in_vopl>;
901 vopl_mmu: iommu@ff940300 {
902 compatible = "rockchip,iommu";
903 reg = <0xff940300 0x100>;
904 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
905 interrupt-names = "vopl_mmu";
906 power-domains = <&power RK3288_PD_VIO>;
911 mipi_dsi: mipi@ff960000 {
912 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
913 reg = <0xff960000 0x4000>;
914 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
915 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
916 clock-names = "ref", "pclk";
917 rockchip,grf = <&grf>;
918 #address-cells = <1>;
923 #address-cells = <1>;
928 #address-cells = <1>;
930 mipi_in_vopb: endpoint@0 {
932 remote-endpoint = <&vopb_out_mipi>;
934 mipi_in_vopl: endpoint@1 {
936 remote-endpoint = <&vopl_out_mipi>;
943 compatible = "rockchip,rk3288-dp";
944 reg = <0xff970000 0x4000>;
945 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
947 clock-names = "dp", "pclk";
950 resets = <&cru SRST_EDP>;
952 rockchip,grf = <&grf>;
956 #address-cells = <1>;
960 #address-cells = <1>;
962 edp_in_vopb: endpoint@0 {
964 remote-endpoint = <&vopb_out_edp>;
966 edp_in_vopl: endpoint@1 {
968 remote-endpoint = <&vopl_out_edp>;
974 lvds: lvds@ff96c000 {
975 compatible = "rockchip,rk3288-lvds";
976 reg = <0xff96c000 0x4000>;
977 clocks = <&cru PCLK_LVDS_PHY>;
978 clock-names = "pclk_lvds";
979 pinctrl-names = "default";
980 pinctrl-0 = <&lcdc0_ctl>;
981 power-domains = <&power RK3288_PD_VIO>;
982 rockchip,grf = <&grf>;
986 #address-cells = <1>;
992 #address-cells = <1>;
995 lvds_in_vopb: endpoint@0 {
997 remote-endpoint = <&vopb_out_lvds>;
999 lvds_in_vopl: endpoint@1 {
1001 remote-endpoint = <&vopl_out_lvds>;
1007 hdmi: hdmi@ff980000 {
1008 compatible = "rockchip,rk3288-dw-hdmi";
1009 reg = <0xff980000 0x20000>;
1011 rockchip,grf = <&grf>;
1012 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1014 clock-names = "iahb", "isfr";
1015 power-domains = <&power RK3288_PD_VIO>;
1016 status = "disabled";
1020 #address-cells = <1>;
1022 hdmi_in_vopb: endpoint@0 {
1024 remote-endpoint = <&vopb_out_hdmi>;
1026 hdmi_in_vopl: endpoint@1 {
1028 remote-endpoint = <&vopl_out_hdmi>;
1035 compatible = "arm,malit764",
1039 reg = <0xffa30000 0x10000>;
1040 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1043 interrupt-names = "JOB", "MMU", "GPU";
1044 clocks = <&cru ACLK_GPU>;
1045 clock-names = "clk_mali";
1046 operating-points = <
1049 /* 500000 1200000 - See crosbug.com/p/33857 */
1055 #cooling-cells = <2>; /* min followed by max */
1056 power-domains = <&power RK3288_PD_GPU>;
1057 status = "disabled";
1060 vpu: video-codec@ff9a0000 {
1061 compatible = "rockchip,rk3288-vpu";
1062 reg = <0xff9a0000 0x800>;
1063 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1065 interrupt-names = "vepu", "vdpu";
1066 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1067 clock-names = "aclk", "hclk";
1068 power-domains = <&power RK3288_PD_VIDEO>;
1069 iommus = <&vpu_mmu>;
1070 assigned-clocks = <&cru ACLK_VCODEC>;
1071 assigned-clock-rates = <400000000>;
1072 status = "disabled";
1075 vpu_service: vpu-service@ff9a0000 {
1076 compatible = "rockchip,vpu_service";
1077 reg = <0xff9a0000 0x800>;
1078 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1079 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1080 interrupt-names = "irq_enc", "irq_dec";
1081 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1082 clock-names = "aclk_vcodec", "hclk_vcodec";
1083 power-domains = <&power RK3288_PD_VIDEO>;
1084 rockchip,grf = <&grf>;
1085 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1086 reset-names = "video_a", "video_h";
1087 iommus = <&vpu_mmu>;
1088 iommu_enabled = <1>;
1090 status = "disabled";
1093 vpu_mmu: iommu@ff9a0800 {
1094 compatible = "rockchip,iommu";
1095 reg = <0xff9a0800 0x100>;
1096 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1097 interrupt-names = "vpu_mmu";
1098 power-domains = <&power RK3288_PD_VIDEO>;
1102 hevc_service: hevc-service@ff9c0000 {
1103 compatible = "rockchip,hevc_service";
1104 reg = <0xff9c0000 0x400>;
1105 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1106 interrupt-names = "irq_dec";
1107 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1108 <&cru SCLK_HEVC_CORE>,
1109 <&cru SCLK_HEVC_CABAC>;
1110 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1112 resets = <&cru SRST_HEVC>;
1113 reset-names = "video";
1114 power-domains = <&power RK3288_PD_HEVC>;
1115 rockchip,grf = <&grf>;
1117 iommus = <&hevc_mmu>;
1118 iommu_enabled = <1>;
1119 status = "disabled";
1122 hevc_mmu: iommu@ff9c0440 {
1123 compatible = "rockchip,iommu";
1124 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1125 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "hevc_mmu";
1127 power-domains = <&power RK3288_PD_HEVC>;
1131 gic: interrupt-controller@ffc01000 {
1132 compatible = "arm,gic-400";
1133 interrupt-controller;
1134 #interrupt-cells = <3>;
1135 #address-cells = <0>;
1137 reg = <0xffc01000 0x1000>,
1138 <0xffc02000 0x1000>,
1139 <0xffc04000 0x2000>,
1140 <0xffc06000 0x2000>;
1141 interrupts = <GIC_PPI 9 0xf04>;
1144 efuse: efuse@ffb40000 {
1145 compatible = "rockchip,rockchip-efuse";
1146 reg = <0xffb40000 0x20>;
1147 #address-cells = <1>;
1149 clocks = <&cru PCLK_EFUSE256>;
1150 clock-names = "pclk_efuse";
1152 cpu_leakage: cpu_leakage@17 {
1158 compatible = "rockchip,rk3288-usb-phy";
1159 rockchip,grf = <&grf>;
1160 #address-cells = <1>;
1162 status = "disabled";
1167 clocks = <&cru SCLK_OTGPHY0>;
1168 clock-names = "phyclk";
1174 clocks = <&cru SCLK_OTGPHY1>;
1175 clock-names = "phyclk";
1181 clocks = <&cru SCLK_OTGPHY2>;
1182 clock-names = "phyclk";
1187 compatible = "rockchip,rk3288-pinctrl";
1188 rockchip,grf = <&grf>;
1189 rockchip,pmu = <&pmu>;
1190 #address-cells = <1>;
1194 gpio0: gpio0@ff750000 {
1195 compatible = "rockchip,gpio-bank";
1196 reg = <0xff750000 0x100>;
1197 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&cru PCLK_GPIO0>;
1203 interrupt-controller;
1204 #interrupt-cells = <2>;
1207 gpio1: gpio1@ff780000 {
1208 compatible = "rockchip,gpio-bank";
1209 reg = <0xff780000 0x100>;
1210 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1211 clocks = <&cru PCLK_GPIO1>;
1216 interrupt-controller;
1217 #interrupt-cells = <2>;
1220 gpio2: gpio2@ff790000 {
1221 compatible = "rockchip,gpio-bank";
1222 reg = <0xff790000 0x100>;
1223 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1224 clocks = <&cru PCLK_GPIO2>;
1229 interrupt-controller;
1230 #interrupt-cells = <2>;
1233 gpio3: gpio3@ff7a0000 {
1234 compatible = "rockchip,gpio-bank";
1235 reg = <0xff7a0000 0x100>;
1236 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&cru PCLK_GPIO3>;
1242 interrupt-controller;
1243 #interrupt-cells = <2>;
1246 gpio4: gpio4@ff7b0000 {
1247 compatible = "rockchip,gpio-bank";
1248 reg = <0xff7b0000 0x100>;
1249 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&cru PCLK_GPIO4>;
1255 interrupt-controller;
1256 #interrupt-cells = <2>;
1259 gpio5: gpio5@ff7c0000 {
1260 compatible = "rockchip,gpio-bank";
1261 reg = <0xff7c0000 0x100>;
1262 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1263 clocks = <&cru PCLK_GPIO5>;
1268 interrupt-controller;
1269 #interrupt-cells = <2>;
1272 gpio6: gpio6@ff7d0000 {
1273 compatible = "rockchip,gpio-bank";
1274 reg = <0xff7d0000 0x100>;
1275 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1276 clocks = <&cru PCLK_GPIO6>;
1281 interrupt-controller;
1282 #interrupt-cells = <2>;
1285 gpio7: gpio7@ff7e0000 {
1286 compatible = "rockchip,gpio-bank";
1287 reg = <0xff7e0000 0x100>;
1288 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1289 clocks = <&cru PCLK_GPIO7>;
1294 interrupt-controller;
1295 #interrupt-cells = <2>;
1298 gpio8: gpio8@ff7f0000 {
1299 compatible = "rockchip,gpio-bank";
1300 reg = <0xff7f0000 0x100>;
1301 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&cru PCLK_GPIO8>;
1307 interrupt-controller;
1308 #interrupt-cells = <2>;
1312 hdmi_ddc: hdmi-ddc {
1313 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1314 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1318 pcfg_pull_up: pcfg-pull-up {
1322 pcfg_pull_down: pcfg-pull-down {
1326 pcfg_pull_none: pcfg-pull-none {
1330 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1332 drive-strength = <12>;
1336 global_pwroff: global-pwroff {
1337 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1340 ddrio_pwroff: ddrio-pwroff {
1341 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1344 ddr0_retention: ddr0-retention {
1345 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1348 ddr1_retention: ddr1-retention {
1349 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1355 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1360 i2c0_xfer: i2c0-xfer {
1361 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1362 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1367 i2c1_xfer: i2c1-xfer {
1368 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1369 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1374 i2c2_xfer: i2c2-xfer {
1375 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1376 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1381 i2c3_xfer: i2c3-xfer {
1382 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1383 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1388 i2c4_xfer: i2c4-xfer {
1389 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1390 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1395 i2c5_xfer: i2c5-xfer {
1396 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1397 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1402 i2s0_bus: i2s0-bus {
1403 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1404 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1405 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1406 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1407 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1408 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1413 lcdc0_ctl: lcdc0-ctl {
1414 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1415 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1416 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1417 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1422 sdmmc_clk: sdmmc-clk {
1423 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1426 sdmmc_cmd: sdmmc-cmd {
1427 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1430 sdmmc_cd: sdmcc-cd {
1431 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1434 sdmmc_bus1: sdmmc-bus1 {
1435 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1438 sdmmc_bus4: sdmmc-bus4 {
1439 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1440 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1441 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1442 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1447 sdio0_bus1: sdio0-bus1 {
1448 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1451 sdio0_bus4: sdio0-bus4 {
1452 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1453 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1454 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1455 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1458 sdio0_cmd: sdio0-cmd {
1459 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1462 sdio0_clk: sdio0-clk {
1463 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1466 sdio0_cd: sdio0-cd {
1467 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1470 sdio0_wp: sdio0-wp {
1471 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1474 sdio0_pwr: sdio0-pwr {
1475 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1478 sdio0_bkpwr: sdio0-bkpwr {
1479 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1482 sdio0_int: sdio0-int {
1483 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1488 sdio1_bus1: sdio1-bus1 {
1489 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1492 sdio1_bus4: sdio1-bus4 {
1493 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1494 <3 25 4 &pcfg_pull_up>,
1495 <3 26 4 &pcfg_pull_up>,
1496 <3 27 4 &pcfg_pull_up>;
1499 sdio1_cd: sdio1-cd {
1500 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1503 sdio1_wp: sdio1-wp {
1504 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1507 sdio1_bkpwr: sdio1-bkpwr {
1508 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1511 sdio1_int: sdio1-int {
1512 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1515 sdio1_cmd: sdio1-cmd {
1516 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1519 sdio1_clk: sdio1-clk {
1520 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1523 sdio1_pwr: sdio1-pwr {
1524 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1529 emmc_clk: emmc-clk {
1530 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1533 emmc_cmd: emmc-cmd {
1534 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1537 emmc_pwr: emmc-pwr {
1538 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1541 emmc_bus1: emmc-bus1 {
1542 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1545 emmc_bus4: emmc-bus4 {
1546 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1547 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1548 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1549 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1552 emmc_bus8: emmc-bus8 {
1553 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1554 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1555 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1556 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1557 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1558 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1559 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1560 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1565 spi0_clk: spi0-clk {
1566 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1568 spi0_cs0: spi0-cs0 {
1569 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1572 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1575 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1577 spi0_cs1: spi0-cs1 {
1578 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1582 spi1_clk: spi1-clk {
1583 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1585 spi1_cs0: spi1-cs0 {
1586 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1589 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1592 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1597 spi2_cs1: spi2-cs1 {
1598 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1600 spi2_clk: spi2-clk {
1601 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1603 spi2_cs0: spi2-cs0 {
1604 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1607 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1610 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1615 uart0_xfer: uart0-xfer {
1616 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1617 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1620 uart0_cts: uart0-cts {
1621 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1624 uart0_rts: uart0-rts {
1625 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1630 uart1_xfer: uart1-xfer {
1631 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1632 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1635 uart1_cts: uart1-cts {
1636 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1639 uart1_rts: uart1-rts {
1640 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1645 uart2_xfer: uart2-xfer {
1646 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1647 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1649 /* no rts / cts for uart2 */
1653 uart3_xfer: uart3-xfer {
1654 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1655 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1658 uart3_cts: uart3-cts {
1659 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1662 uart3_rts: uart3-rts {
1663 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1668 uart4_xfer: uart4-xfer {
1669 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1670 <5 13 3 &pcfg_pull_none>;
1673 uart4_cts: uart4-cts {
1674 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1677 uart4_rts: uart4-rts {
1678 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1683 otp_gpio: otp-gpio {
1684 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1688 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1693 pwm0_pin: pwm0-pin {
1694 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1699 pwm1_pin: pwm1-pin {
1700 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1705 pwm2_pin: pwm2-pin {
1706 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1711 pwm3_pin: pwm3-pin {
1712 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1717 rgmii_pins: rgmii-pins {
1718 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1719 <3 31 3 &pcfg_pull_none>,
1720 <3 26 3 &pcfg_pull_none>,
1721 <3 27 3 &pcfg_pull_none>,
1722 <3 28 3 &pcfg_pull_none_12ma>,
1723 <3 29 3 &pcfg_pull_none_12ma>,
1724 <3 24 3 &pcfg_pull_none_12ma>,
1725 <3 25 3 &pcfg_pull_none_12ma>,
1726 <4 0 3 &pcfg_pull_none>,
1727 <4 5 3 &pcfg_pull_none>,
1728 <4 6 3 &pcfg_pull_none>,
1729 <4 9 3 &pcfg_pull_none_12ma>,
1730 <4 4 3 &pcfg_pull_none_12ma>,
1731 <4 1 3 &pcfg_pull_none>,
1732 <4 3 3 &pcfg_pull_none>;
1735 rmii_pins: rmii-pins {
1736 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1737 <3 31 3 &pcfg_pull_none>,
1738 <3 28 3 &pcfg_pull_none>,
1739 <3 29 3 &pcfg_pull_none>,
1740 <4 0 3 &pcfg_pull_none>,
1741 <4 5 3 &pcfg_pull_none>,
1742 <4 4 3 &pcfg_pull_none>,
1743 <4 1 3 &pcfg_pull_none>,
1744 <4 2 3 &pcfg_pull_none>,
1745 <4 3 3 &pcfg_pull_none>;
1750 spdif_tx: spdif-tx {
1751 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;