arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 mshc0 = &emmc;
  63                 mshc1 = &sdmmc;
  64                 mshc2 = &sdio0;
  65                 mshc3 = &sdio1;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         arm-pmu {
  77                 compatible = "arm,cortex-a12-pmu";
  78                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  83         };
  84
  85         cpus {
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88                 enable-method = "rockchip,rk3066-smp";
  89                 rockchip,pmu = <&pmu>;
  90
  91                 cpu0: cpu@500 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x500>;
  95                         resets = <&cru SRST_CORE0>;
  96                         operating-points = <
  97                                 /* KHz    uV */
  98                                 1608000 1350000
  99                                 1512000 1300000
 100                                 1416000 1200000
 101                                 1200000 1100000
 102                                 1008000 1050000
 103                                  816000 1000000
 104                                  696000  950000
 105                                  600000  900000
 106                                  408000  900000
 107                                  312000  900000
 108                                  216000  900000
 109                                  126000  900000
 110                         >;
 111                         #cooling-cells = <2>; /* min followed by max */
 112                         clock-latency = <40000>;
 113                         clocks = <&cru ARMCLK>;
 114                 };
 115                 cpu1: cpu@501 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a12";
 118                         reg = <0x501>;
 119                         resets = <&cru SRST_CORE1>;
 120                 };
 121                 cpu2: cpu@502 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x502>;
 125                         resets = <&cru SRST_CORE2>;
 126                 };
 127                 cpu3: cpu@503 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a12";
 130                         reg = <0x503>;
 131                         resets = <&cru SRST_CORE3>;
 132                 };
 133         };
 134
 135         amba {
 136                 compatible = "arm,amba-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140
 141                 dmac_peri: dma-controller@ff250000 {
 142                         compatible = "arm,pl330", "arm,primecell";
 143                         reg = <0xff250000 0x4000>;
 144                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 146                         #dma-cells = <1>;
 147                         clocks = <&cru ACLK_DMAC2>;
 148                         clock-names = "apb_pclk";
 149                 };
 150
 151                 dmac_bus_ns: dma-controller@ff600000 {
 152                         compatible = "arm,pl330", "arm,primecell";
 153                         reg = <0xff600000 0x4000>;
 154                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 156                         #dma-cells = <1>;
 157                         clocks = <&cru ACLK_DMAC1>;
 158                         clock-names = "apb_pclk";
 159                         status = "disabled";
 160                 };
 161
 162                 dmac_bus_s: dma-controller@ffb20000 {
 163                         compatible = "arm,pl330", "arm,primecell";
 164                         reg = <0xffb20000 0x4000>;
 165                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 166                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 167                         #dma-cells = <1>;
 168                         clocks = <&cru ACLK_DMAC1>;
 169                         clock-names = "apb_pclk";
 170                 };
 171         };
 172
 173         reserved-memory {
 174                 #address-cells = <1>;
 175                 #size-cells = <1>;
 176                 ranges;
 177
 178                 /*
 179                  * The rk3288 cannot use the memory area above 0xfe000000
 180                  * for dma operations for some reason. While there is
 181                  * probably a better solution available somewhere, we
 182                  * haven't found it yet and while devices with 2GB of ram
 183                  * are not affected, this issue prevents 4GB from booting.
 184                  * So to make these devices at least bootable, block
 185                  * this area for the time being until the real solution
 186                  * is found.
 187                  */
 188                 dma-unusable@fe000000 {
 189                         reg = <0xfe000000 0x1000000>;
 190                 };
 191         };
 192
 193         xin24m: oscillator {
 194                 compatible = "fixed-clock";
 195                 clock-frequency = <24000000>;
 196                 clock-output-names = "xin24m";
 197                 #clock-cells = <0>;
 198         };
 199
 200         timer {
 201                 compatible = "arm,armv7-timer";
 202                 arm,cpu-registers-not-fw-configured;
 203                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 204                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 205                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 206                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 207                 clock-frequency = <24000000>;
 208         };
 209
 210         timer: timer@ff810000 {
 211                 compatible = "rockchip,rk3288-timer";
 212                 reg = <0xff810000 0x20>;
 213                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 215                 clock-names = "timer", "pclk";
 216         };
 217
 218         display-subsystem {
 219                 compatible = "rockchip,display-subsystem";
 220                 ports = <&vopl_out>, <&vopb_out>;
 221         };
 222
 223         sdmmc: dwmmc@ff0c0000 {
 224                 compatible = "rockchip,rk3288-dw-mshc";
 225                 clock-freq-min-max = <400000 150000000>;
 226                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 227                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 228                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 229                 fifo-depth = <0x100>;
 230                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 231                 reg = <0xff0c0000 0x4000>;
 232                 status = "disabled";
 233         };
 234
 235         sdio0: dwmmc@ff0d0000 {
 236                 compatible = "rockchip,rk3288-dw-mshc";
 237                 clock-freq-min-max = <400000 150000000>;
 238                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 239                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 240                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 241                 fifo-depth = <0x100>;
 242                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 243                 reg = <0xff0d0000 0x4000>;
 244                 status = "disabled";
 245         };
 246
 247         sdio1: dwmmc@ff0e0000 {
 248                 compatible = "rockchip,rk3288-dw-mshc";
 249                 clock-freq-min-max = <400000 150000000>;
 250                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 251                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 252                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 253                 fifo-depth = <0x100>;
 254                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 255                 reg = <0xff0e0000 0x4000>;
 256                 status = "disabled";
 257         };
 258
 259         emmc: dwmmc@ff0f0000 {
 260                 compatible = "rockchip,rk3288-dw-mshc";
 261                 clock-freq-min-max = <400000 150000000>;
 262                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 263                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 264                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 265                 fifo-depth = <0x100>;
 266                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 267                 reg = <0xff0f0000 0x4000>;
 268                 status = "disabled";
 269         };
 270
 271         saradc: saradc@ff100000 {
 272                 compatible = "rockchip,saradc";
 273                 reg = <0xff100000 0x100>;
 274                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 275                 #io-channel-cells = <1>;
 276                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 277                 clock-names = "saradc", "apb_pclk";
 278                 status = "disabled";
 279         };
 280
 281         spi0: spi@ff110000 {
 282                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 283                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 284                 clock-names = "spiclk", "apb_pclk";
 285                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 286                 dma-names = "tx", "rx";
 287                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 288                 pinctrl-names = "default";
 289                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 290                 reg = <0xff110000 0x1000>;
 291                 #address-cells = <1>;
 292                 #size-cells = <0>;
 293                 status = "disabled";
 294         };
 295
 296         spi1: spi@ff120000 {
 297                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 298                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 299                 clock-names = "spiclk", "apb_pclk";
 300                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 301                 dma-names = "tx", "rx";
 302                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 305                 reg = <0xff120000 0x1000>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 status = "disabled";
 309         };
 310
 311         spi2: spi@ff130000 {
 312                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 313                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 314                 clock-names = "spiclk", "apb_pclk";
 315                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 316                 dma-names = "tx", "rx";
 317                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 320                 reg = <0xff130000 0x1000>;
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323                 status = "disabled";
 324         };
 325
 326         i2c1: i2c@ff140000 {
 327                 compatible = "rockchip,rk3288-i2c";
 328                 reg = <0xff140000 0x1000>;
 329                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 clock-names = "i2c";
 333                 clocks = <&cru PCLK_I2C1>;
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&i2c1_xfer>;
 336                 status = "disabled";
 337         };
 338
 339         i2c3: i2c@ff150000 {
 340                 compatible = "rockchip,rk3288-i2c";
 341                 reg = <0xff150000 0x1000>;
 342                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 clock-names = "i2c";
 346                 clocks = <&cru PCLK_I2C3>;
 347                 pinctrl-names = "default";
 348                 pinctrl-0 = <&i2c3_xfer>;
 349                 status = "disabled";
 350         };
 351
 352         i2c4: i2c@ff160000 {
 353                 compatible = "rockchip,rk3288-i2c";
 354                 reg = <0xff160000 0x1000>;
 355                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 clock-names = "i2c";
 359                 clocks = <&cru PCLK_I2C4>;
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&i2c4_xfer>;
 362                 status = "disabled";
 363         };
 364
 365         i2c5: i2c@ff170000 {
 366                 compatible = "rockchip,rk3288-i2c";
 367                 reg = <0xff170000 0x1000>;
 368                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 clock-names = "i2c";
 372                 clocks = <&cru PCLK_I2C5>;
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&i2c5_xfer>;
 375                 status = "disabled";
 376         };
 377
 378         uart0: serial@ff180000 {
 379                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 380                 reg = <0xff180000 0x100>;
 381                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 382                 reg-shift = <2>;
 383                 reg-io-width = <4>;
 384                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 385                 clock-names = "baudclk", "apb_pclk";
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&uart0_xfer>;
 388                 status = "disabled";
 389         };
 390
 391         uart1: serial@ff190000 {
 392                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 393                 reg = <0xff190000 0x100>;
 394                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 395                 reg-shift = <2>;
 396                 reg-io-width = <4>;
 397                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 398                 clock-names = "baudclk", "apb_pclk";
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&uart1_xfer>;
 401                 status = "disabled";
 402         };
 403
 404         uart2: serial@ff690000 {
 405                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 406                 reg = <0xff690000 0x100>;
 407                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 408                 reg-shift = <2>;
 409                 reg-io-width = <4>;
 410                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 411                 clock-names = "baudclk", "apb_pclk";
 412                 pinctrl-names = "default";
 413                 pinctrl-0 = <&uart2_xfer>;
 414                 status = "disabled";
 415         };
 416
 417         uart3: serial@ff1b0000 {
 418                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 419                 reg = <0xff1b0000 0x100>;
 420                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 421                 reg-shift = <2>;
 422                 reg-io-width = <4>;
 423                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 424                 clock-names = "baudclk", "apb_pclk";
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&uart3_xfer>;
 427                 status = "disabled";
 428         };
 429
 430         uart4: serial@ff1c0000 {
 431                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 432                 reg = <0xff1c0000 0x100>;
 433                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 434                 reg-shift = <2>;
 435                 reg-io-width = <4>;
 436                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 437                 clock-names = "baudclk", "apb_pclk";
 438                 pinctrl-names = "default";
 439                 pinctrl-0 = <&uart4_xfer>;
 440                 status = "disabled";
 441         };
 442
 443         thermal-zones {
 444                 #include "rk3288-thermal.dtsi"
 445         };
 446
 447         tsadc: tsadc@ff280000 {
 448                 compatible = "rockchip,rk3288-tsadc";
 449                 reg = <0xff280000 0x100>;
 450                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 451                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 452                 clock-names = "tsadc", "apb_pclk";
 453                 resets = <&cru SRST_TSADC>;
 454                 reset-names = "tsadc-apb";
 455                 pinctrl-names = "init", "default", "sleep";
 456                 pinctrl-0 = <&otp_gpio>;
 457                 pinctrl-1 = <&otp_out>;
 458                 pinctrl-2 = <&otp_gpio>;
 459                 #thermal-sensor-cells = <1>;
 460                 rockchip,hw-tshut-temp = <95000>;
 461                 status = "disabled";
 462         };
 463
 464         gmac: ethernet@ff290000 {
 465                 compatible = "rockchip,rk3288-gmac";
 466                 reg = <0xff290000 0x10000>;
 467                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 468                 interrupt-names = "macirq";
 469                 rockchip,grf = <&grf>;
 470                 clocks = <&cru SCLK_MAC>,
 471                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 472                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 473                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 474                 clock-names = "stmmaceth",
 475                         "mac_clk_rx", "mac_clk_tx",
 476                         "clk_mac_ref", "clk_mac_refout",
 477                         "aclk_mac", "pclk_mac";
 478                 resets = <&cru SRST_MAC>;
 479                 reset-names = "stmmaceth";
 480                 status = "disabled";
 481         };
 482
 483         usb_host0_ehci: usb@ff500000 {
 484                 compatible = "generic-ehci";
 485                 reg = <0xff500000 0x100>;
 486                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 487                 clocks = <&cru HCLK_USBHOST0>;
 488                 clock-names = "usbhost";
 489                 phys = <&usbphy1>;
 490                 phy-names = "usb";
 491                 status = "disabled";
 492         };
 493
 494         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 495
 496         usb_host1: usb@ff540000 {
 497                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 498                                 "snps,dwc2";
 499                 reg = <0xff540000 0x40000>;
 500                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 501                 clocks = <&cru HCLK_USBHOST1>;
 502                 clock-names = "otg";
 503                 dr_mode = "host";
 504                 phys = <&usbphy2>;
 505                 phy-names = "usb2-phy";
 506                 status = "disabled";
 507         };
 508
 509         usb_otg: usb@ff580000 {
 510                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 511                                 "snps,dwc2";
 512                 reg = <0xff580000 0x40000>;
 513                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 514                 clocks = <&cru HCLK_OTG0>;
 515                 clock-names = "otg";
 516                 dr_mode = "otg";
 517                 g-np-tx-fifo-size = <16>;
 518                 g-rx-fifo-size = <275>;
 519                 g-tx-fifo-size = <256 128 128 64 64 32>;
 520                 g-use-dma;
 521                 phys = <&usbphy0>;
 522                 phy-names = "usb2-phy";
 523                 status = "disabled";
 524         };
 525
 526         usb_hsic: usb@ff5c0000 {
 527                 compatible = "generic-ehci";
 528                 reg = <0xff5c0000 0x100>;
 529                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 530                 clocks = <&cru HCLK_HSIC>;
 531                 clock-names = "usbhost";
 532                 status = "disabled";
 533         };
 534
 535         i2c0: i2c@ff650000 {
 536                 compatible = "rockchip,rk3288-i2c";
 537                 reg = <0xff650000 0x1000>;
 538                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 clock-names = "i2c";
 542                 clocks = <&cru PCLK_I2C0>;
 543                 pinctrl-names = "default";
 544                 pinctrl-0 = <&i2c0_xfer>;
 545                 status = "disabled";
 546         };
 547
 548         i2c2: i2c@ff660000 {
 549                 compatible = "rockchip,rk3288-i2c";
 550                 reg = <0xff660000 0x1000>;
 551                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 clock-names = "i2c";
 555                 clocks = <&cru PCLK_I2C2>;
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&i2c2_xfer>;
 558                 status = "disabled";
 559         };
 560
 561         pwm0: pwm@ff680000 {
 562                 compatible = "rockchip,rk3288-pwm";
 563                 reg = <0xff680000 0x10>;
 564                 #pwm-cells = <3>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&pwm0_pin>;
 567                 clocks = <&cru PCLK_PWM>;
 568                 clock-names = "pwm";
 569                 status = "disabled";
 570         };
 571
 572         pwm1: pwm@ff680010 {
 573                 compatible = "rockchip,rk3288-pwm";
 574                 reg = <0xff680010 0x10>;
 575                 #pwm-cells = <3>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&pwm1_pin>;
 578                 clocks = <&cru PCLK_PWM>;
 579                 clock-names = "pwm";
 580                 status = "disabled";
 581         };
 582
 583         pwm2: pwm@ff680020 {
 584                 compatible = "rockchip,rk3288-pwm";
 585                 reg = <0xff680020 0x10>;
 586                 #pwm-cells = <3>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&pwm2_pin>;
 589                 clocks = <&cru PCLK_PWM>;
 590                 clock-names = "pwm";
 591                 status = "disabled";
 592         };
 593
 594         pwm3: pwm@ff680030 {
 595                 compatible = "rockchip,rk3288-pwm";
 596                 reg = <0xff680030 0x10>;
 597                 #pwm-cells = <2>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&pwm3_pin>;
 600                 clocks = <&cru PCLK_PWM>;
 601                 clock-names = "pwm";
 602                 status = "disabled";
 603         };
 604
 605         bus_intmem@ff700000 {
 606                 compatible = "mmio-sram";
 607                 reg = <0xff700000 0x18000>;
 608                 #address-cells = <1>;
 609                 #size-cells = <1>;
 610                 ranges = <0 0xff700000 0x18000>;
 611                 smp-sram@0 {
 612                         compatible = "rockchip,rk3066-smp-sram";
 613                         reg = <0x00 0x10>;
 614                 };
 615         };
 616
 617         sram@ff720000 {
 618                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 619                 reg = <0xff720000 0x1000>;
 620         };
 621
 622         pmu: power-management@ff730000 {
 623                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 624                 reg = <0xff730000 0x100>;
 625
 626                 power: power-controller {
 627                         compatible = "rockchip,rk3288-power-controller";
 628                         #power-domain-cells = <1>;
 629                         #address-cells = <1>;
 630                         #size-cells = <0>;
 631
 632                         /*
 633                          * Note: Although SCLK_* are the working clocks
 634                          * of device without including on the NOC, needed for
 635                          * synchronous reset.
 636                          *
 637                          * The clocks on the which NOC:
 638                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 639                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 640                          * ACLK_RGA is on ACLK_RGA_NIU.
 641                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 642                          *
 643                          * Which clock are device clocks:
 644                          *      clocks          devices
 645                          *      *_IEP           IEP:Image Enhancement Processor
 646                          *      *_ISP           ISP:Image Signal Processing
 647                          *      *_VIP           VIP:Video Input Processor
 648                          *      *_VOP*          VOP:Visual Output Processor
 649                          *      *_RGA           RGA
 650                          *      *_EDP*          EDP
 651                          *      *_LVDS_*        LVDS
 652                          *      *_HDMI          HDMI
 653                          *      *_MIPI_*        MIPI
 654                          */
 655                         pd_vio {
 656                                 reg = <RK3288_PD_VIO>;
 657                                 clocks = <&cru ACLK_IEP>,
 658                                          <&cru ACLK_ISP>,
 659                                          <&cru ACLK_RGA>,
 660                                          <&cru ACLK_VIP>,
 661                                          <&cru ACLK_VOP0>,
 662                                          <&cru ACLK_VOP1>,
 663                                          <&cru DCLK_VOP0>,
 664                                          <&cru DCLK_VOP1>,
 665                                          <&cru HCLK_IEP>,
 666                                          <&cru HCLK_ISP>,
 667                                          <&cru HCLK_RGA>,
 668                                          <&cru HCLK_VIP>,
 669                                          <&cru HCLK_VOP0>,
 670                                          <&cru HCLK_VOP1>,
 671                                          <&cru PCLK_EDP_CTRL>,
 672                                          <&cru PCLK_HDMI_CTRL>,
 673                                          <&cru PCLK_LVDS_PHY>,
 674                                          <&cru PCLK_MIPI_CSI>,
 675                                          <&cru PCLK_MIPI_DSI0>,
 676                                          <&cru PCLK_MIPI_DSI1>,
 677                                          <&cru SCLK_EDP_24M>,
 678                                          <&cru SCLK_EDP>,
 679                                          <&cru SCLK_ISP_JPE>,
 680                                          <&cru SCLK_ISP>,
 681                                          <&cru SCLK_RGA>;
 682                         };
 683
 684                         /*
 685                          * Note: The following 3 are HEVC(H.265) clocks,
 686                          * and on the ACLK_HEVC_NIU (NOC).
 687                          */
 688                         pd_hevc {
 689                                 reg = <RK3288_PD_HEVC>;
 690                                 clocks = <&cru ACLK_HEVC>,
 691                                          <&cru SCLK_HEVC_CABAC>,
 692                                          <&cru SCLK_HEVC_CORE>;
 693                         };
 694
 695                         /*
 696                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 697                          * (video endecoder & decoder) clocks that on the
 698                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 699                          */
 700                         pd_video {
 701                                 reg = <RK3288_PD_VIDEO>;
 702                                 clocks = <&cru ACLK_VCODEC>,
 703                                          <&cru HCLK_VCODEC>;
 704                         };
 705
 706                         /*
 707                          * Note: ACLK_GPU is the GPU clock,
 708                          * and on the ACLK_GPU_NIU (NOC).
 709                          */
 710                         pd_gpu {
 711                                 reg = <RK3288_PD_GPU>;
 712                                 clocks = <&cru ACLK_GPU>;
 713                         };
 714                 };
 715         };
 716
 717         sgrf: syscon@ff740000 {
 718                 compatible = "rockchip,rk3288-sgrf", "syscon";
 719                 reg = <0xff740000 0x1000>;
 720         };
 721
 722         cru: clock-controller@ff760000 {
 723                 compatible = "rockchip,rk3288-cru";
 724                 reg = <0xff760000 0x1000>;
 725                 rockchip,grf = <&grf>;
 726                 #clock-cells = <1>;
 727                 #reset-cells = <1>;
 728                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 729                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 730                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 731                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 732                                   <&cru PCLK_PERI>;
 733                 assigned-clock-rates = <594000000>, <400000000>,
 734                                        <500000000>, <300000000>,
 735                                        <150000000>, <75000000>,
 736                                        <300000000>, <150000000>,
 737                                        <75000000>;
 738         };
 739
 740         grf: syscon@ff770000 {
 741                 compatible = "rockchip,rk3288-grf", "syscon";
 742                 reg = <0xff770000 0x1000>;
 743         };
 744
 745         wdt: watchdog@ff800000 {
 746                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 747                 reg = <0xff800000 0x100>;
 748                 clocks = <&cru PCLK_WDT>;
 749                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 750                 status = "disabled";
 751         };
 752
 753         spdif: sound@ff88b0000 {
 754                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 755                 reg = <0xff8b0000 0x10000>;
 756                 #sound-dai-cells = <0>;
 757                 clock-names = "hclk", "mclk";
 758                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 759                 dmas = <&dmac_bus_s 3>;
 760                 dma-names = "tx";
 761                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 762                 pinctrl-names = "default";
 763                 pinctrl-0 = <&spdif_tx>;
 764                 rockchip,grf = <&grf>;
 765                 status = "disabled";
 766         };
 767
 768         i2s: i2s@ff890000 {
 769                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 770                 reg = <0xff890000 0x10000>;
 771                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 772                 #address-cells = <1>;
 773                 #size-cells = <0>;
 774                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 775                 dma-names = "tx", "rx";
 776                 clock-names = "i2s_hclk", "i2s_clk";
 777                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 778                 pinctrl-names = "default";
 779                 pinctrl-0 = <&i2s0_bus>;
 780                 status = "disabled";
 781         };
 782
 783         vopb: vop@ff930000 {
 784                 compatible = "rockchip,rk3288-vop";
 785                 reg = <0xff930000 0x19c>;
 786                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 787                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 788                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 789                 power-domains = <&power RK3288_PD_VIO>;
 790                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 791                 reset-names = "axi", "ahb", "dclk";
 792                 iommus = <&vopb_mmu>;
 793                 status = "disabled";
 794
 795                 vopb_out: port {
 796                         #address-cells = <1>;
 797                         #size-cells = <0>;
 798
 799                         vopb_out_hdmi: endpoint@0 {
 800                                 reg = <0>;
 801                                 remote-endpoint = <&hdmi_in_vopb>;
 802                         };
 803                 };
 804         };
 805
 806         vopb_mmu: iommu@ff930300 {
 807                 compatible = "rockchip,iommu";
 808                 reg = <0xff930300 0x100>;
 809                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 810                 interrupt-names = "vopb_mmu";
 811                 power-domains = <&power RK3288_PD_VIO>;
 812                 #iommu-cells = <0>;
 813                 status = "disabled";
 814         };
 815
 816         vopl: vop@ff940000 {
 817                 compatible = "rockchip,rk3288-vop";
 818                 reg = <0xff940000 0x19c>;
 819                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 820                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 821                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 822                 power-domains = <&power RK3288_PD_VIO>;
 823                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 824                 reset-names = "axi", "ahb", "dclk";
 825                 iommus = <&vopl_mmu>;
 826                 status = "disabled";
 827
 828                 vopl_out: port {
 829                         #address-cells = <1>;
 830                         #size-cells = <0>;
 831
 832                         vopl_out_hdmi: endpoint@0 {
 833                                 reg = <0>;
 834                                 remote-endpoint = <&hdmi_in_vopl>;
 835                         };
 836                 };
 837         };
 838
 839         vopl_mmu: iommu@ff940300 {
 840                 compatible = "rockchip,iommu";
 841                 reg = <0xff940300 0x100>;
 842                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 843                 interrupt-names = "vopl_mmu";
 844                 power-domains = <&power RK3288_PD_VIO>;
 845                 #iommu-cells = <0>;
 846                 status = "disabled";
 847         };
 848
 849         hdmi: hdmi@ff980000 {
 850                 compatible = "rockchip,rk3288-dw-hdmi";
 851                 reg = <0xff980000 0x20000>;
 852                 reg-io-width = <4>;
 853                 rockchip,grf = <&grf>;
 854                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 855                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 856                 clock-names = "iahb", "isfr";
 857                 power-domains = <&power RK3288_PD_VIO>;
 858                 status = "disabled";
 859
 860                 ports {
 861                         hdmi_in: port {
 862                                 #address-cells = <1>;
 863                                 #size-cells = <0>;
 864                                 hdmi_in_vopb: endpoint@0 {
 865                                         reg = <0>;
 866                                         remote-endpoint = <&vopb_out_hdmi>;
 867                                 };
 868                                 hdmi_in_vopl: endpoint@1 {
 869                                         reg = <1>;
 870                                         remote-endpoint = <&vopl_out_hdmi>;
 871                                 };
 872                         };
 873                 };
 874         };
 875
 876         gic: interrupt-controller@ffc01000 {
 877                 compatible = "arm,gic-400";
 878                 interrupt-controller;
 879                 #interrupt-cells = <3>;
 880                 #address-cells = <0>;
 881
 882                 reg = <0xffc01000 0x1000>,
 883                       <0xffc02000 0x1000>,
 884                       <0xffc04000 0x2000>,
 885                       <0xffc06000 0x2000>;
 886                 interrupts = <GIC_PPI 9 0xf04>;
 887         };
 888
 889         usbphy: phy {
 890                 compatible = "rockchip,rk3288-usb-phy";
 891                 rockchip,grf = <&grf>;
 892                 #address-cells = <1>;
 893                 #size-cells = <0>;
 894                 status = "disabled";
 895
 896                 usbphy0: usb-phy0 {
 897                         #phy-cells = <0>;
 898                         reg = <0x320>;
 899                         clocks = <&cru SCLK_OTGPHY0>;
 900                         clock-names = "phyclk";
 901                 };
 902
 903                 usbphy1: usb-phy1 {
 904                         #phy-cells = <0>;
 905                         reg = <0x334>;
 906                         clocks = <&cru SCLK_OTGPHY1>;
 907                         clock-names = "phyclk";
 908                 };
 909
 910                 usbphy2: usb-phy2 {
 911                         #phy-cells = <0>;
 912                         reg = <0x348>;
 913                         clocks = <&cru SCLK_OTGPHY2>;
 914                         clock-names = "phyclk";
 915                 };
 916         };
 917
 918         pinctrl: pinctrl {
 919                 compatible = "rockchip,rk3288-pinctrl";
 920                 rockchip,grf = <&grf>;
 921                 rockchip,pmu = <&pmu>;
 922                 #address-cells = <1>;
 923                 #size-cells = <1>;
 924                 ranges;
 925
 926                 gpio0: gpio0@ff750000 {
 927                         compatible = "rockchip,gpio-bank";
 928                         reg =   <0xff750000 0x100>;
 929                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 930                         clocks = <&cru PCLK_GPIO0>;
 931
 932                         gpio-controller;
 933                         #gpio-cells = <2>;
 934
 935                         interrupt-controller;
 936                         #interrupt-cells = <2>;
 937                 };
 938
 939                 gpio1: gpio1@ff780000 {
 940                         compatible = "rockchip,gpio-bank";
 941                         reg = <0xff780000 0x100>;
 942                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 943                         clocks = <&cru PCLK_GPIO1>;
 944
 945                         gpio-controller;
 946                         #gpio-cells = <2>;
 947
 948                         interrupt-controller;
 949                         #interrupt-cells = <2>;
 950                 };
 951
 952                 gpio2: gpio2@ff790000 {
 953                         compatible = "rockchip,gpio-bank";
 954                         reg = <0xff790000 0x100>;
 955                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 956                         clocks = <&cru PCLK_GPIO2>;
 957
 958                         gpio-controller;
 959                         #gpio-cells = <2>;
 960
 961                         interrupt-controller;
 962                         #interrupt-cells = <2>;
 963                 };
 964
 965                 gpio3: gpio3@ff7a0000 {
 966                         compatible = "rockchip,gpio-bank";
 967                         reg = <0xff7a0000 0x100>;
 968                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 969                         clocks = <&cru PCLK_GPIO3>;
 970
 971                         gpio-controller;
 972                         #gpio-cells = <2>;
 973
 974                         interrupt-controller;
 975                         #interrupt-cells = <2>;
 976                 };
 977
 978                 gpio4: gpio4@ff7b0000 {
 979                         compatible = "rockchip,gpio-bank";
 980                         reg = <0xff7b0000 0x100>;
 981                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 982                         clocks = <&cru PCLK_GPIO4>;
 983
 984                         gpio-controller;
 985                         #gpio-cells = <2>;
 986
 987                         interrupt-controller;
 988                         #interrupt-cells = <2>;
 989                 };
 990
 991                 gpio5: gpio5@ff7c0000 {
 992                         compatible = "rockchip,gpio-bank";
 993                         reg = <0xff7c0000 0x100>;
 994                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 995                         clocks = <&cru PCLK_GPIO5>;
 996
 997                         gpio-controller;
 998                         #gpio-cells = <2>;
 999
1000                         interrupt-controller;
1001                         #interrupt-cells = <2>;
1002                 };
1003
1004                 gpio6: gpio6@ff7d0000 {
1005                         compatible = "rockchip,gpio-bank";
1006                         reg = <0xff7d0000 0x100>;
1007                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1008                         clocks = <&cru PCLK_GPIO6>;
1009
1010                         gpio-controller;
1011                         #gpio-cells = <2>;
1012
1013                         interrupt-controller;
1014                         #interrupt-cells = <2>;
1015                 };
1016
1017                 gpio7: gpio7@ff7e0000 {
1018                         compatible = "rockchip,gpio-bank";
1019                         reg = <0xff7e0000 0x100>;
1020                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1021                         clocks = <&cru PCLK_GPIO7>;
1022
1023                         gpio-controller;
1024                         #gpio-cells = <2>;
1025
1026                         interrupt-controller;
1027                         #interrupt-cells = <2>;
1028                 };
1029
1030                 gpio8: gpio8@ff7f0000 {
1031                         compatible = "rockchip,gpio-bank";
1032                         reg = <0xff7f0000 0x100>;
1033                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1034                         clocks = <&cru PCLK_GPIO8>;
1035
1036                         gpio-controller;
1037                         #gpio-cells = <2>;
1038
1039                         interrupt-controller;
1040                         #interrupt-cells = <2>;
1041                 };
1042
1043                 hdmi {
1044                         hdmi_ddc: hdmi-ddc {
1045                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1046                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1047                         };
1048                 };
1049
1050                 pcfg_pull_up: pcfg-pull-up {
1051                         bias-pull-up;
1052                 };
1053
1054                 pcfg_pull_down: pcfg-pull-down {
1055                         bias-pull-down;
1056                 };
1057
1058                 pcfg_pull_none: pcfg-pull-none {
1059                         bias-disable;
1060                 };
1061
1062                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1063                         bias-disable;
1064                         drive-strength = <12>;
1065                 };
1066
1067                 sleep {
1068                         global_pwroff: global-pwroff {
1069                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1070                         };
1071
1072                         ddrio_pwroff: ddrio-pwroff {
1073                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1074                         };
1075
1076                         ddr0_retention: ddr0-retention {
1077                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1078                         };
1079
1080                         ddr1_retention: ddr1-retention {
1081                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1082                         };
1083                 };
1084
1085                 i2c0 {
1086                         i2c0_xfer: i2c0-xfer {
1087                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1088                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1089                         };
1090                 };
1091
1092                 i2c1 {
1093                         i2c1_xfer: i2c1-xfer {
1094                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1095                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1096                         };
1097                 };
1098
1099                 i2c2 {
1100                         i2c2_xfer: i2c2-xfer {
1101                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1102                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1103                         };
1104                 };
1105
1106                 i2c3 {
1107                         i2c3_xfer: i2c3-xfer {
1108                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1109                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1110                         };
1111                 };
1112
1113                 i2c4 {
1114                         i2c4_xfer: i2c4-xfer {
1115                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1116                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1117                         };
1118                 };
1119
1120                 i2c5 {
1121                         i2c5_xfer: i2c5-xfer {
1122                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1123                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1124                         };
1125                 };
1126
1127                 i2s0 {
1128                         i2s0_bus: i2s0-bus {
1129                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1130                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1131                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1132                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1133                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1134                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1135                         };
1136                 };
1137
1138                 sdmmc {
1139                         sdmmc_clk: sdmmc-clk {
1140                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1141                         };
1142
1143                         sdmmc_cmd: sdmmc-cmd {
1144                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1145                         };
1146
1147                         sdmmc_cd: sdmcc-cd {
1148                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1149                         };
1150
1151                         sdmmc_bus1: sdmmc-bus1 {
1152                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1153                         };
1154
1155                         sdmmc_bus4: sdmmc-bus4 {
1156                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1157                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1158                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1159                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1160                         };
1161                 };
1162
1163                 sdio0 {
1164                         sdio0_bus1: sdio0-bus1 {
1165                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1166                         };
1167
1168                         sdio0_bus4: sdio0-bus4 {
1169                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1170                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1171                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1172                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1173                         };
1174
1175                         sdio0_cmd: sdio0-cmd {
1176                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1177                         };
1178
1179                         sdio0_clk: sdio0-clk {
1180                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1181                         };
1182
1183                         sdio0_cd: sdio0-cd {
1184                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1185                         };
1186
1187                         sdio0_wp: sdio0-wp {
1188                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1189                         };
1190
1191                         sdio0_pwr: sdio0-pwr {
1192                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1193                         };
1194
1195                         sdio0_bkpwr: sdio0-bkpwr {
1196                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1197                         };
1198
1199                         sdio0_int: sdio0-int {
1200                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1201                         };
1202                 };
1203
1204                 sdio1 {
1205                         sdio1_bus1: sdio1-bus1 {
1206                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1207                         };
1208
1209                         sdio1_bus4: sdio1-bus4 {
1210                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1211                                                 <3 25 4 &pcfg_pull_up>,
1212                                                 <3 26 4 &pcfg_pull_up>,
1213                                                 <3 27 4 &pcfg_pull_up>;
1214                         };
1215
1216                         sdio1_cd: sdio1-cd {
1217                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1218                         };
1219
1220                         sdio1_wp: sdio1-wp {
1221                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1222                         };
1223
1224                         sdio1_bkpwr: sdio1-bkpwr {
1225                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1226                         };
1227
1228                         sdio1_int: sdio1-int {
1229                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1230                         };
1231
1232                         sdio1_cmd: sdio1-cmd {
1233                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1234                         };
1235
1236                         sdio1_clk: sdio1-clk {
1237                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1238                         };
1239
1240                         sdio1_pwr: sdio1-pwr {
1241                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1242                         };
1243                 };
1244
1245                 emmc {
1246                         emmc_clk: emmc-clk {
1247                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1248                         };
1249
1250                         emmc_cmd: emmc-cmd {
1251                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1252                         };
1253
1254                         emmc_pwr: emmc-pwr {
1255                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1256                         };
1257
1258                         emmc_bus1: emmc-bus1 {
1259                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1260                         };
1261
1262                         emmc_bus4: emmc-bus4 {
1263                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1264                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1265                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1266                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1267                         };
1268
1269                         emmc_bus8: emmc-bus8 {
1270                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1271                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1272                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1273                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1274                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1275                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1276                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1277                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1278                         };
1279                 };
1280
1281                 spi0 {
1282                         spi0_clk: spi0-clk {
1283                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1284                         };
1285                         spi0_cs0: spi0-cs0 {
1286                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1287                         };
1288                         spi0_tx: spi0-tx {
1289                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1290                         };
1291                         spi0_rx: spi0-rx {
1292                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1293                         };
1294                         spi0_cs1: spi0-cs1 {
1295                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1296                         };
1297                 };
1298                 spi1 {
1299                         spi1_clk: spi1-clk {
1300                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1301                         };
1302                         spi1_cs0: spi1-cs0 {
1303                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1304                         };
1305                         spi1_rx: spi1-rx {
1306                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1307                         };
1308                         spi1_tx: spi1-tx {
1309                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1310                         };
1311                 };
1312
1313                 spi2 {
1314                         spi2_cs1: spi2-cs1 {
1315                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1316                         };
1317                         spi2_clk: spi2-clk {
1318                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1319                         };
1320                         spi2_cs0: spi2-cs0 {
1321                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1322                         };
1323                         spi2_rx: spi2-rx {
1324                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1325                         };
1326                         spi2_tx: spi2-tx {
1327                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1328                         };
1329                 };
1330
1331                 uart0 {
1332                         uart0_xfer: uart0-xfer {
1333                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1334                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1335                         };
1336
1337                         uart0_cts: uart0-cts {
1338                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1339                         };
1340
1341                         uart0_rts: uart0-rts {
1342                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1343                         };
1344                 };
1345
1346                 uart1 {
1347                         uart1_xfer: uart1-xfer {
1348                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1349                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1350                         };
1351
1352                         uart1_cts: uart1-cts {
1353                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1354                         };
1355
1356                         uart1_rts: uart1-rts {
1357                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1358                         };
1359                 };
1360
1361                 uart2 {
1362                         uart2_xfer: uart2-xfer {
1363                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1364                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1365                         };
1366                         /* no rts / cts for uart2 */
1367                 };
1368
1369                 uart3 {
1370                         uart3_xfer: uart3-xfer {
1371                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1372                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1373                         };
1374
1375                         uart3_cts: uart3-cts {
1376                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1377                         };
1378
1379                         uart3_rts: uart3-rts {
1380                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1381                         };
1382                 };
1383
1384                 uart4 {
1385                         uart4_xfer: uart4-xfer {
1386                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1387                                                 <5 13 3 &pcfg_pull_none>;
1388                         };
1389
1390                         uart4_cts: uart4-cts {
1391                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1392                         };
1393
1394                         uart4_rts: uart4-rts {
1395                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1396                         };
1397                 };
1398
1399                 tsadc {
1400                         otp_gpio: otp-gpio {
1401                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1402                         };
1403
1404                         otp_out: otp-out {
1405                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1406                         };
1407                 };
1408
1409                 pwm0 {
1410                         pwm0_pin: pwm0-pin {
1411                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1412                         };
1413                 };
1414
1415                 pwm1 {
1416                         pwm1_pin: pwm1-pin {
1417                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1418                         };
1419                 };
1420
1421                 pwm2 {
1422                         pwm2_pin: pwm2-pin {
1423                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1424                         };
1425                 };
1426
1427                 pwm3 {
1428                         pwm3_pin: pwm3-pin {
1429                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1430                         };
1431                 };
1432
1433                 gmac {
1434                         rgmii_pins: rgmii-pins {
1435                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1436                                                 <3 31 3 &pcfg_pull_none>,
1437                                                 <3 26 3 &pcfg_pull_none>,
1438                                                 <3 27 3 &pcfg_pull_none>,
1439                                                 <3 28 3 &pcfg_pull_none_12ma>,
1440                                                 <3 29 3 &pcfg_pull_none_12ma>,
1441                                                 <3 24 3 &pcfg_pull_none_12ma>,
1442                                                 <3 25 3 &pcfg_pull_none_12ma>,
1443                                                 <4 0 3 &pcfg_pull_none>,
1444                                                 <4 5 3 &pcfg_pull_none>,
1445                                                 <4 6 3 &pcfg_pull_none>,
1446                                                 <4 9 3 &pcfg_pull_none_12ma>,
1447                                                 <4 4 3 &pcfg_pull_none_12ma>,
1448                                                 <4 1 3 &pcfg_pull_none>,
1449                                                 <4 3 3 &pcfg_pull_none>;
1450                         };
1451
1452                         rmii_pins: rmii-pins {
1453                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1454                                                 <3 31 3 &pcfg_pull_none>,
1455                                                 <3 28 3 &pcfg_pull_none>,
1456                                                 <3 29 3 &pcfg_pull_none>,
1457                                                 <4 0 3 &pcfg_pull_none>,
1458                                                 <4 5 3 &pcfg_pull_none>,
1459                                                 <4 4 3 &pcfg_pull_none>,
1460                                                 <4 1 3 &pcfg_pull_none>,
1461                                                 <4 2 3 &pcfg_pull_none>,
1462                                                 <4 3 3 &pcfg_pull_none>;
1463                         };
1464                 };
1465
1466                 spdif {
1467                         spdif_tx: spdif-tx {
1468                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1469                         };
1470                 };
1471         };
1472 };