arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "arm,amba-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         peripherals-req-type-burst;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         peripherals-req-type-burst;
 162                         clocks = <&cru ACLK_DMAC1>;
 163                         clock-names = "apb_pclk";
 164                         status = "disabled";
 165                 };
 166
 167                 dmac_bus_s: dma-controller@ffb20000 {
 168                         compatible = "arm,pl330", "arm,primecell";
 169                         reg = <0xffb20000 0x4000>;
 170                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 172                         #dma-cells = <1>;
 173                         arm,pl330-broken-no-flushp;
 174                         peripherals-req-type-burst;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         timer {
 208                 compatible = "arm,armv7-timer";
 209                 arm,cpu-registers-not-fw-configured;
 210                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 212                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 213                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 214                 clock-frequency = <24000000>;
 215         };
 216
 217         timer: timer@ff810000 {
 218                 compatible = "rockchip,rk3288-timer";
 219                 reg = <0xff810000 0x20>;
 220                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 222                 clock-names = "timer", "pclk";
 223         };
 224
 225         display-subsystem {
 226                 compatible = "rockchip,display-subsystem";
 227                 ports = <&vopl_out>, <&vopb_out>;
 228         };
 229
 230         sdmmc: dwmmc@ff0c0000 {
 231                 compatible = "rockchip,rk3288-dw-mshc";
 232                 clock-freq-min-max = <400000 150000000>;
 233                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 234                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 236                 fifo-depth = <0x100>;
 237                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 238                 reg = <0xff0c0000 0x4000>;
 239                 status = "disabled";
 240         };
 241
 242         sdio0: dwmmc@ff0d0000 {
 243                 compatible = "rockchip,rk3288-dw-mshc";
 244                 clock-freq-min-max = <400000 150000000>;
 245                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 246                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 250                 reg = <0xff0d0000 0x4000>;
 251                 status = "disabled";
 252         };
 253
 254         sdio1: dwmmc@ff0e0000 {
 255                 compatible = "rockchip,rk3288-dw-mshc";
 256                 clock-freq-min-max = <400000 150000000>;
 257                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 258                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 259                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 260                 fifo-depth = <0x100>;
 261                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 262                 reg = <0xff0e0000 0x4000>;
 263                 status = "disabled";
 264         };
 265
 266         emmc: dwmmc@ff0f0000 {
 267                 compatible = "rockchip,rk3288-dw-mshc";
 268                 clock-freq-min-max = <400000 150000000>;
 269                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 270                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 271                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 272                 fifo-depth = <0x100>;
 273                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 274                 reg = <0xff0f0000 0x4000>;
 275                 status = "disabled";
 276                 supports-emmc;
 277         };
 278
 279         saradc: saradc@ff100000 {
 280                 compatible = "rockchip,saradc";
 281                 reg = <0xff100000 0x100>;
 282                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 283                 #io-channel-cells = <1>;
 284                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 285                 clock-names = "saradc", "apb_pclk";
 286                 resets = <&cru SRST_SARADC>;
 287                 reset-names = "saradc-apb";
 288                 status = "disabled";
 289         };
 290
 291         spi0: spi@ff110000 {
 292                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 293                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 294                 clock-names = "spiclk", "apb_pclk";
 295                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 296                 dma-names = "tx", "rx";
 297                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 300                 reg = <0xff110000 0x1000>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 status = "disabled";
 304         };
 305
 306         spi1: spi@ff120000 {
 307                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 308                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 309                 clock-names = "spiclk", "apb_pclk";
 310                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 311                 dma-names = "tx", "rx";
 312                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 315                 reg = <0xff120000 0x1000>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 status = "disabled";
 319         };
 320
 321         spi2: spi@ff130000 {
 322                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 323                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 324                 clock-names = "spiclk", "apb_pclk";
 325                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 326                 dma-names = "tx", "rx";
 327                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 328                 pinctrl-names = "default";
 329                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 330                 reg = <0xff130000 0x1000>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 status = "disabled";
 334         };
 335
 336         i2c1: i2c@ff140000 {
 337                 compatible = "rockchip,rk3288-i2c";
 338                 reg = <0xff140000 0x1000>;
 339                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clock-names = "i2c";
 343                 clocks = <&cru PCLK_I2C1>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&i2c1_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         i2c3: i2c@ff150000 {
 350                 compatible = "rockchip,rk3288-i2c";
 351                 reg = <0xff150000 0x1000>;
 352                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clock-names = "i2c";
 356                 clocks = <&cru PCLK_I2C3>;
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&i2c3_xfer>;
 359                 status = "disabled";
 360         };
 361
 362         i2c4: i2c@ff160000 {
 363                 compatible = "rockchip,rk3288-i2c";
 364                 reg = <0xff160000 0x1000>;
 365                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clock-names = "i2c";
 369                 clocks = <&cru PCLK_I2C4>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&i2c4_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         i2c5: i2c@ff170000 {
 376                 compatible = "rockchip,rk3288-i2c";
 377                 reg = <0xff170000 0x1000>;
 378                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clock-names = "i2c";
 382                 clocks = <&cru PCLK_I2C5>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&i2c5_xfer>;
 385                 status = "disabled";
 386         };
 387
 388         uart0: serial@ff180000 {
 389                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 390                 reg = <0xff180000 0x100>;
 391                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 392                 reg-shift = <2>;
 393                 reg-io-width = <4>;
 394                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 395                 clock-names = "baudclk", "apb_pclk";
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&uart0_xfer>;
 398                 status = "disabled";
 399         };
 400
 401         uart1: serial@ff190000 {
 402                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 403                 reg = <0xff190000 0x100>;
 404                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 408                 clock-names = "baudclk", "apb_pclk";
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&uart1_xfer>;
 411                 status = "disabled";
 412         };
 413
 414         uart2: serial@ff690000 {
 415                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 416                 reg = <0xff690000 0x100>;
 417                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 418                 reg-shift = <2>;
 419                 reg-io-width = <4>;
 420                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 421                 clock-names = "baudclk", "apb_pclk";
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&uart2_xfer>;
 424                 status = "disabled";
 425         };
 426
 427         uart3: serial@ff1b0000 {
 428                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 429                 reg = <0xff1b0000 0x100>;
 430                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 431                 reg-shift = <2>;
 432                 reg-io-width = <4>;
 433                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 434                 clock-names = "baudclk", "apb_pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&uart3_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         uart4: serial@ff1c0000 {
 441                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 442                 reg = <0xff1c0000 0x100>;
 443                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 444                 reg-shift = <2>;
 445                 reg-io-width = <4>;
 446                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 447                 clock-names = "baudclk", "apb_pclk";
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&uart4_xfer>;
 450                 status = "disabled";
 451         };
 452
 453         thermal-zones {
 454                 #include "rk3288-thermal.dtsi"
 455         };
 456
 457         tsadc: tsadc@ff280000 {
 458                 compatible = "rockchip,rk3288-tsadc";
 459                 reg = <0xff280000 0x100>;
 460                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 461                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 462                 clock-names = "tsadc", "apb_pclk";
 463                 resets = <&cru SRST_TSADC>;
 464                 reset-names = "tsadc-apb";
 465                 pinctrl-names = "init", "default", "sleep";
 466                 pinctrl-0 = <&otp_gpio>;
 467                 pinctrl-1 = <&otp_out>;
 468                 pinctrl-2 = <&otp_gpio>;
 469                 #thermal-sensor-cells = <1>;
 470                 rockchip,hw-tshut-temp = <95000>;
 471                 status = "disabled";
 472         };
 473
 474         gmac: ethernet@ff290000 {
 475                 compatible = "rockchip,rk3288-gmac";
 476                 reg = <0xff290000 0x10000>;
 477                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 478                 interrupt-names = "macirq";
 479                 rockchip,grf = <&grf>;
 480                 clocks = <&cru SCLK_MAC>,
 481                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 482                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 483                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 484                 clock-names = "stmmaceth",
 485                         "mac_clk_rx", "mac_clk_tx",
 486                         "clk_mac_ref", "clk_mac_refout",
 487                         "aclk_mac", "pclk_mac";
 488                 resets = <&cru SRST_MAC>;
 489                 reset-names = "stmmaceth";
 490                 max-speed = <100>;
 491                 status = "disabled";
 492         };
 493
 494         usb_host0_ehci: usb@ff500000 {
 495                 compatible = "generic-ehci";
 496                 reg = <0xff500000 0x100>;
 497                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&cru HCLK_USBHOST0>;
 499                 clock-names = "usbhost";
 500                 phys = <&usbphy1>;
 501                 phy-names = "usb";
 502                 status = "disabled";
 503         };
 504
 505         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 506
 507         usb_host1: usb@ff540000 {
 508                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 509                                 "snps,dwc2";
 510                 reg = <0xff540000 0x40000>;
 511                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&cru HCLK_USBHOST1>;
 513                 clock-names = "otg";
 514                 dr_mode = "host";
 515                 phys = <&usbphy2>;
 516                 phy-names = "usb2-phy";
 517                 status = "disabled";
 518         };
 519
 520         usb_otg: usb@ff580000 {
 521                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 522                                 "snps,dwc2";
 523                 reg = <0xff580000 0x40000>;
 524                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&cru HCLK_OTG0>;
 526                 clock-names = "otg";
 527                 dr_mode = "otg";
 528                 g-np-tx-fifo-size = <16>;
 529                 g-rx-fifo-size = <275>;
 530                 g-tx-fifo-size = <256 128 128 64 64 32>;
 531                 g-use-dma;
 532                 phys = <&usbphy0>;
 533                 phy-names = "usb2-phy";
 534                 status = "disabled";
 535         };
 536
 537         usb_hsic: usb@ff5c0000 {
 538                 compatible = "generic-ehci";
 539                 reg = <0xff5c0000 0x100>;
 540                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 541                 clocks = <&cru HCLK_HSIC>;
 542                 clock-names = "usbhost";
 543                 status = "disabled";
 544         };
 545
 546         i2c0: i2c@ff650000 {
 547                 compatible = "rockchip,rk3288-i2c";
 548                 reg = <0xff650000 0x1000>;
 549                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 clock-names = "i2c";
 553                 clocks = <&cru PCLK_I2C0>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&i2c0_xfer>;
 556                 status = "disabled";
 557         };
 558
 559         i2c2: i2c@ff660000 {
 560                 compatible = "rockchip,rk3288-i2c";
 561                 reg = <0xff660000 0x1000>;
 562                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 clock-names = "i2c";
 566                 clocks = <&cru PCLK_I2C2>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&i2c2_xfer>;
 569                 status = "disabled";
 570         };
 571
 572         pwm0: pwm@ff680000 {
 573                 compatible = "rockchip,rk3288-pwm";
 574                 reg = <0xff680000 0x10>;
 575                 #pwm-cells = <3>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&pwm0_pin>;
 578                 clocks = <&cru PCLK_PWM>;
 579                 clock-names = "pwm";
 580                 status = "disabled";
 581         };
 582
 583         pwm1: pwm@ff680010 {
 584                 compatible = "rockchip,rk3288-pwm";
 585                 reg = <0xff680010 0x10>;
 586                 #pwm-cells = <3>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&pwm1_pin>;
 589                 clocks = <&cru PCLK_PWM>;
 590                 clock-names = "pwm";
 591                 status = "disabled";
 592         };
 593
 594         pwm2: pwm@ff680020 {
 595                 compatible = "rockchip,rk3288-pwm";
 596                 reg = <0xff680020 0x10>;
 597                 #pwm-cells = <3>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&pwm2_pin>;
 600                 clocks = <&cru PCLK_PWM>;
 601                 clock-names = "pwm";
 602                 status = "disabled";
 603         };
 604
 605         pwm3: pwm@ff680030 {
 606                 compatible = "rockchip,rk3288-pwm";
 607                 reg = <0xff680030 0x10>;
 608                 #pwm-cells = <2>;
 609                 pinctrl-names = "default";
 610                 pinctrl-0 = <&pwm3_pin>;
 611                 clocks = <&cru PCLK_PWM>;
 612                 clock-names = "pwm";
 613                 status = "disabled";
 614         };
 615
 616         bus_intmem@ff700000 {
 617                 compatible = "mmio-sram";
 618                 reg = <0xff700000 0x18000>;
 619                 #address-cells = <1>;
 620                 #size-cells = <1>;
 621                 ranges = <0 0xff700000 0x18000>;
 622                 smp-sram@0 {
 623                         compatible = "rockchip,rk3066-smp-sram";
 624                         reg = <0x00 0x10>;
 625                 };
 626         };
 627
 628         sram@ff720000 {
 629                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 630                 reg = <0xff720000 0x1000>;
 631         };
 632
 633         qos_gpu_r: qos@ffaa0000 {
 634                 compatible = "syscon";
 635                 reg = <0xffaa0000 0x20>;
 636         };
 637
 638         qos_gpu_w: qos@ffaa0080 {
 639                 compatible = "syscon";
 640                 reg = <0xffaa0080 0x20>;
 641         };
 642
 643         qos_vio1_vop: qos@ffad0000 {
 644                 compatible = "syscon";
 645                 reg = <0xffad0000 0x20>;
 646         };
 647
 648         qos_vio1_isp_w0: qos@ffad0100 {
 649                 compatible = "syscon";
 650                 reg = <0xffad0100 0x20>;
 651         };
 652
 653         qos_vio1_isp_w1: qos@ffad0180 {
 654                 compatible = "syscon";
 655                 reg = <0xffad0180 0x20>;
 656         };
 657
 658         qos_vio0_vop: qos@ffad0400 {
 659                 compatible = "syscon";
 660                 reg = <0xffad0400 0x20>;
 661         };
 662
 663         qos_vio0_vip: qos@ffad0480 {
 664                 compatible = "syscon";
 665                 reg = <0xffad0480 0x20>;
 666         };
 667
 668         qos_vio0_iep: qos@ffad0500 {
 669                 compatible = "syscon";
 670                 reg = <0xffad0500 0x20>;
 671         };
 672
 673         qos_vio2_rga_r: qos@ffad0800 {
 674                 compatible = "syscon";
 675                 reg = <0xffad0800 0x20>;
 676         };
 677
 678         qos_vio2_rga_w: qos@ffad0880 {
 679                 compatible = "syscon";
 680                 reg = <0xffad0880 0x20>;
 681         };
 682
 683         qos_vio1_isp_r: qos@ffad0900 {
 684                 compatible = "syscon";
 685                 reg = <0xffad0900 0x20>;
 686         };
 687
 688         qos_video: qos@ffae0000 {
 689                 compatible = "syscon";
 690                 reg = <0xffae0000 0x20>;
 691         };
 692
 693         qos_hevc_r: qos@ffaf0000 {
 694                 compatible = "syscon";
 695                 reg = <0xffaf0000 0x20>;
 696         };
 697
 698         qos_hevc_w: qos@ffaf0080 {
 699                 compatible = "syscon";
 700                 reg = <0xffaf0080 0x20>;
 701         };
 702
 703         pmu: power-management@ff730000 {
 704                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 705                 reg = <0xff730000 0x100>;
 706
 707                 power: power-controller {
 708                         compatible = "rockchip,rk3288-power-controller";
 709                         #power-domain-cells = <1>;
 710                         #address-cells = <1>;
 711                         #size-cells = <0>;
 712
 713                         /*
 714                          * Note: Although SCLK_* are the working clocks
 715                          * of device without including on the NOC, needed for
 716                          * synchronous reset.
 717                          *
 718                          * The clocks on the which NOC:
 719                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 720                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 721                          * ACLK_RGA is on ACLK_RGA_NIU.
 722                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 723                          *
 724                          * Which clock are device clocks:
 725                          *      clocks          devices
 726                          *      *_IEP           IEP:Image Enhancement Processor
 727                          *      *_ISP           ISP:Image Signal Processing
 728                          *      *_VIP           VIP:Video Input Processor
 729                          *      *_VOP*          VOP:Visual Output Processor
 730                          *      *_RGA           RGA
 731                          *      *_EDP*          EDP
 732                          *      *_LVDS_*        LVDS
 733                          *      *_HDMI          HDMI
 734                          *      *_MIPI_*        MIPI
 735                          */
 736                         pd_vio {
 737                                 reg = <RK3288_PD_VIO>;
 738                                 clocks = <&cru ACLK_IEP>,
 739                                          <&cru ACLK_ISP>,
 740                                          <&cru ACLK_RGA>,
 741                                          <&cru ACLK_VIP>,
 742                                          <&cru ACLK_VOP0>,
 743                                          <&cru ACLK_VOP1>,
 744                                          <&cru DCLK_VOP0>,
 745                                          <&cru DCLK_VOP1>,
 746                                          <&cru HCLK_IEP>,
 747                                          <&cru HCLK_ISP>,
 748                                          <&cru HCLK_RGA>,
 749                                          <&cru HCLK_VIP>,
 750                                          <&cru HCLK_VOP0>,
 751                                          <&cru HCLK_VOP1>,
 752                                          <&cru PCLK_EDP_CTRL>,
 753                                          <&cru PCLK_HDMI_CTRL>,
 754                                          <&cru PCLK_LVDS_PHY>,
 755                                          <&cru PCLK_MIPI_CSI>,
 756                                          <&cru PCLK_MIPI_DSI0>,
 757                                          <&cru PCLK_MIPI_DSI1>,
 758                                          <&cru SCLK_EDP_24M>,
 759                                          <&cru SCLK_EDP>,
 760                                          <&cru SCLK_ISP_JPE>,
 761                                          <&cru SCLK_ISP>,
 762                                          <&cru SCLK_RGA>;
 763                                 pm_qos = <&qos_vio0_iep>,
 764                                          <&qos_vio1_vop>,
 765                                          <&qos_vio1_isp_w0>,
 766                                          <&qos_vio1_isp_w1>,
 767                                          <&qos_vio0_vop>,
 768                                          <&qos_vio0_vip>,
 769                                          <&qos_vio2_rga_r>,
 770                                          <&qos_vio2_rga_w>,
 771                                          <&qos_vio1_isp_r>;
 772                         };
 773
 774                         /*
 775                          * Note: The following 3 are HEVC(H.265) clocks,
 776                          * and on the ACLK_HEVC_NIU (NOC).
 777                          */
 778                         pd_hevc {
 779                                 reg = <RK3288_PD_HEVC>;
 780                                 clocks = <&cru ACLK_HEVC>,
 781                                          <&cru SCLK_HEVC_CABAC>,
 782                                          <&cru SCLK_HEVC_CORE>;
 783                                 pm_qos = <&qos_hevc_r>,
 784                                          <&qos_hevc_w>;
 785                         };
 786
 787                         /*
 788                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 789                          * (video endecoder & decoder) clocks that on the
 790                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 791                          */
 792                         pd_video {
 793                                 reg = <RK3288_PD_VIDEO>;
 794                                 clocks = <&cru ACLK_VCODEC>,
 795                                          <&cru HCLK_VCODEC>;
 796                                 pm_qos = <&qos_video>;
 797                         };
 798
 799                         /*
 800                          * Note: ACLK_GPU is the GPU clock,
 801                          * and on the ACLK_GPU_NIU (NOC).
 802                          */
 803                         pd_gpu {
 804                                 reg = <RK3288_PD_GPU>;
 805                                 clocks = <&cru ACLK_GPU>;
 806                                 pm_qos = <&qos_gpu_r>,
 807                                          <&qos_gpu_w>;
 808                         };
 809                 };
 810
 811                 reboot-mode {
 812                         compatible = "syscon-reboot-mode";
 813                         offset = <0x94>;
 814                         mode-normal = <BOOT_NORMAL>;
 815                         mode-recovery = <BOOT_RECOVERY>;
 816                         mode-bootloader = <BOOT_FASTBOOT>;
 817                         mode-loader = <BOOT_LOADER>;
 818                         mode-ums = <BOOT_UMS>;
 819                 };
 820         };
 821
 822         sgrf: syscon@ff740000 {
 823                 compatible = "rockchip,rk3288-sgrf", "syscon";
 824                 reg = <0xff740000 0x1000>;
 825         };
 826
 827         cru: clock-controller@ff760000 {
 828                 compatible = "rockchip,rk3288-cru";
 829                 reg = <0xff760000 0x1000>;
 830                 rockchip,grf = <&grf>;
 831                 #clock-cells = <1>;
 832                 #reset-cells = <1>;
 833                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 834                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 835                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 836                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 837                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 838                                   <&cru PCLK_PERI>;
 839                 assigned-clock-rates = <0>, <0>,
 840                                        <594000000>, <400000000>,
 841                                        <500000000>, <300000000>,
 842                                        <150000000>, <75000000>,
 843                                        <300000000>, <150000000>,
 844                                        <75000000>;
 845                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 846         };
 847
 848         grf: syscon@ff770000 {
 849                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 850                 reg = <0xff770000 0x1000>;
 851
 852                 edp_phy: edp-phy {
 853                         compatible = "rockchip,rk3288-dp-phy";
 854                         clocks = <&cru SCLK_EDP_24M>;
 855                         clock-names = "24m";
 856                         #phy-cells = <0>;
 857                         status = "disabled";
 858                 };
 859
 860                 io_domains: io-domains {
 861                         compatible = "rockchip,rk3288-io-voltage-domain";
 862                         status = "disabled";
 863                 };
 864
 865                 usbphy: phy {
 866                         compatible = "rockchip,rk3288-usb-phy";
 867                         #address-cells = <1>;
 868                         #size-cells = <0>;
 869                         status = "disabled";
 870
 871                         usbphy0: usb-phy0 {
 872                                 #phy-cells = <0>;
 873                                 reg = <0x320>;
 874                                 clocks = <&cru SCLK_OTGPHY0>;
 875                                 clock-names = "phyclk";
 876                                 resets = <&cru SRST_USBOTG_PHY>;
 877                                 reset-names = "phy-reset";
 878                         };
 879
 880                         usbphy1: usb-phy1 {
 881                                 #phy-cells = <0>;
 882                                 reg = <0x334>;
 883                                 clocks = <&cru SCLK_OTGPHY1>;
 884                                 clock-names = "phyclk";
 885                         };
 886
 887                         usbphy2: usb-phy2 {
 888                                 #phy-cells = <0>;
 889                                 reg = <0x348>;
 890                                 clocks = <&cru SCLK_OTGPHY2>;
 891                                 clock-names = "phyclk";
 892                                 resets = <&cru SRST_USBHOST1_PHY>;
 893                                 reset-names = "phy-reset";
 894                         };
 895                 };
 896         };
 897
 898         wdt: watchdog@ff800000 {
 899                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 900                 reg = <0xff800000 0x100>;
 901                 clocks = <&cru PCLK_WDT>;
 902                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 903                 status = "disabled";
 904         };
 905
 906         spdif: sound@ff88b0000 {
 907                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 908                 reg = <0xff8b0000 0x10000>;
 909                 #sound-dai-cells = <0>;
 910                 clock-names = "hclk", "mclk";
 911                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 912                 dmas = <&dmac_bus_s 3>;
 913                 dma-names = "tx";
 914                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 915                 pinctrl-names = "default";
 916                 pinctrl-0 = <&spdif_tx>;
 917                 rockchip,grf = <&grf>;
 918                 status = "disabled";
 919         };
 920
 921         i2s: i2s@ff890000 {
 922                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 923                 reg = <0xff890000 0x10000>;
 924                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 925                 #address-cells = <1>;
 926                 #size-cells = <0>;
 927                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 928                 dma-names = "tx", "rx";
 929                 clock-names = "i2s_hclk", "i2s_clk";
 930                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 931                 pinctrl-names = "default";
 932                 pinctrl-0 = <&i2s0_bus>;
 933                 status = "disabled";
 934         };
 935
 936         vopb: vop@ff930000 {
 937                 compatible = "rockchip,rk3288-vop";
 938                 reg = <0xff930000 0x19c>;
 939                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 940                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 941                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 942                 power-domains = <&power RK3288_PD_VIO>;
 943                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 944                 reset-names = "axi", "ahb", "dclk";
 945                 iommus = <&vopb_mmu>;
 946                 status = "disabled";
 947
 948                 vopb_out: port {
 949                         #address-cells = <1>;
 950                         #size-cells = <0>;
 951
 952                         vopb_out_hdmi: endpoint@0 {
 953                                 reg = <0>;
 954                                 remote-endpoint = <&hdmi_in_vopb>;
 955                         };
 956
 957                         vopb_out_edp: endpoint@1 {
 958                                 reg = <1>;
 959                                 remote-endpoint = <&edp_in_vopb>;
 960                         };
 961
 962                         vopb_out_mipi: endpoint@2 {
 963                                 reg = <2>;
 964                                 remote-endpoint = <&mipi_in_vopb>;
 965                         };
 966
 967                         vopb_out_lvds: endpoint@3 {
 968                                 reg = <3>;
 969                                 remote-endpoint = <&lvds_in_vopb>;
 970                         };
 971                 };
 972         };
 973
 974         vopb_mmu: iommu@ff930300 {
 975                 compatible = "rockchip,iommu";
 976                 reg = <0xff930300 0x100>;
 977                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 978                 interrupt-names = "vopb_mmu";
 979                 power-domains = <&power RK3288_PD_VIO>;
 980                 #iommu-cells = <0>;
 981                 status = "disabled";
 982         };
 983
 984         vopl: vop@ff940000 {
 985                 compatible = "rockchip,rk3288-vop";
 986                 reg = <0xff940000 0x19c>;
 987                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 988                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 989                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 990                 power-domains = <&power RK3288_PD_VIO>;
 991                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 992                 reset-names = "axi", "ahb", "dclk";
 993                 iommus = <&vopl_mmu>;
 994                 status = "disabled";
 995
 996                 vopl_out: port {
 997                         #address-cells = <1>;
 998                         #size-cells = <0>;
 999
1000                         vopl_out_hdmi: endpoint@0 {
1001                                 reg = <0>;
1002                                 remote-endpoint = <&hdmi_in_vopl>;
1003                         };
1004
1005                         vopl_out_edp: endpoint@1 {
1006                                 reg = <1>;
1007                                 remote-endpoint = <&edp_in_vopl>;
1008                         };
1009
1010                         vopl_out_mipi: endpoint@2 {
1011                                 reg = <2>;
1012                                 remote-endpoint = <&mipi_in_vopl>;
1013                         };
1014
1015                         vopl_out_lvds: endpoint@3 {
1016                                 reg = <3>;
1017                                 remote-endpoint = <&lvds_in_vopl>;
1018                         };
1019
1020                 };
1021         };
1022
1023         vopl_mmu: iommu@ff940300 {
1024                 compatible = "rockchip,iommu";
1025                 reg = <0xff940300 0x100>;
1026                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1027                 interrupt-names = "vopl_mmu";
1028                 power-domains = <&power RK3288_PD_VIO>;
1029                 #iommu-cells = <0>;
1030                 status = "disabled";
1031         };
1032
1033         mipi_dsi: mipi@ff960000 {
1034                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1035                 reg = <0xff960000 0x4000>;
1036                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1037                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1038                 clock-names = "ref", "pclk";
1039                 rockchip,grf = <&grf>;
1040                 #address-cells = <1>;
1041                 #size-cells = <0>;
1042                 status = "disabled";
1043
1044                 ports {
1045                         #address-cells = <1>;
1046                         #size-cells = <0>;
1047                         reg = <1>;
1048
1049                         mipi_in: port {
1050                                 #address-cells = <1>;
1051                                 #size-cells = <0>;
1052                                 mipi_in_vopb: endpoint@0 {
1053                                         reg = <0>;
1054                                         remote-endpoint = <&vopb_out_mipi>;
1055                                 };
1056                                 mipi_in_vopl: endpoint@1 {
1057                                         reg = <1>;
1058                                         remote-endpoint = <&vopl_out_mipi>;
1059                                 };
1060                         };
1061                 };
1062         };
1063
1064         edp: dp@ff970000 {
1065                 compatible = "rockchip,rk3288-dp";
1066                 reg = <0xff970000 0x4000>;
1067                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1068                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1069                 clock-names = "dp", "pclk";
1070                 phys = <&edp_phy>;
1071                 phy-names = "dp";
1072                 resets = <&cru SRST_EDP>;
1073                 reset-names = "dp";
1074                 rockchip,grf = <&grf>;
1075                 status = "disabled";
1076
1077                 ports {
1078                         #address-cells = <1>;
1079                         #size-cells = <0>;
1080                         edp_in: port@0 {
1081                                 reg = <0>;
1082                                 #address-cells = <1>;
1083                                 #size-cells = <0>;
1084                                 edp_in_vopb: endpoint@0 {
1085                                         reg = <0>;
1086                                         remote-endpoint = <&vopb_out_edp>;
1087                                 };
1088                                 edp_in_vopl: endpoint@1 {
1089                                         reg = <1>;
1090                                         remote-endpoint = <&vopl_out_edp>;
1091                                 };
1092                         };
1093                 };
1094         };
1095
1096         lvds: lvds@ff96c000 {
1097                 compatible = "rockchip,rk3288-lvds";
1098                 reg = <0xff96c000 0x4000>;
1099                 clocks = <&cru PCLK_LVDS_PHY>;
1100                 clock-names = "pclk_lvds";
1101                 pinctrl-names = "default";
1102                 pinctrl-0 = <&lcdc0_ctl>;
1103                 power-domains = <&power RK3288_PD_VIO>;
1104                 rockchip,grf = <&grf>;
1105                 status = "disabled";
1106
1107                 ports {
1108                         #address-cells = <1>;
1109                         #size-cells = <0>;
1110
1111                         lvds_in: port@0 {
1112                                 reg = <0>;
1113
1114                                 #address-cells = <1>;
1115                                 #size-cells = <0>;
1116
1117                                 lvds_in_vopb: endpoint@0 {
1118                                         reg = <0>;
1119                                         remote-endpoint = <&vopb_out_lvds>;
1120                                 };
1121                                 lvds_in_vopl: endpoint@1 {
1122                                         reg = <1>;
1123                                         remote-endpoint = <&vopl_out_lvds>;
1124                                 };
1125                         };
1126                 };
1127         };
1128
1129         hdmi: hdmi@ff980000 {
1130                 compatible = "rockchip,rk3288-dw-hdmi";
1131                 reg = <0xff980000 0x20000>;
1132                 reg-io-width = <4>;
1133                 rockchip,grf = <&grf>;
1134                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1135                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1136                 clock-names = "iahb", "isfr";
1137                 power-domains = <&power RK3288_PD_VIO>;
1138                 status = "disabled";
1139
1140                 ports {
1141                         hdmi_in: port {
1142                                 #address-cells = <1>;
1143                                 #size-cells = <0>;
1144                                 hdmi_in_vopb: endpoint@0 {
1145                                         reg = <0>;
1146                                         remote-endpoint = <&vopb_out_hdmi>;
1147                                 };
1148                                 hdmi_in_vopl: endpoint@1 {
1149                                         reg = <1>;
1150                                         remote-endpoint = <&vopl_out_hdmi>;
1151                                 };
1152                         };
1153                 };
1154         };
1155
1156         gpu: gpu@ffa30000 {
1157                 compatible = "arm,malit764",
1158                              "arm,malit76x",
1159                              "arm,malit7xx",
1160                              "arm,mali-midgard";
1161                 reg = <0xffa30000 0x10000>;
1162                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1163                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1164                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1165                 interrupt-names = "JOB", "MMU", "GPU";
1166                 clocks = <&cru ACLK_GPU>;
1167                 clock-names = "clk_mali";
1168                 operating-points = <
1169                         /* KHz uV */
1170                         600000 1250000
1171                         /* 500000 1200000 - See crosbug.com/p/33857 */
1172                         400000 1100000
1173                         300000 1000000
1174                         200000 950000
1175                         100000 950000
1176                 >;
1177                 #cooling-cells = <2>; /* min followed by max */
1178                 power-domains = <&power RK3288_PD_GPU>;
1179                 status = "disabled";
1180         };
1181
1182         vpu: video-codec@ff9a0000 {
1183                 compatible = "rockchip,rk3288-vpu";
1184                 reg = <0xff9a0000 0x800>;
1185                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1186                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1187                 interrupt-names = "vepu", "vdpu";
1188                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1189                 clock-names = "aclk", "hclk";
1190                 power-domains = <&power RK3288_PD_VIDEO>;
1191                 iommus = <&vpu_mmu>;
1192                 assigned-clocks = <&cru ACLK_VCODEC>;
1193                 assigned-clock-rates = <400000000>;
1194                 status = "disabled";
1195         };
1196
1197         vpu_service: vpu-service@ff9a0000 {
1198                 compatible = "rockchip,vpu_service";
1199                 reg = <0xff9a0000 0x800>;
1200                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1201                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1202                 interrupt-names = "irq_enc", "irq_dec";
1203                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1204                 clock-names = "aclk_vcodec", "hclk_vcodec";
1205                 power-domains = <&power RK3288_PD_VIDEO>;
1206                 rockchip,grf = <&grf>;
1207                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1208                 reset-names = "video_a", "video_h";
1209                 iommus = <&vpu_mmu>;
1210                 iommu_enabled = <1>;
1211                 dev_mode = <0>;
1212                 status = "disabled";
1213         };
1214
1215         vpu_mmu: iommu@ff9a0800 {
1216                 compatible = "rockchip,iommu";
1217                 reg = <0xff9a0800 0x100>;
1218                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1219                 interrupt-names = "vpu_mmu";
1220                 power-domains = <&power RK3288_PD_VIDEO>;
1221                 #iommu-cells = <0>;
1222         };
1223
1224         hevc_service: hevc-service@ff9c0000 {
1225                 compatible = "rockchip,hevc_service";
1226                 reg = <0xff9c0000 0x400>;
1227                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1228                 interrupt-names = "irq_dec";
1229                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1230                         <&cru SCLK_HEVC_CORE>,
1231                         <&cru SCLK_HEVC_CABAC>;
1232                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1233                         "clk_cabac";
1234                 /*
1235                  * The 4K hevc would also work well with 500/125/300/300,
1236                  * no more err irq and reset request.
1237                  */
1238                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1239                                   <&cru SCLK_HEVC_CORE>,
1240                                   <&cru SCLK_HEVC_CABAC>;
1241                 assigned-clock-rates = <400000000>, <100000000>,
1242                                        <300000000>, <300000000>;
1243
1244                 resets = <&cru SRST_HEVC>;
1245                 reset-names = "video";
1246                 power-domains = <&power RK3288_PD_HEVC>;
1247                 rockchip,grf = <&grf>;
1248                 dev_mode = <1>;
1249                 iommus = <&hevc_mmu>;
1250                 iommu_enabled = <1>;
1251                 status = "disabled";
1252         };
1253
1254         hevc_mmu: iommu@ff9c0440 {
1255                 compatible = "rockchip,iommu";
1256                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1257                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1258                 interrupt-names = "hevc_mmu";
1259                 power-domains = <&power RK3288_PD_HEVC>;
1260                 #iommu-cells = <0>;
1261         };
1262
1263         gic: interrupt-controller@ffc01000 {
1264                 compatible = "arm,gic-400";
1265                 interrupt-controller;
1266                 #interrupt-cells = <3>;
1267                 #address-cells = <0>;
1268
1269                 reg = <0xffc01000 0x1000>,
1270                       <0xffc02000 0x1000>,
1271                       <0xffc04000 0x2000>,
1272                       <0xffc06000 0x2000>;
1273                 interrupts = <GIC_PPI 9 0xf04>;
1274         };
1275
1276         efuse: efuse@ffb40000 {
1277                 compatible = "rockchip,rockchip-efuse";
1278                 reg = <0xffb40000 0x20>;
1279                 #address-cells = <1>;
1280                 #size-cells = <1>;
1281                 clocks = <&cru PCLK_EFUSE256>;
1282                 clock-names = "pclk_efuse";
1283
1284                 cpu_leakage: cpu_leakage@17 {
1285                         reg = <0x17 0x1>;
1286                 };
1287         };
1288
1289         cif_isp0: cif_isp@ff910000 {
1290                 compatible = "rockchip,rk3288-cif-isp";
1291                 rockchip,grf = <&grf>;
1292                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1293                 reg-names = "register", "csihost-register";
1294                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1295                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1296                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1297                         <&cru SCLK_MIPIDSI_24M>;
1298                 clock-names = "aclk_isp", "hclk_isp",
1299                         "sclk_isp", "sclk_isp_jpe",
1300                         "pclk_mipi_csi", "pclk_isp_in",
1301                         "sclk_mipidsi_24m";
1302                 resets = <&cru SRST_ISP>;
1303                 reset-names = "rst_isp";
1304                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1305                 interrupt-names = "cif_isp10_irq";
1306                 status = "disabled";
1307         };
1308
1309         pinctrl: pinctrl {
1310                 compatible = "rockchip,rk3288-pinctrl";
1311                 rockchip,grf = <&grf>;
1312                 rockchip,pmu = <&pmu>;
1313                 #address-cells = <1>;
1314                 #size-cells = <1>;
1315                 ranges;
1316
1317                 gpio0: gpio0@ff750000 {
1318                         compatible = "rockchip,gpio-bank";
1319                         reg =   <0xff750000 0x100>;
1320                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1321                         clocks = <&cru PCLK_GPIO0>;
1322
1323                         gpio-controller;
1324                         #gpio-cells = <2>;
1325
1326                         interrupt-controller;
1327                         #interrupt-cells = <2>;
1328                 };
1329
1330                 gpio1: gpio1@ff780000 {
1331                         compatible = "rockchip,gpio-bank";
1332                         reg = <0xff780000 0x100>;
1333                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1334                         clocks = <&cru PCLK_GPIO1>;
1335
1336                         gpio-controller;
1337                         #gpio-cells = <2>;
1338
1339                         interrupt-controller;
1340                         #interrupt-cells = <2>;
1341                 };
1342
1343                 gpio2: gpio2@ff790000 {
1344                         compatible = "rockchip,gpio-bank";
1345                         reg = <0xff790000 0x100>;
1346                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1347                         clocks = <&cru PCLK_GPIO2>;
1348
1349                         gpio-controller;
1350                         #gpio-cells = <2>;
1351
1352                         interrupt-controller;
1353                         #interrupt-cells = <2>;
1354                 };
1355
1356                 gpio3: gpio3@ff7a0000 {
1357                         compatible = "rockchip,gpio-bank";
1358                         reg = <0xff7a0000 0x100>;
1359                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1360                         clocks = <&cru PCLK_GPIO3>;
1361
1362                         gpio-controller;
1363                         #gpio-cells = <2>;
1364
1365                         interrupt-controller;
1366                         #interrupt-cells = <2>;
1367                 };
1368
1369                 gpio4: gpio4@ff7b0000 {
1370                         compatible = "rockchip,gpio-bank";
1371                         reg = <0xff7b0000 0x100>;
1372                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1373                         clocks = <&cru PCLK_GPIO4>;
1374
1375                         gpio-controller;
1376                         #gpio-cells = <2>;
1377
1378                         interrupt-controller;
1379                         #interrupt-cells = <2>;
1380                 };
1381
1382                 gpio5: gpio5@ff7c0000 {
1383                         compatible = "rockchip,gpio-bank";
1384                         reg = <0xff7c0000 0x100>;
1385                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1386                         clocks = <&cru PCLK_GPIO5>;
1387
1388                         gpio-controller;
1389                         #gpio-cells = <2>;
1390
1391                         interrupt-controller;
1392                         #interrupt-cells = <2>;
1393                 };
1394
1395                 gpio6: gpio6@ff7d0000 {
1396                         compatible = "rockchip,gpio-bank";
1397                         reg = <0xff7d0000 0x100>;
1398                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1399                         clocks = <&cru PCLK_GPIO6>;
1400
1401                         gpio-controller;
1402                         #gpio-cells = <2>;
1403
1404                         interrupt-controller;
1405                         #interrupt-cells = <2>;
1406                 };
1407
1408                 gpio7: gpio7@ff7e0000 {
1409                         compatible = "rockchip,gpio-bank";
1410                         reg = <0xff7e0000 0x100>;
1411                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1412                         clocks = <&cru PCLK_GPIO7>;
1413
1414                         gpio-controller;
1415                         #gpio-cells = <2>;
1416
1417                         interrupt-controller;
1418                         #interrupt-cells = <2>;
1419                 };
1420
1421                 gpio8: gpio8@ff7f0000 {
1422                         compatible = "rockchip,gpio-bank";
1423                         reg = <0xff7f0000 0x100>;
1424                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1425                         clocks = <&cru PCLK_GPIO8>;
1426
1427                         gpio-controller;
1428                         #gpio-cells = <2>;
1429
1430                         interrupt-controller;
1431                         #interrupt-cells = <2>;
1432                 };
1433
1434                 hdmi {
1435                         hdmi_ddc: hdmi-ddc {
1436                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1437                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1438                         };
1439                 };
1440
1441                 pcfg_pull_up: pcfg-pull-up {
1442                         bias-pull-up;
1443                 };
1444
1445                 pcfg_pull_down: pcfg-pull-down {
1446                         bias-pull-down;
1447                 };
1448
1449                 pcfg_pull_none: pcfg-pull-none {
1450                         bias-disable;
1451                 };
1452
1453                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1454                         bias-disable;
1455                         drive-strength = <12>;
1456                 };
1457
1458                 sleep {
1459                         global_pwroff: global-pwroff {
1460                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1461                         };
1462
1463                         ddrio_pwroff: ddrio-pwroff {
1464                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1465                         };
1466
1467                         ddr0_retention: ddr0-retention {
1468                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1469                         };
1470
1471                         ddr1_retention: ddr1-retention {
1472                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1473                         };
1474                 };
1475
1476                 edp {
1477                         edp_hpd: edp-hpd {
1478                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1479                         };
1480                 };
1481
1482                 i2c0 {
1483                         i2c0_xfer: i2c0-xfer {
1484                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1485                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1486                         };
1487                 };
1488
1489                 i2c1 {
1490                         i2c1_xfer: i2c1-xfer {
1491                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1492                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1493                         };
1494                 };
1495
1496                 i2c2 {
1497                         i2c2_xfer: i2c2-xfer {
1498                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1499                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1500                         };
1501                 };
1502
1503                 i2c3 {
1504                         i2c3_xfer: i2c3-xfer {
1505                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1506                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1507                         };
1508                 };
1509
1510                 i2c4 {
1511                         i2c4_xfer: i2c4-xfer {
1512                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1513                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1514                         };
1515                 };
1516
1517                 i2c5 {
1518                         i2c5_xfer: i2c5-xfer {
1519                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1520                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1521                         };
1522                 };
1523
1524                 i2s0 {
1525                         i2s0_bus: i2s0-bus {
1526                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1527                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1528                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1529                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1530                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1531                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1532                         };
1533                 };
1534
1535                 lcdc0 {
1536                         lcdc0_ctl: lcdc0-ctl {
1537                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1538                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1539                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1540                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1541                         };
1542                 };
1543
1544                 sdmmc {
1545                         sdmmc_clk: sdmmc-clk {
1546                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1547                         };
1548
1549                         sdmmc_cmd: sdmmc-cmd {
1550                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1551                         };
1552
1553                         sdmmc_cd: sdmcc-cd {
1554                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1555                         };
1556
1557                         sdmmc_bus1: sdmmc-bus1 {
1558                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1559                         };
1560
1561                         sdmmc_bus4: sdmmc-bus4 {
1562                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1563                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1564                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1565                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1566                         };
1567                 };
1568
1569                 sdio0 {
1570                         sdio0_bus1: sdio0-bus1 {
1571                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1572                         };
1573
1574                         sdio0_bus4: sdio0-bus4 {
1575                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1576                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1577                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1578                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1579                         };
1580
1581                         sdio0_cmd: sdio0-cmd {
1582                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1583                         };
1584
1585                         sdio0_clk: sdio0-clk {
1586                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1587                         };
1588
1589                         sdio0_cd: sdio0-cd {
1590                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1591                         };
1592
1593                         sdio0_wp: sdio0-wp {
1594                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1595                         };
1596
1597                         sdio0_pwr: sdio0-pwr {
1598                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1599                         };
1600
1601                         sdio0_bkpwr: sdio0-bkpwr {
1602                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1603                         };
1604
1605                         sdio0_int: sdio0-int {
1606                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1607                         };
1608                 };
1609
1610                 sdio1 {
1611                         sdio1_bus1: sdio1-bus1 {
1612                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1613                         };
1614
1615                         sdio1_bus4: sdio1-bus4 {
1616                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1617                                                 <3 25 4 &pcfg_pull_up>,
1618                                                 <3 26 4 &pcfg_pull_up>,
1619                                                 <3 27 4 &pcfg_pull_up>;
1620                         };
1621
1622                         sdio1_cd: sdio1-cd {
1623                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1624                         };
1625
1626                         sdio1_wp: sdio1-wp {
1627                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1628                         };
1629
1630                         sdio1_bkpwr: sdio1-bkpwr {
1631                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1632                         };
1633
1634                         sdio1_int: sdio1-int {
1635                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1636                         };
1637
1638                         sdio1_cmd: sdio1-cmd {
1639                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1640                         };
1641
1642                         sdio1_clk: sdio1-clk {
1643                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1644                         };
1645
1646                         sdio1_pwr: sdio1-pwr {
1647                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1648                         };
1649                 };
1650
1651                 emmc {
1652                         emmc_clk: emmc-clk {
1653                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1654                         };
1655
1656                         emmc_cmd: emmc-cmd {
1657                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1658                         };
1659
1660                         emmc_pwr: emmc-pwr {
1661                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1662                         };
1663
1664                         emmc_bus1: emmc-bus1 {
1665                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1666                         };
1667
1668                         emmc_bus4: emmc-bus4 {
1669                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1670                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1671                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1672                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1673                         };
1674
1675                         emmc_bus8: emmc-bus8 {
1676                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1677                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1678                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1679                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1680                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1681                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1682                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1683                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1684                         };
1685                 };
1686
1687                 spi0 {
1688                         spi0_clk: spi0-clk {
1689                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1690                         };
1691                         spi0_cs0: spi0-cs0 {
1692                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1693                         };
1694                         spi0_tx: spi0-tx {
1695                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1696                         };
1697                         spi0_rx: spi0-rx {
1698                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1699                         };
1700                         spi0_cs1: spi0-cs1 {
1701                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1702                         };
1703                 };
1704                 spi1 {
1705                         spi1_clk: spi1-clk {
1706                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1707                         };
1708                         spi1_cs0: spi1-cs0 {
1709                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1710                         };
1711                         spi1_rx: spi1-rx {
1712                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1713                         };
1714                         spi1_tx: spi1-tx {
1715                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1716                         };
1717                 };
1718
1719                 spi2 {
1720                         spi2_cs1: spi2-cs1 {
1721                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1722                         };
1723                         spi2_clk: spi2-clk {
1724                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1725                         };
1726                         spi2_cs0: spi2-cs0 {
1727                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1728                         };
1729                         spi2_rx: spi2-rx {
1730                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1731                         };
1732                         spi2_tx: spi2-tx {
1733                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1734                         };
1735                 };
1736
1737                 uart0 {
1738                         uart0_xfer: uart0-xfer {
1739                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1740                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1741                         };
1742
1743                         uart0_cts: uart0-cts {
1744                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1745                         };
1746
1747                         uart0_rts: uart0-rts {
1748                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1749                         };
1750                 };
1751
1752                 uart1 {
1753                         uart1_xfer: uart1-xfer {
1754                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1755                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1756                         };
1757
1758                         uart1_cts: uart1-cts {
1759                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1760                         };
1761
1762                         uart1_rts: uart1-rts {
1763                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1764                         };
1765                 };
1766
1767                 uart2 {
1768                         uart2_xfer: uart2-xfer {
1769                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1770                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1771                         };
1772                         /* no rts / cts for uart2 */
1773                 };
1774
1775                 uart3 {
1776                         uart3_xfer: uart3-xfer {
1777                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1778                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1779                         };
1780
1781                         uart3_cts: uart3-cts {
1782                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1783                         };
1784
1785                         uart3_rts: uart3-rts {
1786                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1787                         };
1788                 };
1789
1790                 uart4 {
1791                         uart4_xfer: uart4-xfer {
1792                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1793                                                 <5 13 3 &pcfg_pull_none>;
1794                         };
1795
1796                         uart4_cts: uart4-cts {
1797                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1798                         };
1799
1800                         uart4_rts: uart4-rts {
1801                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1802                         };
1803                 };
1804
1805                 tsadc {
1806                         otp_gpio: otp-gpio {
1807                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1808                         };
1809
1810                         otp_out: otp-out {
1811                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1812                         };
1813                 };
1814
1815                 pwm0 {
1816                         pwm0_pin: pwm0-pin {
1817                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1818                         };
1819                 };
1820
1821                 pwm1 {
1822                         pwm1_pin: pwm1-pin {
1823                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1824                         };
1825                 };
1826
1827                 pwm2 {
1828                         pwm2_pin: pwm2-pin {
1829                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1830                         };
1831                 };
1832
1833                 pwm3 {
1834                         pwm3_pin: pwm3-pin {
1835                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1836                         };
1837                 };
1838
1839                 gmac {
1840                         rgmii_pins: rgmii-pins {
1841                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1842                                                 <3 31 3 &pcfg_pull_none>,
1843                                                 <3 26 3 &pcfg_pull_none>,
1844                                                 <3 27 3 &pcfg_pull_none>,
1845                                                 <3 28 3 &pcfg_pull_none_12ma>,
1846                                                 <3 29 3 &pcfg_pull_none_12ma>,
1847                                                 <3 24 3 &pcfg_pull_none_12ma>,
1848                                                 <3 25 3 &pcfg_pull_none_12ma>,
1849                                                 <4 0 3 &pcfg_pull_none>,
1850                                                 <4 5 3 &pcfg_pull_none>,
1851                                                 <4 6 3 &pcfg_pull_none>,
1852                                                 <4 9 3 &pcfg_pull_none_12ma>,
1853                                                 <4 4 3 &pcfg_pull_none_12ma>,
1854                                                 <4 1 3 &pcfg_pull_none>,
1855                                                 <4 3 3 &pcfg_pull_none>;
1856                         };
1857
1858                         rmii_pins: rmii-pins {
1859                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1860                                                 <3 31 3 &pcfg_pull_none>,
1861                                                 <3 28 3 &pcfg_pull_none>,
1862                                                 <3 29 3 &pcfg_pull_none>,
1863                                                 <4 0 3 &pcfg_pull_none>,
1864                                                 <4 5 3 &pcfg_pull_none>,
1865                                                 <4 4 3 &pcfg_pull_none>,
1866                                                 <4 1 3 &pcfg_pull_none>,
1867                                                 <4 2 3 &pcfg_pull_none>,
1868                                                 <4 3 3 &pcfg_pull_none>;
1869                         };
1870                 };
1871
1872                 spdif {
1873                         spdif_tx: spdif-tx {
1874                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1875                         };
1876                 };
1877
1878                 cif {
1879                         cif_dvp_d2d9: cif-dvp-d2d9 {
1880                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
1881                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1882                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1883                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1884                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1885                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1886                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1887                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1888                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1889                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1890                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
1891                         };
1892                 };
1893         };
1894 };