arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/display/drm_mipi_dsi.h>
  50 #include "skeleton.dtsi"
  51
  52 / {
  53         compatible = "rockchip,rk3288";
  54
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 mshc0 = &emmc;
  66                 mshc1 = &sdmmc;
  67                 mshc2 = &sdio0;
  68                 mshc3 = &sdio1;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         arm-pmu {
  80                 compatible = "arm,cortex-a12-pmu";
  81                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  85                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  86         };
  87
  88         cpus {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 enable-method = "rockchip,rk3066-smp";
  92                 rockchip,pmu = <&pmu>;
  93
  94                 cpu0: cpu@500 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a12";
  97                         reg = <0x500>;
  98                         resets = <&cru SRST_CORE0>;
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         clocks = <&cru ARMCLK>;
 102                 };
 103                 cpu1: cpu@501 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a12";
 106                         reg = <0x501>;
 107                         resets = <&cru SRST_CORE1>;
 108                         operating-points-v2 = <&cpu0_opp_table>;
 109                 };
 110                 cpu2: cpu@502 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a12";
 113                         reg = <0x502>;
 114                         resets = <&cru SRST_CORE2>;
 115                         operating-points-v2 = <&cpu0_opp_table>;
 116                 };
 117                 cpu3: cpu@503 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a12";
 120                         reg = <0x503>;
 121                         resets = <&cru SRST_CORE3>;
 122                         operating-points-v2 = <&cpu0_opp_table>;
 123                 };
 124         };
 125
 126         cpu0_opp_table: opp_table0 {
 127                 compatible = "operating-points-v2";
 128                 opp-shared;
 129
 130                 opp@126000000 {
 131                         opp-hz = /bits/ 64 <126000000>;
 132                         opp-microvolt = <900000>;
 133                         clock-latency-ns = <40000>;
 134                 };
 135                 opp@216000000 {
 136                         opp-hz = /bits/ 64 <216000000>;
 137                         opp-microvolt = <900000>;
 138                         clock-latency-ns = <40000>;
 139                 };
 140                 opp@408000000 {
 141                         opp-hz = /bits/ 64 <408000000>;
 142                         opp-microvolt = <900000>;
 143                         clock-latency-ns = <40000>;
 144                 };
 145                 opp@600000000 {
 146                         opp-hz = /bits/ 64 <600000000>;
 147                         opp-microvolt = <900000>;
 148                         clock-latency-ns = <40000>;
 149                 };
 150                 opp@696000000 {
 151                         opp-hz = /bits/ 64 <696000000>;
 152                         opp-microvolt = <950000>;
 153                         clock-latency-ns = <40000>;
 154                 };
 155                 opp@816000000 {
 156                         opp-hz = /bits/ 64 <816000000>;
 157                         opp-microvolt = <1000000>;
 158                         clock-latency-ns = <40000>;
 159                         opp-suspend;
 160                 };
 161                 opp@1008000000 {
 162                         opp-hz = /bits/ 64 <1008000000>;
 163                         opp-microvolt = <1050000>;
 164                         clock-latency-ns = <40000>;
 165                 };
 166                 opp@1200000000 {
 167                         opp-hz = /bits/ 64 <1200000000>;
 168                         opp-microvolt = <1100000>;
 169                         clock-latency-ns = <40000>;
 170                 };
 171                 opp@1416000000 {
 172                         opp-hz = /bits/ 64 <1416000000>;
 173                         opp-microvolt = <1200000>;
 174                         clock-latency-ns = <40000>;
 175                 };
 176                 opp@1512000000 {
 177                         opp-hz = /bits/ 64 <1512000000>;
 178                         opp-microvolt = <1300000>;
 179                         clock-latency-ns = <40000>;
 180                 };
 181                 opp@1608000000 {
 182                         opp-hz = /bits/ 64 <1608000000>;
 183                         opp-microvolt = <1350000>;
 184                         clock-latency-ns = <40000>;
 185                 };
 186         };
 187
 188         cpu_avs: cpu-avs {
 189                 cluster0-avs {
 190                         cluster-id = <0>;
 191                         min-volt = <900000>; /* uV */
 192                         min-freq = <126000>; /* KHz */
 193                         leakage-adjust-volt = <
 194                         /*  mA        mA         uV */
 195                             0         254        0
 196                         >;
 197                         nvmem-cells = <&cpu_leakage>;
 198                         nvmem-cell-names = "cpu_leakage";
 199                 };
 200         };
 201
 202         amba {
 203                 compatible = "arm,amba-bus";
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges;
 207
 208                 dmac_peri: dma-controller@ff250000 {
 209                         compatible = "arm,pl330", "arm,primecell";
 210                         reg = <0xff250000 0x4000>;
 211                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 213                         #dma-cells = <1>;
 214                         arm,pl330-broken-no-flushp;
 215                         peripherals-req-type-burst;
 216                         clocks = <&cru ACLK_DMAC2>;
 217                         clock-names = "apb_pclk";
 218                 };
 219
 220                 dmac_bus_ns: dma-controller@ff600000 {
 221                         compatible = "arm,pl330", "arm,primecell";
 222                         reg = <0xff600000 0x4000>;
 223                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 225                         #dma-cells = <1>;
 226                         arm,pl330-broken-no-flushp;
 227                         peripherals-req-type-burst;
 228                         clocks = <&cru ACLK_DMAC1>;
 229                         clock-names = "apb_pclk";
 230                         status = "disabled";
 231                 };
 232
 233                 dmac_bus_s: dma-controller@ffb20000 {
 234                         compatible = "arm,pl330", "arm,primecell";
 235                         reg = <0xffb20000 0x4000>;
 236                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 238                         #dma-cells = <1>;
 239                         arm,pl330-broken-no-flushp;
 240                         peripherals-req-type-burst;
 241                         clocks = <&cru ACLK_DMAC1>;
 242                         clock-names = "apb_pclk";
 243                 };
 244         };
 245
 246         reserved-memory {
 247                 #address-cells = <1>;
 248                 #size-cells = <1>;
 249                 ranges;
 250
 251                 /*
 252                  * The rk3288 cannot use the memory area above 0xfe000000
 253                  * for dma operations for some reason. While there is
 254                  * probably a better solution available somewhere, we
 255                  * haven't found it yet and while devices with 2GB of ram
 256                  * are not affected, this issue prevents 4GB from booting.
 257                  * So to make these devices at least bootable, block
 258                  * this area for the time being until the real solution
 259                  * is found.
 260                  */
 261                 dma-unusable@fe000000 {
 262                         reg = <0xfe000000 0x1000000>;
 263                 };
 264         };
 265
 266         xin24m: oscillator {
 267                 compatible = "fixed-clock";
 268                 clock-frequency = <24000000>;
 269                 clock-output-names = "xin24m";
 270                 #clock-cells = <0>;
 271         };
 272
 273         timer {
 274                 compatible = "arm,armv7-timer";
 275                 arm,cpu-registers-not-fw-configured;
 276                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 277                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 278                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 279                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 280                 clock-frequency = <24000000>;
 281         };
 282
 283         timer: timer@ff810000 {
 284                 compatible = "rockchip,rk3288-timer";
 285                 reg = <0xff810000 0x20>;
 286                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 287                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 288                 clock-names = "timer", "pclk";
 289         };
 290
 291         display-subsystem {
 292                 compatible = "rockchip,display-subsystem";
 293                 ports = <&vopl_out>, <&vopb_out>;
 294         };
 295
 296         sdmmc: dwmmc@ff0c0000 {
 297                 compatible = "rockchip,rk3288-dw-mshc";
 298                 clock-freq-min-max = <400000 150000000>;
 299                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 300                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 301                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 302                 fifo-depth = <0x100>;
 303                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 304                 reg = <0xff0c0000 0x4000>;
 305                 status = "disabled";
 306         };
 307
 308         sdio0: dwmmc@ff0d0000 {
 309                 compatible = "rockchip,rk3288-dw-mshc";
 310                 clock-freq-min-max = <400000 150000000>;
 311                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 312                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 313                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 314                 fifo-depth = <0x100>;
 315                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 316                 reg = <0xff0d0000 0x4000>;
 317                 status = "disabled";
 318         };
 319
 320         sdio1: dwmmc@ff0e0000 {
 321                 compatible = "rockchip,rk3288-dw-mshc";
 322                 clock-freq-min-max = <400000 150000000>;
 323                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 324                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 325                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 326                 fifo-depth = <0x100>;
 327                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 328                 reg = <0xff0e0000 0x4000>;
 329                 status = "disabled";
 330         };
 331
 332         emmc: dwmmc@ff0f0000 {
 333                 compatible = "rockchip,rk3288-dw-mshc";
 334                 clock-freq-min-max = <400000 150000000>;
 335                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 336                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 337                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 338                 fifo-depth = <0x100>;
 339                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 340                 reg = <0xff0f0000 0x4000>;
 341                 status = "disabled";
 342                 supports-emmc;
 343         };
 344
 345         saradc: saradc@ff100000 {
 346                 compatible = "rockchip,saradc";
 347                 reg = <0xff100000 0x100>;
 348                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 349                 #io-channel-cells = <1>;
 350                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 351                 clock-names = "saradc", "apb_pclk";
 352                 resets = <&cru SRST_SARADC>;
 353                 reset-names = "saradc-apb";
 354                 status = "disabled";
 355         };
 356
 357         spi0: spi@ff110000 {
 358                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 359                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 360                 clock-names = "spiclk", "apb_pclk";
 361                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 362                 dma-names = "tx", "rx";
 363                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 366                 reg = <0xff110000 0x1000>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 status = "disabled";
 370         };
 371
 372         spi1: spi@ff120000 {
 373                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 374                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 377                 dma-names = "tx", "rx";
 378                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 381                 reg = <0xff120000 0x1000>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 status = "disabled";
 385         };
 386
 387         spi2: spi@ff130000 {
 388                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 389                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 390                 clock-names = "spiclk", "apb_pclk";
 391                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 392                 dma-names = "tx", "rx";
 393                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 396                 reg = <0xff130000 0x1000>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 status = "disabled";
 400         };
 401
 402         i2c0: i2c@ff650000 {
 403                 compatible = "rockchip,rk3288-i2c";
 404                 reg = <0xff650000 0x1000>;
 405                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C0>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c0_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         i2c1: i2c@ff140000 {
 416                 compatible = "rockchip,rk3288-i2c";
 417                 reg = <0xff140000 0x1000>;
 418                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 clock-names = "i2c";
 422                 clocks = <&cru PCLK_I2C1>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&i2c1_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         i2c3: i2c@ff150000 {
 429                 compatible = "rockchip,rk3288-i2c";
 430                 reg = <0xff150000 0x1000>;
 431                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 clock-names = "i2c";
 435                 clocks = <&cru PCLK_I2C3>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&i2c3_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         i2c4: i2c@ff160000 {
 442                 compatible = "rockchip,rk3288-i2c";
 443                 reg = <0xff160000 0x1000>;
 444                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clock-names = "i2c";
 448                 clocks = <&cru PCLK_I2C4>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&i2c4_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         i2c5: i2c@ff170000 {
 455                 compatible = "rockchip,rk3288-i2c";
 456                 reg = <0xff170000 0x1000>;
 457                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 458                 #address-cells = <1>;
 459                 #size-cells = <0>;
 460                 clock-names = "i2c";
 461                 clocks = <&cru PCLK_I2C5>;
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&i2c5_xfer>;
 464                 status = "disabled";
 465         };
 466
 467         uart0: serial@ff180000 {
 468                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 469                 reg = <0xff180000 0x100>;
 470                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 474                 clock-names = "baudclk", "apb_pclk";
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&uart0_xfer>;
 477                 status = "disabled";
 478         };
 479
 480         uart1: serial@ff190000 {
 481                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 482                 reg = <0xff190000 0x100>;
 483                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 484                 reg-shift = <2>;
 485                 reg-io-width = <4>;
 486                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 487                 clock-names = "baudclk", "apb_pclk";
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&uart1_xfer>;
 490                 status = "disabled";
 491         };
 492
 493         uart2: serial@ff690000 {
 494                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 495                 reg = <0xff690000 0x100>;
 496                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 497                 reg-shift = <2>;
 498                 reg-io-width = <4>;
 499                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 500                 clock-names = "baudclk", "apb_pclk";
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&uart2_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         uart3: serial@ff1b0000 {
 507                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 508                 reg = <0xff1b0000 0x100>;
 509                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 510                 reg-shift = <2>;
 511                 reg-io-width = <4>;
 512                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 513                 clock-names = "baudclk", "apb_pclk";
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&uart3_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         uart4: serial@ff1c0000 {
 520                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 521                 reg = <0xff1c0000 0x100>;
 522                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 523                 reg-shift = <2>;
 524                 reg-io-width = <4>;
 525                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 526                 clock-names = "baudclk", "apb_pclk";
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&uart4_xfer>;
 529                 status = "disabled";
 530         };
 531
 532         thermal-zones {
 533                 reserve_thermal: reserve_thermal {
 534                         polling-delay-passive = <1000>; /* milliseconds */
 535                         polling-delay = <5000>; /* milliseconds */
 536
 537                         thermal-sensors = <&tsadc 0>;
 538                 };
 539
 540                 cpu_thermal: cpu_thermal {
 541                         polling-delay-passive = <250>; /* milliseconds */
 542                         polling-delay = <5000>; /* milliseconds */
 543
 544                         thermal-sensors = <&tsadc 1>;
 545
 546                         trips {
 547                                 cpu_alert0: cpu_alert0 {
 548                                         temperature = <70000>; /* millicelsius */
 549                                         hysteresis = <2000>; /* millicelsius */
 550                                         type = "passive";
 551                                 };
 552                                 cpu_alert1: cpu_alert1 {
 553                                         temperature = <80000>; /* millicelsius */
 554                                         hysteresis = <2000>; /* millicelsius */
 555                                         type = "passive";
 556                                 };
 557                                 cpu_crit: cpu_crit {
 558                                         temperature = <90000>; /* millicelsius */
 559                                         hysteresis = <2000>; /* millicelsius */
 560                                         type = "critical";
 561                                 };
 562                         };
 563
 564                         cooling-maps {
 565                                 map0 {
 566                                         trip = <&cpu_alert0>;
 567                                         cooling-device =
 568                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 569                                 };
 570                                 map1 {
 571                                         trip = <&cpu_alert1>;
 572                                         cooling-device =
 573                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 574                                 };
 575                         };
 576                 };
 577
 578                 gpu_thermal: gpu_thermal {
 579                         polling-delay-passive = <250>; /* milliseconds */
 580                         polling-delay = <5000>; /* milliseconds */
 581
 582                         thermal-sensors = <&tsadc 2>;
 583
 584                         trips {
 585                                 gpu_alert0: gpu_alert0 {
 586                                         temperature = <80000>; /* millicelsius */
 587                                         hysteresis = <2000>; /* millicelsius */
 588                                         type = "passive";
 589                                 };
 590                                 gpu_crit: gpu_crit {
 591                                         temperature = <90000>; /* millicelsius */
 592                                         hysteresis = <2000>; /* millicelsius */
 593                                         type = "critical";
 594                                 };
 595                         };
 596
 597                         cooling-maps {
 598                                 map0 {
 599                                         trip = <&gpu_alert0>;
 600                                         cooling-device =
 601                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 602                                 };
 603                         };
 604                 };
 605         };
 606
 607         tsadc: tsadc@ff280000 {
 608                 compatible = "rockchip,rk3288-tsadc";
 609                 reg = <0xff280000 0x100>;
 610                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 611                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 612                 clock-names = "tsadc", "apb_pclk";
 613                 assigned-clocks = <&cru SCLK_TSADC>;
 614                 assigned-clock-rates = <10000>;
 615                 resets = <&cru SRST_TSADC>;
 616                 reset-names = "tsadc-apb";
 617                 pinctrl-names = "init", "default", "sleep";
 618                 pinctrl-0 = <&otp_gpio>;
 619                 pinctrl-1 = <&otp_out>;
 620                 pinctrl-2 = <&otp_gpio>;
 621                 #thermal-sensor-cells = <1>;
 622                 rockchip,hw-tshut-temp = <95000>;
 623                 status = "disabled";
 624         };
 625
 626         gmac: ethernet@ff290000 {
 627                 compatible = "rockchip,rk3288-gmac";
 628                 reg = <0xff290000 0x10000>;
 629                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 630                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 631                 interrupt-names = "macirq", "eth_wake_irq";
 632                 rockchip,grf = <&grf>;
 633                 clocks = <&cru SCLK_MAC>,
 634                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 635                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 636                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 637                 clock-names = "stmmaceth",
 638                         "mac_clk_rx", "mac_clk_tx",
 639                         "clk_mac_ref", "clk_mac_refout",
 640                         "aclk_mac", "pclk_mac";
 641                 resets = <&cru SRST_MAC>;
 642                 reset-names = "stmmaceth";
 643                 status = "disabled";
 644         };
 645
 646         usb_host0_ehci: usb@ff500000 {
 647                 compatible = "generic-ehci";
 648                 reg = <0xff500000 0x100>;
 649                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 650                 clocks = <&cru HCLK_USBHOST0>;
 651                 clock-names = "usbhost";
 652                 phys = <&usbphy1>;
 653                 phy-names = "usb";
 654                 status = "disabled";
 655         };
 656
 657         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 658
 659         usb_host1: usb@ff540000 {
 660                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 661                                 "snps,dwc2";
 662                 reg = <0xff540000 0x40000>;
 663                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 664                 clocks = <&cru HCLK_USBHOST1>;
 665                 clock-names = "otg";
 666                 dr_mode = "host";
 667                 phys = <&usbphy2>;
 668                 phy-names = "usb2-phy";
 669                 status = "disabled";
 670         };
 671
 672         usb_otg: usb@ff580000 {
 673                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 674                                 "snps,dwc2";
 675                 reg = <0xff580000 0x40000>;
 676                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 677                 clocks = <&cru HCLK_OTG0>;
 678                 clock-names = "otg";
 679                 dr_mode = "otg";
 680                 g-np-tx-fifo-size = <16>;
 681                 g-rx-fifo-size = <275>;
 682                 g-tx-fifo-size = <256 128 128 64 64 32>;
 683                 g-use-dma;
 684                 phys = <&usbphy0>;
 685                 phy-names = "usb2-phy";
 686                 status = "disabled";
 687         };
 688
 689         usb_hsic: usb@ff5c0000 {
 690                 compatible = "generic-ehci";
 691                 reg = <0xff5c0000 0x100>;
 692                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 693                 clocks = <&cru HCLK_HSIC>;
 694                 clock-names = "usbhost";
 695                 status = "disabled";
 696         };
 697
 698         dmc: dmc@ff610000 {
 699                 compatible = "rockchip,rk3288-dmc", "syscon";
 700                 rockchip,cru = <&cru>;
 701                 rockchip,grf = <&grf>;
 702                 rockchip,pmu = <&pmu>;
 703                 rockchip,sgrf = <&sgrf>;
 704                 rockchip,noc = <&noc>;
 705                 reg = <0xff610000 0x3fc
 706                        0xff620000 0x294
 707                        0xff630000 0x3fc
 708                        0xff640000 0x294>;
 709                 rockchip,sram = <&ddr_sram>;
 710                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 711                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 712                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 713                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 714                               "pclk_ddrupctl1", "pclk_publ1",
 715                               "arm_clk", "aclk_dmac1";
 716         };
 717
 718         i2c2: i2c@ff660000 {
 719                 compatible = "rockchip,rk3288-i2c";
 720                 reg = <0xff660000 0x1000>;
 721                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 722                 #address-cells = <1>;
 723                 #size-cells = <0>;
 724                 clock-names = "i2c";
 725                 clocks = <&cru PCLK_I2C2>;
 726                 pinctrl-names = "default";
 727                 pinctrl-0 = <&i2c2_xfer>;
 728                 status = "disabled";
 729         };
 730
 731         pwm0: pwm@ff680000 {
 732                 compatible = "rockchip,rk3288-pwm";
 733                 reg = <0xff680000 0x10>;
 734                 #pwm-cells = <3>;
 735                 pinctrl-names = "default";
 736                 pinctrl-0 = <&pwm0_pin>;
 737                 clocks = <&cru PCLK_PWM>;
 738                 clock-names = "pwm";
 739                 status = "disabled";
 740         };
 741
 742         pwm1: pwm@ff680010 {
 743                 compatible = "rockchip,rk3288-pwm";
 744                 reg = <0xff680010 0x10>;
 745                 #pwm-cells = <3>;
 746                 pinctrl-names = "default";
 747                 pinctrl-0 = <&pwm1_pin>;
 748                 clocks = <&cru PCLK_PWM>;
 749                 clock-names = "pwm";
 750                 status = "disabled";
 751         };
 752
 753         pwm2: pwm@ff680020 {
 754                 compatible = "rockchip,rk3288-pwm";
 755                 reg = <0xff680020 0x10>;
 756                 #pwm-cells = <3>;
 757                 pinctrl-names = "default";
 758                 pinctrl-0 = <&pwm2_pin>;
 759                 clocks = <&cru PCLK_PWM>;
 760                 clock-names = "pwm";
 761                 status = "disabled";
 762         };
 763
 764         pwm3: pwm@ff680030 {
 765                 compatible = "rockchip,rk3288-pwm";
 766                 reg = <0xff680030 0x10>;
 767                 #pwm-cells = <2>;
 768                 pinctrl-names = "default";
 769                 pinctrl-0 = <&pwm3_pin>;
 770                 clocks = <&cru PCLK_PWM>;
 771                 clock-names = "pwm";
 772                 status = "disabled";
 773         };
 774
 775         bus_intmem@ff700000 {
 776                 compatible = "mmio-sram";
 777                 reg = <0xff700000 0x18000>;
 778                 #address-cells = <1>;
 779                 #size-cells = <1>;
 780                 ranges = <0 0xff700000 0x18000>;
 781                 smp-sram@0 {
 782                         compatible = "rockchip,rk3066-smp-sram";
 783                         reg = <0x00 0x10>;
 784                 };
 785                 ddr_sram: ddr-sram@1000 {
 786                         compatible = "rockchip,rk3288-ddr-sram";
 787                         reg = <0x1000 0x4000>;
 788                 };
 789         };
 790
 791         sram@ff720000 {
 792                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 793                 reg = <0xff720000 0x1000>;
 794         };
 795
 796         qos_gpu_r: qos@ffaa0000 {
 797                 compatible = "syscon";
 798                 reg = <0xffaa0000 0x20>;
 799         };
 800
 801         qos_gpu_w: qos@ffaa0080 {
 802                 compatible = "syscon";
 803                 reg = <0xffaa0080 0x20>;
 804         };
 805
 806         qos_vio1_vop: qos@ffad0000 {
 807                 compatible = "syscon";
 808                 reg = <0xffad0000 0x20>;
 809         };
 810
 811         qos_vio1_isp_w0: qos@ffad0100 {
 812                 compatible = "syscon";
 813                 reg = <0xffad0100 0x20>;
 814         };
 815
 816         qos_vio1_isp_w1: qos@ffad0180 {
 817                 compatible = "syscon";
 818                 reg = <0xffad0180 0x20>;
 819         };
 820
 821         qos_vio0_vop: qos@ffad0400 {
 822                 compatible = "syscon";
 823                 reg = <0xffad0400 0x20>;
 824         };
 825
 826         qos_vio0_vip: qos@ffad0480 {
 827                 compatible = "syscon";
 828                 reg = <0xffad0480 0x20>;
 829         };
 830
 831         qos_vio0_iep: qos@ffad0500 {
 832                 compatible = "syscon";
 833                 reg = <0xffad0500 0x20>;
 834         };
 835
 836         qos_vio2_rga_r: qos@ffad0800 {
 837                 compatible = "syscon";
 838                 reg = <0xffad0800 0x20>;
 839         };
 840
 841         qos_vio2_rga_w: qos@ffad0880 {
 842                 compatible = "syscon";
 843                 reg = <0xffad0880 0x20>;
 844         };
 845
 846         qos_vio1_isp_r: qos@ffad0900 {
 847                 compatible = "syscon";
 848                 reg = <0xffad0900 0x20>;
 849         };
 850
 851         qos_video: qos@ffae0000 {
 852                 compatible = "syscon";
 853                 reg = <0xffae0000 0x20>;
 854         };
 855
 856         qos_hevc_r: qos@ffaf0000 {
 857                 compatible = "syscon";
 858                 reg = <0xffaf0000 0x20>;
 859         };
 860
 861         qos_hevc_w: qos@ffaf0080 {
 862                 compatible = "syscon";
 863                 reg = <0xffaf0080 0x20>;
 864         };
 865
 866         pmu: power-management@ff730000 {
 867                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 868                 reg = <0xff730000 0x100>;
 869
 870                 power: power-controller {
 871                         compatible = "rockchip,rk3288-power-controller";
 872                         #power-domain-cells = <1>;
 873                         #address-cells = <1>;
 874                         #size-cells = <0>;
 875
 876                         /*
 877                          * Note: Although SCLK_* are the working clocks
 878                          * of device without including on the NOC, needed for
 879                          * synchronous reset.
 880                          *
 881                          * The clocks on the which NOC:
 882                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 883                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 884                          * ACLK_RGA is on ACLK_RGA_NIU.
 885                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 886                          *
 887                          * Which clock are device clocks:
 888                          *      clocks          devices
 889                          *      *_IEP           IEP:Image Enhancement Processor
 890                          *      *_ISP           ISP:Image Signal Processing
 891                          *      *_VIP           VIP:Video Input Processor
 892                          *      *_VOP*          VOP:Visual Output Processor
 893                          *      *_RGA           RGA
 894                          *      *_EDP*          EDP
 895                          *      *_LVDS_*        LVDS
 896                          *      *_HDMI          HDMI
 897                          *      *_MIPI_*        MIPI
 898                          */
 899                         pd_vio@RK3288_PD_VIO {
 900                                 reg = <RK3288_PD_VIO>;
 901                                 clocks = <&cru ACLK_IEP>,
 902                                          <&cru ACLK_ISP>,
 903                                          <&cru ACLK_RGA>,
 904                                          <&cru ACLK_VIP>,
 905                                          <&cru ACLK_VOP0>,
 906                                          <&cru ACLK_VOP1>,
 907                                          <&cru DCLK_VOP0>,
 908                                          <&cru DCLK_VOP1>,
 909                                          <&cru HCLK_IEP>,
 910                                          <&cru HCLK_ISP>,
 911                                          <&cru HCLK_RGA>,
 912                                          <&cru HCLK_VIP>,
 913                                          <&cru HCLK_VOP0>,
 914                                          <&cru HCLK_VOP1>,
 915                                          <&cru PCLK_EDP_CTRL>,
 916                                          <&cru PCLK_HDMI_CTRL>,
 917                                          <&cru PCLK_LVDS_PHY>,
 918                                          <&cru PCLK_MIPI_CSI>,
 919                                          <&cru PCLK_MIPI_DSI0>,
 920                                          <&cru PCLK_MIPI_DSI1>,
 921                                          <&cru SCLK_EDP_24M>,
 922                                          <&cru SCLK_EDP>,
 923                                          <&cru SCLK_ISP_JPE>,
 924                                          <&cru SCLK_ISP>,
 925                                          <&cru SCLK_RGA>;
 926                                 pm_qos = <&qos_vio0_iep>,
 927                                          <&qos_vio1_vop>,
 928                                          <&qos_vio1_isp_w0>,
 929                                          <&qos_vio1_isp_w1>,
 930                                          <&qos_vio0_vop>,
 931                                          <&qos_vio0_vip>,
 932                                          <&qos_vio2_rga_r>,
 933                                          <&qos_vio2_rga_w>,
 934                                          <&qos_vio1_isp_r>;
 935                         };
 936
 937                         /*
 938                          * Note: The following 3 are HEVC(H.265) clocks,
 939                          * and on the ACLK_HEVC_NIU (NOC).
 940                          */
 941                         pd_hevc@RK3288_PD_HEVC {
 942                                 reg = <RK3288_PD_HEVC>;
 943                                 clocks = <&cru ACLK_HEVC>,
 944                                          <&cru SCLK_HEVC_CABAC>,
 945                                          <&cru SCLK_HEVC_CORE>;
 946                                 pm_qos = <&qos_hevc_r>,
 947                                          <&qos_hevc_w>;
 948                         };
 949
 950                         /*
 951                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 952                          * (video endecoder & decoder) clocks that on the
 953                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 954                          */
 955                         pd_video@RK3288_PD_VIDEO {
 956                                 reg = <RK3288_PD_VIDEO>;
 957                                 clocks = <&cru ACLK_VCODEC>,
 958                                          <&cru HCLK_VCODEC>;
 959                                 pm_qos = <&qos_video>;
 960                         };
 961
 962                         /*
 963                          * Note: ACLK_GPU is the GPU clock,
 964                          * and on the ACLK_GPU_NIU (NOC).
 965                          */
 966                         pd_gpu@RK3288_PD_GPU {
 967                                 reg = <RK3288_PD_GPU>;
 968                                 clocks = <&cru ACLK_GPU>;
 969                                 pm_qos = <&qos_gpu_r>,
 970                                          <&qos_gpu_w>;
 971                         };
 972                 };
 973
 974                 reboot-mode {
 975                         compatible = "syscon-reboot-mode";
 976                         offset = <0x94>;
 977                         mode-normal = <BOOT_NORMAL>;
 978                         mode-recovery = <BOOT_RECOVERY>;
 979                         mode-bootloader = <BOOT_FASTBOOT>;
 980                         mode-loader = <BOOT_BL_DOWNLOAD>;
 981                         mode-ums = <BOOT_UMS>;
 982                 };
 983         };
 984
 985         sgrf: syscon@ff740000 {
 986                 compatible = "rockchip,rk3288-sgrf", "syscon";
 987                 reg = <0xff740000 0x1000>;
 988         };
 989
 990         cru: clock-controller@ff760000 {
 991                 compatible = "rockchip,rk3288-cru";
 992                 reg = <0xff760000 0x1000>;
 993                 rockchip,grf = <&grf>;
 994                 #clock-cells = <1>;
 995                 #reset-cells = <1>;
 996                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 997                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 998                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 999                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
1000                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
1001                                   <&cru PCLK_PERI>;
1002                 assigned-clock-rates = <0>, <0>,
1003                                        <594000000>, <400000000>,
1004                                        <500000000>, <300000000>,
1005                                        <150000000>, <75000000>,
1006                                        <300000000>, <150000000>,
1007                                        <75000000>;
1008                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
1009         };
1010
1011         grf: syscon@ff770000 {
1012                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
1013                 reg = <0xff770000 0x1000>;
1014
1015                 edp_phy: edp-phy {
1016                         compatible = "rockchip,rk3288-dp-phy";
1017                         clocks = <&cru SCLK_EDP_24M>;
1018                         clock-names = "24m";
1019                         #phy-cells = <0>;
1020                         status = "disabled";
1021                 };
1022
1023                 io_domains: io-domains {
1024                         compatible = "rockchip,rk3288-io-voltage-domain";
1025                         status = "disabled";
1026                 };
1027
1028                 usbphy: usbphy {
1029                         compatible = "rockchip,rk3288-usb-phy";
1030                         #address-cells = <1>;
1031                         #size-cells = <0>;
1032                         status = "disabled";
1033
1034                         usbphy0: usb-phy@320 {
1035                                 #phy-cells = <0>;
1036                                 reg = <0x320>;
1037                                 clocks = <&cru SCLK_OTGPHY0>;
1038                                 clock-names = "phyclk";
1039                                 #clock-cells = <0>;
1040                                 resets = <&cru SRST_USBOTG_PHY>;
1041                                 reset-names = "phy-reset";
1042                         };
1043
1044                         usbphy1: usb-phy@334 {
1045                                 #phy-cells = <0>;
1046                                 reg = <0x334>;
1047                                 clocks = <&cru SCLK_OTGPHY1>;
1048                                 clock-names = "phyclk";
1049                                 #clock-cells = <0>;
1050                         };
1051
1052                         usbphy2: usb-phy@348 {
1053                                 #phy-cells = <0>;
1054                                 reg = <0x348>;
1055                                 clocks = <&cru SCLK_OTGPHY2>;
1056                                 clock-names = "phyclk";
1057                                 #clock-cells = <0>;
1058                                 resets = <&cru SRST_USBHOST1_PHY>;
1059                                 reset-names = "phy-reset";
1060                         };
1061                 };
1062         };
1063
1064         wdt: watchdog@ff800000 {
1065                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1066                 reg = <0xff800000 0x100>;
1067                 clocks = <&cru PCLK_WDT>;
1068                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1069                 status = "disabled";
1070         };
1071
1072         spdif: sound@ff88b0000 {
1073                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1074                 reg = <0xff8b0000 0x10000>;
1075                 #sound-dai-cells = <0>;
1076                 clock-names = "hclk", "mclk";
1077                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1078                 dmas = <&dmac_bus_s 3>;
1079                 dma-names = "tx";
1080                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1081                 pinctrl-names = "default";
1082                 pinctrl-0 = <&spdif_tx>;
1083                 rockchip,grf = <&grf>;
1084                 status = "disabled";
1085         };
1086
1087         i2s: i2s@ff890000 {
1088                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1089                 reg = <0xff890000 0x10000>;
1090                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1091                 #address-cells = <1>;
1092                 #size-cells = <0>;
1093                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1094                 dma-names = "tx", "rx";
1095                 clock-names = "i2s_hclk", "i2s_clk";
1096                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1097                 pinctrl-names = "default";
1098                 pinctrl-0 = <&i2s0_bus>;
1099                 rockchip,playback-channels = <8>;
1100                 rockchip,capture-channels = <2>;
1101                 status = "disabled";
1102         };
1103
1104         cif_isp0: cif_isp@ff910000 {
1105                 compatible = "rockchip,rk3288-cif-isp";
1106                 rockchip,grf = <&grf>;
1107                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1108                 reg-names = "register", "csihost-register";
1109                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1110                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1111                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1112                         <&cru SCLK_MIPIDSI_24M>;
1113                 clock-names = "aclk_isp", "hclk_isp",
1114                         "sclk_isp", "sclk_isp_jpe",
1115                         "pclk_mipi_csi", "pclk_isp_in",
1116                         "sclk_mipidsi_24m";
1117                 resets = <&cru SRST_ISP>;
1118                 reset-names = "rst_isp";
1119                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1120                 interrupt-names = "cif_isp10_irq";
1121                 status = "disabled";
1122         };
1123
1124         rga: rga@ff920000 {
1125                 compatible = "rockchip,rk3288-rga";
1126                 reg = <0xff920000 0x180>;
1127                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1128                 interrupt-names = "rga";
1129                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1130                 clock-names = "aclk", "hclk", "sclk";
1131                 power-domains = <&power RK3288_PD_VIO>;
1132                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1133                 reset-names = "core", "axi", "ahb";
1134                 dma-coherent;
1135                 status = "disabled";
1136         };
1137
1138         vopb: vop@ff930000 {
1139                 compatible = "rockchip,rk3288-vop";
1140                 reg = <0xff930000 0x19c>;
1141                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1142                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1143                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1144                 power-domains = <&power RK3288_PD_VIO>;
1145                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1146                 reset-names = "axi", "ahb", "dclk";
1147                 iommus = <&vopb_mmu>;
1148                 status = "disabled";
1149
1150                 vopb_out: port {
1151                         #address-cells = <1>;
1152                         #size-cells = <0>;
1153
1154                         vopb_out_hdmi: endpoint@0 {
1155                                 reg = <0>;
1156                                 remote-endpoint = <&hdmi_in_vopb>;
1157                         };
1158
1159                         vopb_out_edp: endpoint@1 {
1160                                 reg = <1>;
1161                                 remote-endpoint = <&edp_in_vopb>;
1162                         };
1163
1164                         vopb_out_mipi: endpoint@2 {
1165                                 reg = <2>;
1166                                 remote-endpoint = <&mipi_in_vopb>;
1167                         };
1168
1169                         vopb_out_lvds: endpoint@3 {
1170                                 reg = <3>;
1171                                 remote-endpoint = <&lvds_in_vopb>;
1172                         };
1173                 };
1174         };
1175
1176         vopb_mmu: iommu@ff930300 {
1177                 compatible = "rockchip,iommu";
1178                 reg = <0xff930300 0x100>;
1179                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1180                 interrupt-names = "vopb_mmu";
1181                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1182                 clock-names = "aclk", "hclk";
1183                 power-domains = <&power RK3288_PD_VIO>;
1184                 #iommu-cells = <0>;
1185                 status = "disabled";
1186         };
1187
1188         vopl: vop@ff940000 {
1189                 compatible = "rockchip,rk3288-vop";
1190                 reg = <0xff940000 0x19c>;
1191                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1192                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1193                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1194                 power-domains = <&power RK3288_PD_VIO>;
1195                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1196                 reset-names = "axi", "ahb", "dclk";
1197                 iommus = <&vopl_mmu>;
1198                 status = "disabled";
1199
1200                 vopl_out: port {
1201                         #address-cells = <1>;
1202                         #size-cells = <0>;
1203
1204                         vopl_out_hdmi: endpoint@0 {
1205                                 reg = <0>;
1206                                 remote-endpoint = <&hdmi_in_vopl>;
1207                         };
1208
1209                         vopl_out_edp: endpoint@1 {
1210                                 reg = <1>;
1211                                 remote-endpoint = <&edp_in_vopl>;
1212                         };
1213
1214                         vopl_out_mipi: endpoint@2 {
1215                                 reg = <2>;
1216                                 remote-endpoint = <&mipi_in_vopl>;
1217                         };
1218
1219                         vopl_out_lvds: endpoint@3 {
1220                                 reg = <3>;
1221                                 remote-endpoint = <&lvds_in_vopl>;
1222                         };
1223
1224                 };
1225         };
1226
1227         vopl_mmu: iommu@ff940300 {
1228                 compatible = "rockchip,iommu";
1229                 reg = <0xff940300 0x100>;
1230                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1231                 interrupt-names = "vopl_mmu";
1232                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1233                 clock-names = "aclk", "hclk";
1234                 power-domains = <&power RK3288_PD_VIO>;
1235                 #iommu-cells = <0>;
1236                 status = "disabled";
1237         };
1238
1239         mipi_dsi: mipi@ff960000 {
1240                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1241                 reg = <0xff960000 0x4000>;
1242                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1243                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1244                 clock-names = "ref", "pclk";
1245                 power-domains = <&power RK3288_PD_VIO>;
1246                 rockchip,grf = <&grf>;
1247                 #address-cells = <1>;
1248                 #size-cells = <0>;
1249                 status = "disabled";
1250
1251                 ports {
1252                         mipi_in: port {
1253                                 #address-cells = <1>;
1254                                 #size-cells = <0>;
1255                                 mipi_in_vopb: endpoint@0 {
1256                                         reg = <0>;
1257                                         remote-endpoint = <&vopb_out_mipi>;
1258                                 };
1259                                 mipi_in_vopl: endpoint@1 {
1260                                         reg = <1>;
1261                                         remote-endpoint = <&vopl_out_mipi>;
1262                                 };
1263                         };
1264                 };
1265         };
1266
1267         edp: dp@ff970000 {
1268                 compatible = "rockchip,rk3288-dp";
1269                 reg = <0xff970000 0x4000>;
1270                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1271                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1272                 clock-names = "dp", "pclk";
1273                 power-domains = <&power RK3288_PD_VIO>;
1274                 phys = <&edp_phy>;
1275                 phy-names = "dp";
1276                 resets = <&cru SRST_EDP>;
1277                 reset-names = "dp";
1278                 rockchip,grf = <&grf>;
1279                 status = "disabled";
1280
1281                 ports {
1282                         #address-cells = <1>;
1283                         #size-cells = <0>;
1284                         edp_in: port@0 {
1285                                 reg = <0>;
1286                                 #address-cells = <1>;
1287                                 #size-cells = <0>;
1288                                 edp_in_vopb: endpoint@0 {
1289                                         reg = <0>;
1290                                         remote-endpoint = <&vopb_out_edp>;
1291                                 };
1292                                 edp_in_vopl: endpoint@1 {
1293                                         reg = <1>;
1294                                         remote-endpoint = <&vopl_out_edp>;
1295                                 };
1296                         };
1297                 };
1298         };
1299
1300         lvds: lvds@ff96c000 {
1301                 compatible = "rockchip,rk3288-lvds";
1302                 reg = <0xff96c000 0x4000>;
1303                 clocks = <&cru PCLK_LVDS_PHY>;
1304                 clock-names = "pclk_lvds";
1305                 pinctrl-names = "default";
1306                 pinctrl-0 = <&lcdc0_ctl>;
1307                 power-domains = <&power RK3288_PD_VIO>;
1308                 rockchip,grf = <&grf>;
1309                 status = "disabled";
1310
1311                 ports {
1312                         #address-cells = <1>;
1313                         #size-cells = <0>;
1314
1315                         lvds_in: port@0 {
1316                                 reg = <0>;
1317
1318                                 #address-cells = <1>;
1319                                 #size-cells = <0>;
1320
1321                                 lvds_in_vopb: endpoint@0 {
1322                                         reg = <0>;
1323                                         remote-endpoint = <&vopb_out_lvds>;
1324                                 };
1325                                 lvds_in_vopl: endpoint@1 {
1326                                         reg = <1>;
1327                                         remote-endpoint = <&vopl_out_lvds>;
1328                                 };
1329                         };
1330                 };
1331         };
1332
1333         hdmi: hdmi@ff980000 {
1334                 compatible = "rockchip,rk3288-dw-hdmi";
1335                 reg = <0xff980000 0x20000>;
1336                 reg-io-width = <4>;
1337                 rockchip,grf = <&grf>;
1338                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1339                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1340                 clock-names = "iahb", "isfr";
1341                 pinctrl-names = "default";
1342                 pinctrl-0 = <&hdmi_ddc>;
1343                 power-domains = <&power RK3288_PD_VIO>;
1344                 status = "disabled";
1345
1346                 ports {
1347                         hdmi_in: port {
1348                                 #address-cells = <1>;
1349                                 #size-cells = <0>;
1350                                 hdmi_in_vopb: endpoint@0 {
1351                                         reg = <0>;
1352                                         remote-endpoint = <&vopb_out_hdmi>;
1353                                 };
1354                                 hdmi_in_vopl: endpoint@1 {
1355                                         reg = <1>;
1356                                         remote-endpoint = <&vopl_out_hdmi>;
1357                                 };
1358                         };
1359                 };
1360         };
1361
1362         vpu: video-codec@ff9a0000 {
1363                 compatible = "rockchip,rk3288-vpu";
1364                 reg = <0xff9a0000 0x800>;
1365                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1366                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1367                 interrupt-names = "vepu", "vdpu";
1368                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1369                 clock-names = "aclk", "hclk";
1370                 power-domains = <&power RK3288_PD_VIDEO>;
1371                 iommus = <&vpu_mmu>;
1372                 assigned-clocks = <&cru ACLK_VCODEC>;
1373                 assigned-clock-rates = <400000000>;
1374                 status = "disabled";
1375         };
1376
1377         vpu_service: vpu-service@ff9a0000 {
1378                 compatible = "rockchip,vpu_service";
1379                 reg = <0xff9a0000 0x800>;
1380                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1381                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1382                 interrupt-names = "irq_enc", "irq_dec";
1383                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1384                 clock-names = "aclk_vcodec", "hclk_vcodec";
1385                 power-domains = <&power RK3288_PD_VIDEO>;
1386                 rockchip,grf = <&grf>;
1387                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1388                 reset-names = "video_a", "video_h";
1389                 iommus = <&vpu_mmu>;
1390                 iommu_enabled = <1>;
1391                 dev_mode = <0>;
1392                 status = "disabled";
1393                 /* 0 means ion, 1 means drm */
1394                 allocator = <1>;
1395         };
1396
1397         vpu_mmu: iommu@ff9a0800 {
1398                 compatible = "rockchip,iommu";
1399                 reg = <0xff9a0800 0x100>;
1400                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1401                 interrupt-names = "vpu_mmu";
1402                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1403                 clock-names = "aclk", "hclk";
1404                 power-domains = <&power RK3288_PD_VIDEO>;
1405                 #iommu-cells = <0>;
1406         };
1407
1408         hevc_service: hevc-service@ff9c0000 {
1409                 compatible = "rockchip,hevc_service";
1410                 reg = <0xff9c0000 0x400>;
1411                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1412                 interrupt-names = "irq_dec";
1413                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1414                         <&cru SCLK_HEVC_CORE>,
1415                         <&cru SCLK_HEVC_CABAC>;
1416                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1417                         "clk_cabac";
1418                 /*
1419                  * The 4K hevc would also work well with 500/125/300/300,
1420                  * no more err irq and reset request.
1421                  */
1422                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1423                                   <&cru SCLK_HEVC_CORE>,
1424                                   <&cru SCLK_HEVC_CABAC>;
1425                 assigned-clock-rates = <400000000>, <100000000>,
1426                                        <300000000>, <300000000>;
1427
1428                 resets = <&cru SRST_HEVC>;
1429                 reset-names = "video";
1430                 power-domains = <&power RK3288_PD_HEVC>;
1431                 rockchip,grf = <&grf>;
1432                 dev_mode = <1>;
1433                 iommus = <&hevc_mmu>;
1434                 iommu_enabled = <1>;
1435                 status = "disabled";
1436                 /* 0 means ion, 1 means drm */
1437                 allocator = <1>;
1438         };
1439
1440         hevc_mmu: iommu@ff9c0440 {
1441                 compatible = "rockchip,iommu";
1442                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1443                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1444                 interrupt-names = "hevc_mmu";
1445                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1446                         <&cru SCLK_HEVC_CORE>,
1447                         <&cru SCLK_HEVC_CABAC>;
1448                 clock-names = "aclk", "hclk", "clk_core",
1449                         "clk_cabac";
1450                 power-domains = <&power RK3288_PD_HEVC>;
1451                 #iommu-cells = <0>;
1452         };
1453
1454         gpu: gpu@ffa30000 {
1455                 compatible = "arm,malit764",
1456                              "arm,malit76x",
1457                              "arm,malit7xx",
1458                              "arm,mali-midgard";
1459                 reg = <0xffa30000 0x10000>;
1460                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1461                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1462                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1463                 interrupt-names = "JOB", "MMU", "GPU";
1464                 clocks = <&cru ACLK_GPU>;
1465                 clock-names = "clk_mali";
1466                 operating-points-v2 = <&gpu_opp_table>;
1467                 #cooling-cells = <2>; /* min followed by max */
1468                 power-domains = <&power RK3288_PD_GPU>;
1469                 status = "disabled";
1470
1471                 upthreshold = <75>;
1472                 downdifferential = <10>;
1473
1474                 gpu_power_model: power_model {
1475                         compatible = "arm,mali-simple-power-model";
1476                         voltage = <950>;
1477                         frequency = <500>;
1478                         static-power = <300>;
1479                         dynamic-power = <396>;
1480                         ts = <32000 4700 (-80) 2>;
1481                         thermal-zone = "gpu_thermal";
1482                 };
1483         };
1484
1485         gpu_opp_table: opp-table1 {
1486                 compatible = "operating-points-v2";
1487
1488                 opp@100000000 {
1489                         opp-hz = /bits/ 64 <100000000>;
1490                         opp-microvolt = <950000>;
1491                 };
1492                 opp@200000000 {
1493                         opp-hz = /bits/ 64 <200000000>;
1494                         opp-microvolt = <950000>;
1495                 };
1496                 opp@300000000 {
1497                         opp-hz = /bits/ 64 <300000000>;
1498                         opp-microvolt = <1000000>;
1499                 };
1500                 opp@400000000 {
1501                         opp-hz = /bits/ 64 <400000000>;
1502                         opp-microvolt = <1100000>;
1503                 };
1504                 opp@600000000 {
1505                         opp-hz = /bits/ 64 <600000000>;
1506                         opp-microvolt = <1250000>;
1507                 };
1508         };
1509
1510         noc: syscon@ffac0000 {
1511                 compatible = "rockchip,rk3288-noc", "syscon";
1512                 reg = <0xffac0000 0x2000>;
1513         };
1514
1515         efuse: efuse@ffb40000 {
1516                 compatible = "rockchip,rockchip-efuse";
1517                 reg = <0xffb40000 0x20>;
1518                 #address-cells = <1>;
1519                 #size-cells = <1>;
1520                 clocks = <&cru PCLK_EFUSE256>;
1521                 clock-names = "pclk_efuse";
1522
1523                 cpu_leakage: cpu_leakage@17 {
1524                         reg = <0x17 0x1>;
1525                 };
1526         };
1527
1528         gic: interrupt-controller@ffc01000 {
1529                 compatible = "arm,gic-400";
1530                 interrupt-controller;
1531                 #interrupt-cells = <3>;
1532                 #address-cells = <0>;
1533
1534                 reg = <0xffc01000 0x1000>,
1535                       <0xffc02000 0x1000>,
1536                       <0xffc04000 0x2000>,
1537                       <0xffc06000 0x2000>;
1538                 interrupts = <GIC_PPI 9 0xf04>;
1539         };
1540
1541         pinctrl: pinctrl {
1542                 compatible = "rockchip,rk3288-pinctrl";
1543                 rockchip,grf = <&grf>;
1544                 rockchip,pmu = <&pmu>;
1545                 #address-cells = <1>;
1546                 #size-cells = <1>;
1547                 ranges;
1548
1549                 gpio0: gpio0@ff750000 {
1550                         compatible = "rockchip,gpio-bank";
1551                         reg =   <0xff750000 0x100>;
1552                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1553                         clocks = <&cru PCLK_GPIO0>;
1554
1555                         gpio-controller;
1556                         #gpio-cells = <2>;
1557
1558                         interrupt-controller;
1559                         #interrupt-cells = <2>;
1560                 };
1561
1562                 gpio1: gpio1@ff780000 {
1563                         compatible = "rockchip,gpio-bank";
1564                         reg = <0xff780000 0x100>;
1565                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1566                         clocks = <&cru PCLK_GPIO1>;
1567
1568                         gpio-controller;
1569                         #gpio-cells = <2>;
1570
1571                         interrupt-controller;
1572                         #interrupt-cells = <2>;
1573                 };
1574
1575                 gpio2: gpio2@ff790000 {
1576                         compatible = "rockchip,gpio-bank";
1577                         reg = <0xff790000 0x100>;
1578                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1579                         clocks = <&cru PCLK_GPIO2>;
1580
1581                         gpio-controller;
1582                         #gpio-cells = <2>;
1583
1584                         interrupt-controller;
1585                         #interrupt-cells = <2>;
1586                 };
1587
1588                 gpio3: gpio3@ff7a0000 {
1589                         compatible = "rockchip,gpio-bank";
1590                         reg = <0xff7a0000 0x100>;
1591                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1592                         clocks = <&cru PCLK_GPIO3>;
1593
1594                         gpio-controller;
1595                         #gpio-cells = <2>;
1596
1597                         interrupt-controller;
1598                         #interrupt-cells = <2>;
1599                 };
1600
1601                 gpio4: gpio4@ff7b0000 {
1602                         compatible = "rockchip,gpio-bank";
1603                         reg = <0xff7b0000 0x100>;
1604                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1605                         clocks = <&cru PCLK_GPIO4>;
1606
1607                         gpio-controller;
1608                         #gpio-cells = <2>;
1609
1610                         interrupt-controller;
1611                         #interrupt-cells = <2>;
1612                 };
1613
1614                 gpio5: gpio5@ff7c0000 {
1615                         compatible = "rockchip,gpio-bank";
1616                         reg = <0xff7c0000 0x100>;
1617                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1618                         clocks = <&cru PCLK_GPIO5>;
1619
1620                         gpio-controller;
1621                         #gpio-cells = <2>;
1622
1623                         interrupt-controller;
1624                         #interrupt-cells = <2>;
1625                 };
1626
1627                 gpio6: gpio6@ff7d0000 {
1628                         compatible = "rockchip,gpio-bank";
1629                         reg = <0xff7d0000 0x100>;
1630                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1631                         clocks = <&cru PCLK_GPIO6>;
1632
1633                         gpio-controller;
1634                         #gpio-cells = <2>;
1635
1636                         interrupt-controller;
1637                         #interrupt-cells = <2>;
1638                 };
1639
1640                 gpio7: gpio7@ff7e0000 {
1641                         compatible = "rockchip,gpio-bank";
1642                         reg = <0xff7e0000 0x100>;
1643                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1644                         clocks = <&cru PCLK_GPIO7>;
1645
1646                         gpio-controller;
1647                         #gpio-cells = <2>;
1648
1649                         interrupt-controller;
1650                         #interrupt-cells = <2>;
1651                 };
1652
1653                 gpio8: gpio8@ff7f0000 {
1654                         compatible = "rockchip,gpio-bank";
1655                         reg = <0xff7f0000 0x100>;
1656                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1657                         clocks = <&cru PCLK_GPIO8>;
1658
1659                         gpio-controller;
1660                         #gpio-cells = <2>;
1661
1662                         interrupt-controller;
1663                         #interrupt-cells = <2>;
1664                 };
1665
1666                 hdmi {
1667                         hdmi_ddc: hdmi-ddc {
1668                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1669                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1670                         };
1671                 };
1672
1673                 pcfg_pull_up: pcfg-pull-up {
1674                         bias-pull-up;
1675                 };
1676
1677                 pcfg_pull_down: pcfg-pull-down {
1678                         bias-pull-down;
1679                 };
1680
1681                 pcfg_pull_none: pcfg-pull-none {
1682                         bias-disable;
1683                 };
1684
1685                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1686                         bias-disable;
1687                         drive-strength = <12>;
1688                 };
1689
1690                 sleep {
1691                         global_pwroff: global-pwroff {
1692                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1693                         };
1694
1695                         ddrio_pwroff: ddrio-pwroff {
1696                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1697                         };
1698
1699                         ddr0_retention: ddr0-retention {
1700                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1701                         };
1702
1703                         ddr1_retention: ddr1-retention {
1704                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1705                         };
1706                 };
1707
1708                 edp {
1709                         edp_hpd: edp-hpd {
1710                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1711                         };
1712                 };
1713
1714                 i2c0 {
1715                         i2c0_xfer: i2c0-xfer {
1716                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1717                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1718                         };
1719                 };
1720
1721                 i2c1 {
1722                         i2c1_xfer: i2c1-xfer {
1723                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1724                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1725                         };
1726                 };
1727
1728                 i2c2 {
1729                         i2c2_xfer: i2c2-xfer {
1730                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1731                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1732                         };
1733                 };
1734
1735                 i2c3 {
1736                         i2c3_xfer: i2c3-xfer {
1737                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1738                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1739                         };
1740                 };
1741
1742                 i2c4 {
1743                         i2c4_xfer: i2c4-xfer {
1744                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1745                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1746                         };
1747                 };
1748
1749                 i2c5 {
1750                         i2c5_xfer: i2c5-xfer {
1751                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1752                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1753                         };
1754                 };
1755
1756                 i2s0 {
1757                         i2s0_bus: i2s0-bus {
1758                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1759                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1760                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1761                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1762                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1763                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1764                         };
1765                 };
1766
1767                 lcdc0 {
1768                         lcdc0_ctl: lcdc0-ctl {
1769                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1770                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1771                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1772                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774                 };
1775
1776                 sdmmc {
1777                         sdmmc_clk: sdmmc-clk {
1778                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1779                         };
1780
1781                         sdmmc_cmd: sdmmc-cmd {
1782                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1783                         };
1784
1785                         sdmmc_cd: sdmcc-cd {
1786                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1787                         };
1788
1789                         sdmmc_bus1: sdmmc-bus1 {
1790                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1791                         };
1792
1793                         sdmmc_bus4: sdmmc-bus4 {
1794                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1795                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1796                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1797                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1798                         };
1799                 };
1800
1801                 sdio0 {
1802                         sdio0_bus1: sdio0-bus1 {
1803                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1804                         };
1805
1806                         sdio0_bus4: sdio0-bus4 {
1807                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1808                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1809                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1810                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1811                         };
1812
1813                         sdio0_cmd: sdio0-cmd {
1814                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1815                         };
1816
1817                         sdio0_clk: sdio0-clk {
1818                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1819                         };
1820
1821                         sdio0_cd: sdio0-cd {
1822                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1823                         };
1824
1825                         sdio0_wp: sdio0-wp {
1826                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1827                         };
1828
1829                         sdio0_pwr: sdio0-pwr {
1830                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1831                         };
1832
1833                         sdio0_bkpwr: sdio0-bkpwr {
1834                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1835                         };
1836
1837                         sdio0_int: sdio0-int {
1838                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1839                         };
1840                 };
1841
1842                 sdio1 {
1843                         sdio1_bus1: sdio1-bus1 {
1844                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1845                         };
1846
1847                         sdio1_bus4: sdio1-bus4 {
1848                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1849                                                 <3 25 4 &pcfg_pull_up>,
1850                                                 <3 26 4 &pcfg_pull_up>,
1851                                                 <3 27 4 &pcfg_pull_up>;
1852                         };
1853
1854                         sdio1_cd: sdio1-cd {
1855                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1856                         };
1857
1858                         sdio1_wp: sdio1-wp {
1859                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1860                         };
1861
1862                         sdio1_bkpwr: sdio1-bkpwr {
1863                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1864                         };
1865
1866                         sdio1_int: sdio1-int {
1867                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1868                         };
1869
1870                         sdio1_cmd: sdio1-cmd {
1871                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1872                         };
1873
1874                         sdio1_clk: sdio1-clk {
1875                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1876                         };
1877
1878                         sdio1_pwr: sdio1-pwr {
1879                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1880                         };
1881                 };
1882
1883                 emmc {
1884                         emmc_clk: emmc-clk {
1885                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1886                         };
1887
1888                         emmc_cmd: emmc-cmd {
1889                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1890                         };
1891
1892                         emmc_pwr: emmc-pwr {
1893                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1894                         };
1895
1896                         emmc_bus1: emmc-bus1 {
1897                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1898                         };
1899
1900                         emmc_bus4: emmc-bus4 {
1901                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1902                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1903                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1904                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1905                         };
1906
1907                         emmc_bus8: emmc-bus8 {
1908                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1909                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1910                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1911                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1912                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1913                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1914                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1915                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1916                         };
1917                 };
1918
1919                 spi0 {
1920                         spi0_clk: spi0-clk {
1921                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1922                         };
1923                         spi0_cs0: spi0-cs0 {
1924                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1925                         };
1926                         spi0_tx: spi0-tx {
1927                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1928                         };
1929                         spi0_rx: spi0-rx {
1930                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1931                         };
1932                         spi0_cs1: spi0-cs1 {
1933                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1934                         };
1935                 };
1936                 spi1 {
1937                         spi1_clk: spi1-clk {
1938                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1939                         };
1940                         spi1_cs0: spi1-cs0 {
1941                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1942                         };
1943                         spi1_rx: spi1-rx {
1944                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1945                         };
1946                         spi1_tx: spi1-tx {
1947                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1948                         };
1949                 };
1950
1951                 spi2 {
1952                         spi2_cs1: spi2-cs1 {
1953                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1954                         };
1955                         spi2_clk: spi2-clk {
1956                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1957                         };
1958                         spi2_cs0: spi2-cs0 {
1959                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1960                         };
1961                         spi2_rx: spi2-rx {
1962                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1963                         };
1964                         spi2_tx: spi2-tx {
1965                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1966                         };
1967                 };
1968
1969                 uart0 {
1970                         uart0_xfer: uart0-xfer {
1971                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1972                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1973                         };
1974
1975                         uart0_cts: uart0-cts {
1976                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1977                         };
1978
1979                         uart0_rts: uart0-rts {
1980                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1981                         };
1982                 };
1983
1984                 uart1 {
1985                         uart1_xfer: uart1-xfer {
1986                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1987                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1988                         };
1989
1990                         uart1_cts: uart1-cts {
1991                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1992                         };
1993
1994                         uart1_rts: uart1-rts {
1995                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1996                         };
1997                 };
1998
1999                 uart2 {
2000                         uart2_xfer: uart2-xfer {
2001                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
2002                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2003                         };
2004                         /* no rts / cts for uart2 */
2005                 };
2006
2007                 uart3 {
2008                         uart3_xfer: uart3-xfer {
2009                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2010                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2011                         };
2012
2013                         uart3_cts: uart3-cts {
2014                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2015                         };
2016
2017                         uart3_rts: uart3-rts {
2018                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2019                         };
2020                 };
2021
2022                 uart4 {
2023                         uart4_xfer: uart4-xfer {
2024                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2025                                                 <5 13 3 &pcfg_pull_none>;
2026                         };
2027
2028                         uart4_cts: uart4-cts {
2029                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2030                         };
2031
2032                         uart4_rts: uart4-rts {
2033                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2034                         };
2035                 };
2036
2037                 tsadc {
2038                         otp_gpio: otp-gpio {
2039                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2040                         };
2041
2042                         otp_out: otp-out {
2043                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2044                         };
2045                 };
2046
2047                 pwm0 {
2048                         pwm0_pin: pwm0-pin {
2049                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2050                         };
2051                 };
2052
2053                 pwm1 {
2054                         pwm1_pin: pwm1-pin {
2055                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2056                         };
2057                 };
2058
2059                 pwm2 {
2060                         pwm2_pin: pwm2-pin {
2061                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2062                         };
2063                 };
2064
2065                 pwm3 {
2066                         pwm3_pin: pwm3-pin {
2067                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2068                         };
2069                 };
2070
2071                 gmac {
2072                         rgmii_pins: rgmii-pins {
2073                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2074                                                 <3 31 3 &pcfg_pull_none>,
2075                                                 <3 26 3 &pcfg_pull_none>,
2076                                                 <3 27 3 &pcfg_pull_none>,
2077                                                 <3 28 3 &pcfg_pull_none_12ma>,
2078                                                 <3 29 3 &pcfg_pull_none_12ma>,
2079                                                 <3 24 3 &pcfg_pull_none_12ma>,
2080                                                 <3 25 3 &pcfg_pull_none_12ma>,
2081                                                 <4 0 3 &pcfg_pull_none>,
2082                                                 <4 5 3 &pcfg_pull_none>,
2083                                                 <4 6 3 &pcfg_pull_none>,
2084                                                 <4 9 3 &pcfg_pull_none_12ma>,
2085                                                 <4 4 3 &pcfg_pull_none_12ma>,
2086                                                 <4 1 3 &pcfg_pull_none>,
2087                                                 <4 3 3 &pcfg_pull_none>;
2088                         };
2089
2090                         rmii_pins: rmii-pins {
2091                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2092                                                 <3 31 3 &pcfg_pull_none>,
2093                                                 <3 28 3 &pcfg_pull_none>,
2094                                                 <3 29 3 &pcfg_pull_none>,
2095                                                 <4 0 3 &pcfg_pull_none>,
2096                                                 <4 5 3 &pcfg_pull_none>,
2097                                                 <4 4 3 &pcfg_pull_none>,
2098                                                 <4 1 3 &pcfg_pull_none>,
2099                                                 <4 2 3 &pcfg_pull_none>,
2100                                                 <4 3 3 &pcfg_pull_none>;
2101                         };
2102                 };
2103
2104                 spdif {
2105                         spdif_tx: spdif-tx {
2106                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2107                         };
2108                 };
2109
2110                 cif {
2111                         cif_dvp_d2d9: cif-dvp-d2d9 {
2112                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2113                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2114                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2115                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2116                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2117                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2118                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2119                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2120                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2121                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2122                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2123                         };
2124                 };
2125         };
2126 };