2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include "skeleton.dtsi"
52 compatible = "rockchip,rk3288";
54 interrupt-parent = <&gic>;
79 compatible = "arm,cortex-a12-pmu";
80 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
90 enable-method = "rockchip,rk3066-smp";
91 rockchip,pmu = <&pmu>;
95 compatible = "arm,cortex-a12";
97 resets = <&cru SRST_CORE0>;
98 operating-points-v2 = <&cpu0_opp_table>;
99 #cooling-cells = <2>; /* min followed by max */
100 clocks = <&cru ARMCLK>;
104 compatible = "arm,cortex-a12";
106 resets = <&cru SRST_CORE1>;
107 operating-points-v2 = <&cpu0_opp_table>;
111 compatible = "arm,cortex-a12";
113 resets = <&cru SRST_CORE2>;
114 operating-points-v2 = <&cpu0_opp_table>;
118 compatible = "arm,cortex-a12";
120 resets = <&cru SRST_CORE3>;
121 operating-points-v2 = <&cpu0_opp_table>;
125 cpu0_opp_table: opp_table0 {
126 compatible = "operating-points-v2";
130 opp-hz = /bits/ 64 <126000000>;
131 opp-microvolt = <900000>;
132 clock-latency-ns = <40000>;
135 opp-hz = /bits/ 64 <216000000>;
136 opp-microvolt = <900000>;
137 clock-latency-ns = <40000>;
140 opp-hz = /bits/ 64 <408000000>;
141 opp-microvolt = <900000>;
142 clock-latency-ns = <40000>;
145 opp-hz = /bits/ 64 <600000000>;
146 opp-microvolt = <900000>;
147 clock-latency-ns = <40000>;
150 opp-hz = /bits/ 64 <696000000>;
151 opp-microvolt = <950000>;
152 clock-latency-ns = <40000>;
155 opp-hz = /bits/ 64 <816000000>;
156 opp-microvolt = <1000000>;
157 clock-latency-ns = <40000>;
161 opp-hz = /bits/ 64 <1008000000>;
162 opp-microvolt = <1050000>;
163 clock-latency-ns = <40000>;
166 opp-hz = /bits/ 64 <1200000000>;
167 opp-microvolt = <1100000>;
168 clock-latency-ns = <40000>;
171 opp-hz = /bits/ 64 <1416000000>;
172 opp-microvolt = <1200000>;
173 clock-latency-ns = <40000>;
176 opp-hz = /bits/ 64 <1512000000>;
177 opp-microvolt = <1300000>;
178 clock-latency-ns = <40000>;
181 opp-hz = /bits/ 64 <1608000000>;
182 opp-microvolt = <1350000>;
183 clock-latency-ns = <40000>;
190 min-volt = <900000>; /* uV */
191 min-freq = <126000>; /* KHz */
192 leakage-adjust-volt = <
196 nvmem-cells = <&cpu_leakage>;
197 nvmem-cell-names = "cpu_leakage";
202 compatible = "arm,amba-bus";
203 #address-cells = <1>;
207 dmac_peri: dma-controller@ff250000 {
208 compatible = "arm,pl330", "arm,primecell";
209 reg = <0xff250000 0x4000>;
210 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
213 arm,pl330-broken-no-flushp;
214 peripherals-req-type-burst;
215 clocks = <&cru ACLK_DMAC2>;
216 clock-names = "apb_pclk";
219 dmac_bus_ns: dma-controller@ff600000 {
220 compatible = "arm,pl330", "arm,primecell";
221 reg = <0xff600000 0x4000>;
222 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
225 arm,pl330-broken-no-flushp;
226 peripherals-req-type-burst;
227 clocks = <&cru ACLK_DMAC1>;
228 clock-names = "apb_pclk";
232 dmac_bus_s: dma-controller@ffb20000 {
233 compatible = "arm,pl330", "arm,primecell";
234 reg = <0xffb20000 0x4000>;
235 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
238 arm,pl330-broken-no-flushp;
239 peripherals-req-type-burst;
240 clocks = <&cru ACLK_DMAC1>;
241 clock-names = "apb_pclk";
246 #address-cells = <1>;
251 * The rk3288 cannot use the memory area above 0xfe000000
252 * for dma operations for some reason. While there is
253 * probably a better solution available somewhere, we
254 * haven't found it yet and while devices with 2GB of ram
255 * are not affected, this issue prevents 4GB from booting.
256 * So to make these devices at least bootable, block
257 * this area for the time being until the real solution
260 dma-unusable@fe000000 {
261 reg = <0xfe000000 0x1000000>;
266 compatible = "fixed-clock";
267 clock-frequency = <24000000>;
268 clock-output-names = "xin24m";
273 compatible = "arm,armv7-timer";
274 arm,cpu-registers-not-fw-configured;
275 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
276 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
277 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
278 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
279 clock-frequency = <24000000>;
282 timer: timer@ff810000 {
283 compatible = "rockchip,rk3288-timer";
284 reg = <0xff810000 0x20>;
285 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&xin24m>, <&cru PCLK_TIMER>;
287 clock-names = "timer", "pclk";
291 compatible = "rockchip,display-subsystem";
292 ports = <&vopl_out>, <&vopb_out>;
295 sdmmc: dwmmc@ff0c0000 {
296 compatible = "rockchip,rk3288-dw-mshc";
297 clock-freq-min-max = <400000 150000000>;
298 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
299 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
300 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
301 fifo-depth = <0x100>;
302 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
303 reg = <0xff0c0000 0x4000>;
307 sdio0: dwmmc@ff0d0000 {
308 compatible = "rockchip,rk3288-dw-mshc";
309 clock-freq-min-max = <400000 150000000>;
310 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
311 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
312 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
313 fifo-depth = <0x100>;
314 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
315 reg = <0xff0d0000 0x4000>;
319 sdio1: dwmmc@ff0e0000 {
320 compatible = "rockchip,rk3288-dw-mshc";
321 clock-freq-min-max = <400000 150000000>;
322 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
323 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
324 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
325 fifo-depth = <0x100>;
326 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
327 reg = <0xff0e0000 0x4000>;
331 emmc: dwmmc@ff0f0000 {
332 compatible = "rockchip,rk3288-dw-mshc";
333 clock-freq-min-max = <400000 150000000>;
334 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
335 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
336 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
337 fifo-depth = <0x100>;
338 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
339 reg = <0xff0f0000 0x4000>;
344 saradc: saradc@ff100000 {
345 compatible = "rockchip,saradc";
346 reg = <0xff100000 0x100>;
347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
348 #io-channel-cells = <1>;
349 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
350 clock-names = "saradc", "apb_pclk";
351 resets = <&cru SRST_SARADC>;
352 reset-names = "saradc-apb";
357 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
358 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
359 clock-names = "spiclk", "apb_pclk";
360 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
361 dma-names = "tx", "rx";
362 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
365 reg = <0xff110000 0x1000>;
366 #address-cells = <1>;
372 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
373 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
374 clock-names = "spiclk", "apb_pclk";
375 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
376 dma-names = "tx", "rx";
377 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
380 reg = <0xff120000 0x1000>;
381 #address-cells = <1>;
387 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
388 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
389 clock-names = "spiclk", "apb_pclk";
390 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
391 dma-names = "tx", "rx";
392 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
395 reg = <0xff130000 0x1000>;
396 #address-cells = <1>;
402 compatible = "rockchip,rk3288-i2c";
403 reg = <0xff650000 0x1000>;
404 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
405 #address-cells = <1>;
408 clocks = <&cru PCLK_I2C0>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c0_xfer>;
415 compatible = "rockchip,rk3288-i2c";
416 reg = <0xff140000 0x1000>;
417 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
421 clocks = <&cru PCLK_I2C1>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c1_xfer>;
428 compatible = "rockchip,rk3288-i2c";
429 reg = <0xff150000 0x1000>;
430 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
434 clocks = <&cru PCLK_I2C3>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c3_xfer>;
441 compatible = "rockchip,rk3288-i2c";
442 reg = <0xff160000 0x1000>;
443 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
447 clocks = <&cru PCLK_I2C4>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&i2c4_xfer>;
454 compatible = "rockchip,rk3288-i2c";
455 reg = <0xff170000 0x1000>;
456 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
457 #address-cells = <1>;
460 clocks = <&cru PCLK_I2C5>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&i2c5_xfer>;
466 uart0: serial@ff180000 {
467 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
468 reg = <0xff180000 0x100>;
469 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
473 clock-names = "baudclk", "apb_pclk";
474 pinctrl-names = "default";
475 pinctrl-0 = <&uart0_xfer>;
479 uart1: serial@ff190000 {
480 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
481 reg = <0xff190000 0x100>;
482 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
486 clock-names = "baudclk", "apb_pclk";
487 pinctrl-names = "default";
488 pinctrl-0 = <&uart1_xfer>;
492 uart2: serial@ff690000 {
493 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
494 reg = <0xff690000 0x100>;
495 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
499 clock-names = "baudclk", "apb_pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart2_xfer>;
505 uart3: serial@ff1b0000 {
506 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
507 reg = <0xff1b0000 0x100>;
508 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
512 clock-names = "baudclk", "apb_pclk";
513 pinctrl-names = "default";
514 pinctrl-0 = <&uart3_xfer>;
518 uart4: serial@ff1c0000 {
519 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
520 reg = <0xff1c0000 0x100>;
521 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
525 clock-names = "baudclk", "apb_pclk";
526 pinctrl-names = "default";
527 pinctrl-0 = <&uart4_xfer>;
532 reserve_thermal: reserve_thermal {
533 polling-delay-passive = <1000>; /* milliseconds */
534 polling-delay = <5000>; /* milliseconds */
536 thermal-sensors = <&tsadc 0>;
539 cpu_thermal: cpu_thermal {
540 polling-delay-passive = <250>; /* milliseconds */
541 polling-delay = <5000>; /* milliseconds */
543 thermal-sensors = <&tsadc 1>;
546 cpu_alert0: cpu_alert0 {
547 temperature = <70000>; /* millicelsius */
548 hysteresis = <2000>; /* millicelsius */
551 cpu_alert1: cpu_alert1 {
552 temperature = <80000>; /* millicelsius */
553 hysteresis = <2000>; /* millicelsius */
557 temperature = <90000>; /* millicelsius */
558 hysteresis = <2000>; /* millicelsius */
565 trip = <&cpu_alert0>;
567 <&cpu0 THERMAL_NO_LIMIT 6>;
570 trip = <&cpu_alert1>;
572 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
577 gpu_thermal: gpu_thermal {
578 polling-delay-passive = <250>; /* milliseconds */
579 polling-delay = <5000>; /* milliseconds */
581 thermal-sensors = <&tsadc 2>;
584 gpu_alert0: gpu_alert0 {
585 temperature = <80000>; /* millicelsius */
586 hysteresis = <2000>; /* millicelsius */
590 temperature = <90000>; /* millicelsius */
591 hysteresis = <2000>; /* millicelsius */
598 trip = <&gpu_alert0>;
600 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
606 tsadc: tsadc@ff280000 {
607 compatible = "rockchip,rk3288-tsadc";
608 reg = <0xff280000 0x100>;
609 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
611 clock-names = "tsadc", "apb_pclk";
612 resets = <&cru SRST_TSADC>;
613 reset-names = "tsadc-apb";
614 pinctrl-names = "init", "default", "sleep";
615 pinctrl-0 = <&otp_gpio>;
616 pinctrl-1 = <&otp_out>;
617 pinctrl-2 = <&otp_gpio>;
618 #thermal-sensor-cells = <1>;
619 rockchip,hw-tshut-temp = <95000>;
623 gmac: ethernet@ff290000 {
624 compatible = "rockchip,rk3288-gmac";
625 reg = <0xff290000 0x10000>;
626 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-names = "macirq", "eth_wake_irq";
629 rockchip,grf = <&grf>;
630 clocks = <&cru SCLK_MAC>,
631 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
632 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
633 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
634 clock-names = "stmmaceth",
635 "mac_clk_rx", "mac_clk_tx",
636 "clk_mac_ref", "clk_mac_refout",
637 "aclk_mac", "pclk_mac";
638 resets = <&cru SRST_MAC>;
639 reset-names = "stmmaceth";
643 usb_host0_ehci: usb@ff500000 {
644 compatible = "generic-ehci";
645 reg = <0xff500000 0x100>;
646 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&cru HCLK_USBHOST0>;
648 clock-names = "usbhost";
654 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
656 usb_host1: usb@ff540000 {
657 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
659 reg = <0xff540000 0x40000>;
660 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&cru HCLK_USBHOST1>;
665 phy-names = "usb2-phy";
669 usb_otg: usb@ff580000 {
670 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
672 reg = <0xff580000 0x40000>;
673 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&cru HCLK_OTG0>;
677 g-np-tx-fifo-size = <16>;
678 g-rx-fifo-size = <275>;
679 g-tx-fifo-size = <256 128 128 64 64 32>;
682 phy-names = "usb2-phy";
686 usb_hsic: usb@ff5c0000 {
687 compatible = "generic-ehci";
688 reg = <0xff5c0000 0x100>;
689 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cru HCLK_HSIC>;
691 clock-names = "usbhost";
696 compatible = "rockchip,rk3288-dmc", "syscon";
697 rockchip,cru = <&cru>;
698 rockchip,grf = <&grf>;
699 rockchip,pmu = <&pmu>;
700 rockchip,sgrf = <&sgrf>;
701 rockchip,noc = <&noc>;
702 reg = <0xff610000 0x3fc
706 rockchip,sram = <&ddr_sram>;
707 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
708 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
709 <&cru ARMCLK>, <&cru ACLK_DMAC1>;
710 clock-names = "pclk_ddrupctl0", "pclk_publ0",
711 "pclk_ddrupctl1", "pclk_publ1",
712 "arm_clk", "aclk_dmac1";
716 compatible = "rockchip,rk3288-i2c";
717 reg = <0xff660000 0x1000>;
718 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
719 #address-cells = <1>;
722 clocks = <&cru PCLK_I2C2>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&i2c2_xfer>;
729 compatible = "rockchip,rk3288-pwm";
730 reg = <0xff680000 0x10>;
732 pinctrl-names = "default";
733 pinctrl-0 = <&pwm0_pin>;
734 clocks = <&cru PCLK_PWM>;
740 compatible = "rockchip,rk3288-pwm";
741 reg = <0xff680010 0x10>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&pwm1_pin>;
745 clocks = <&cru PCLK_PWM>;
751 compatible = "rockchip,rk3288-pwm";
752 reg = <0xff680020 0x10>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&pwm2_pin>;
756 clocks = <&cru PCLK_PWM>;
762 compatible = "rockchip,rk3288-pwm";
763 reg = <0xff680030 0x10>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&pwm3_pin>;
767 clocks = <&cru PCLK_PWM>;
772 bus_intmem@ff700000 {
773 compatible = "mmio-sram";
774 reg = <0xff700000 0x18000>;
775 #address-cells = <1>;
777 ranges = <0 0xff700000 0x18000>;
779 compatible = "rockchip,rk3066-smp-sram";
782 ddr_sram: ddr-sram@1000 {
783 compatible = "rockchip,rk3288-ddr-sram";
784 reg = <0x1000 0x4000>;
789 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
790 reg = <0xff720000 0x1000>;
793 qos_gpu_r: qos@ffaa0000 {
794 compatible = "syscon";
795 reg = <0xffaa0000 0x20>;
798 qos_gpu_w: qos@ffaa0080 {
799 compatible = "syscon";
800 reg = <0xffaa0080 0x20>;
803 qos_vio1_vop: qos@ffad0000 {
804 compatible = "syscon";
805 reg = <0xffad0000 0x20>;
808 qos_vio1_isp_w0: qos@ffad0100 {
809 compatible = "syscon";
810 reg = <0xffad0100 0x20>;
813 qos_vio1_isp_w1: qos@ffad0180 {
814 compatible = "syscon";
815 reg = <0xffad0180 0x20>;
818 qos_vio0_vop: qos@ffad0400 {
819 compatible = "syscon";
820 reg = <0xffad0400 0x20>;
823 qos_vio0_vip: qos@ffad0480 {
824 compatible = "syscon";
825 reg = <0xffad0480 0x20>;
828 qos_vio0_iep: qos@ffad0500 {
829 compatible = "syscon";
830 reg = <0xffad0500 0x20>;
833 qos_vio2_rga_r: qos@ffad0800 {
834 compatible = "syscon";
835 reg = <0xffad0800 0x20>;
838 qos_vio2_rga_w: qos@ffad0880 {
839 compatible = "syscon";
840 reg = <0xffad0880 0x20>;
843 qos_vio1_isp_r: qos@ffad0900 {
844 compatible = "syscon";
845 reg = <0xffad0900 0x20>;
848 qos_video: qos@ffae0000 {
849 compatible = "syscon";
850 reg = <0xffae0000 0x20>;
853 qos_hevc_r: qos@ffaf0000 {
854 compatible = "syscon";
855 reg = <0xffaf0000 0x20>;
858 qos_hevc_w: qos@ffaf0080 {
859 compatible = "syscon";
860 reg = <0xffaf0080 0x20>;
863 pmu: power-management@ff730000 {
864 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
865 reg = <0xff730000 0x100>;
867 power: power-controller {
868 compatible = "rockchip,rk3288-power-controller";
869 #power-domain-cells = <1>;
870 #address-cells = <1>;
874 * Note: Although SCLK_* are the working clocks
875 * of device without including on the NOC, needed for
878 * The clocks on the which NOC:
879 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
880 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
881 * ACLK_RGA is on ACLK_RGA_NIU.
882 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
884 * Which clock are device clocks:
886 * *_IEP IEP:Image Enhancement Processor
887 * *_ISP ISP:Image Signal Processing
888 * *_VIP VIP:Video Input Processor
889 * *_VOP* VOP:Visual Output Processor
896 pd_vio@RK3288_PD_VIO {
897 reg = <RK3288_PD_VIO>;
898 clocks = <&cru ACLK_IEP>,
912 <&cru PCLK_EDP_CTRL>,
913 <&cru PCLK_HDMI_CTRL>,
914 <&cru PCLK_LVDS_PHY>,
915 <&cru PCLK_MIPI_CSI>,
916 <&cru PCLK_MIPI_DSI0>,
917 <&cru PCLK_MIPI_DSI1>,
923 pm_qos = <&qos_vio0_iep>,
935 * Note: The following 3 are HEVC(H.265) clocks,
936 * and on the ACLK_HEVC_NIU (NOC).
938 pd_hevc@RK3288_PD_HEVC {
939 reg = <RK3288_PD_HEVC>;
940 clocks = <&cru ACLK_HEVC>,
941 <&cru SCLK_HEVC_CABAC>,
942 <&cru SCLK_HEVC_CORE>;
943 pm_qos = <&qos_hevc_r>,
948 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
949 * (video endecoder & decoder) clocks that on the
950 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
952 pd_video@RK3288_PD_VIDEO {
953 reg = <RK3288_PD_VIDEO>;
954 clocks = <&cru ACLK_VCODEC>,
956 pm_qos = <&qos_video>;
960 * Note: ACLK_GPU is the GPU clock,
961 * and on the ACLK_GPU_NIU (NOC).
963 pd_gpu@RK3288_PD_GPU {
964 reg = <RK3288_PD_GPU>;
965 clocks = <&cru ACLK_GPU>;
966 pm_qos = <&qos_gpu_r>,
972 compatible = "syscon-reboot-mode";
974 mode-normal = <BOOT_NORMAL>;
975 mode-recovery = <BOOT_RECOVERY>;
976 mode-bootloader = <BOOT_FASTBOOT>;
977 mode-loader = <BOOT_BL_DOWNLOAD>;
978 mode-ums = <BOOT_UMS>;
982 sgrf: syscon@ff740000 {
983 compatible = "rockchip,rk3288-sgrf", "syscon";
984 reg = <0xff740000 0x1000>;
987 cru: clock-controller@ff760000 {
988 compatible = "rockchip,rk3288-cru";
989 reg = <0xff760000 0x1000>;
990 rockchip,grf = <&grf>;
993 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
994 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
995 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
996 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
997 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
999 assigned-clock-rates = <0>, <0>,
1000 <594000000>, <400000000>,
1001 <500000000>, <300000000>,
1002 <150000000>, <75000000>,
1003 <300000000>, <150000000>,
1005 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
1008 grf: syscon@ff770000 {
1009 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
1010 reg = <0xff770000 0x1000>;
1013 compatible = "rockchip,rk3288-dp-phy";
1014 clocks = <&cru SCLK_EDP_24M>;
1015 clock-names = "24m";
1017 status = "disabled";
1020 io_domains: io-domains {
1021 compatible = "rockchip,rk3288-io-voltage-domain";
1022 status = "disabled";
1026 compatible = "rockchip,rk3288-usb-phy";
1027 #address-cells = <1>;
1029 status = "disabled";
1031 usbphy0: usb-phy@320 {
1034 clocks = <&cru SCLK_OTGPHY0>;
1035 clock-names = "phyclk";
1037 resets = <&cru SRST_USBOTG_PHY>;
1038 reset-names = "phy-reset";
1041 usbphy1: usb-phy@334 {
1044 clocks = <&cru SCLK_OTGPHY1>;
1045 clock-names = "phyclk";
1049 usbphy2: usb-phy@348 {
1052 clocks = <&cru SCLK_OTGPHY2>;
1053 clock-names = "phyclk";
1055 resets = <&cru SRST_USBHOST1_PHY>;
1056 reset-names = "phy-reset";
1061 wdt: watchdog@ff800000 {
1062 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1063 reg = <0xff800000 0x100>;
1064 clocks = <&cru PCLK_WDT>;
1065 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1066 status = "disabled";
1069 spdif: sound@ff88b0000 {
1070 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1071 reg = <0xff8b0000 0x10000>;
1072 #sound-dai-cells = <0>;
1073 clock-names = "hclk", "mclk";
1074 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1075 dmas = <&dmac_bus_s 3>;
1077 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&spdif_tx>;
1080 rockchip,grf = <&grf>;
1081 status = "disabled";
1085 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1086 reg = <0xff890000 0x10000>;
1087 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1088 #address-cells = <1>;
1090 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1091 dma-names = "tx", "rx";
1092 clock-names = "i2s_hclk", "i2s_clk";
1093 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1094 pinctrl-names = "default";
1095 pinctrl-0 = <&i2s0_bus>;
1096 rockchip,playback-channels = <8>;
1097 rockchip,capture-channels = <2>;
1098 status = "disabled";
1101 cif_isp0: cif_isp@ff910000 {
1102 compatible = "rockchip,rk3288-cif-isp";
1103 rockchip,grf = <&grf>;
1104 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1105 reg-names = "register", "csihost-register";
1106 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1107 <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1108 <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1109 <&cru SCLK_MIPIDSI_24M>;
1110 clock-names = "aclk_isp", "hclk_isp",
1111 "sclk_isp", "sclk_isp_jpe",
1112 "pclk_mipi_csi", "pclk_isp_in",
1114 resets = <&cru SRST_ISP>;
1115 reset-names = "rst_isp";
1116 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1117 interrupt-names = "cif_isp10_irq";
1118 status = "disabled";
1122 compatible = "rockchip,rk3288-rga";
1123 reg = <0xff920000 0x180>;
1124 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1125 interrupt-names = "rga";
1126 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1127 clock-names = "aclk", "hclk", "sclk";
1128 power-domains = <&power RK3288_PD_VIO>;
1129 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1130 reset-names = "core", "axi", "ahb";
1132 status = "disabled";
1135 vopb: vop@ff930000 {
1136 compatible = "rockchip,rk3288-vop";
1137 reg = <0xff930000 0x19c>;
1138 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1140 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1141 power-domains = <&power RK3288_PD_VIO>;
1142 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1143 reset-names = "axi", "ahb", "dclk";
1144 iommus = <&vopb_mmu>;
1145 status = "disabled";
1148 #address-cells = <1>;
1151 vopb_out_hdmi: endpoint@0 {
1153 remote-endpoint = <&hdmi_in_vopb>;
1156 vopb_out_edp: endpoint@1 {
1158 remote-endpoint = <&edp_in_vopb>;
1161 vopb_out_mipi: endpoint@2 {
1163 remote-endpoint = <&mipi_in_vopb>;
1166 vopb_out_lvds: endpoint@3 {
1168 remote-endpoint = <&lvds_in_vopb>;
1173 vopb_mmu: iommu@ff930300 {
1174 compatible = "rockchip,iommu";
1175 reg = <0xff930300 0x100>;
1176 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "vopb_mmu";
1178 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1179 clock-names = "aclk", "hclk";
1180 power-domains = <&power RK3288_PD_VIO>;
1182 status = "disabled";
1185 vopl: vop@ff940000 {
1186 compatible = "rockchip,rk3288-vop";
1187 reg = <0xff940000 0x19c>;
1188 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1190 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1191 power-domains = <&power RK3288_PD_VIO>;
1192 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1193 reset-names = "axi", "ahb", "dclk";
1194 iommus = <&vopl_mmu>;
1195 status = "disabled";
1198 #address-cells = <1>;
1201 vopl_out_hdmi: endpoint@0 {
1203 remote-endpoint = <&hdmi_in_vopl>;
1206 vopl_out_edp: endpoint@1 {
1208 remote-endpoint = <&edp_in_vopl>;
1211 vopl_out_mipi: endpoint@2 {
1213 remote-endpoint = <&mipi_in_vopl>;
1216 vopl_out_lvds: endpoint@3 {
1218 remote-endpoint = <&lvds_in_vopl>;
1224 vopl_mmu: iommu@ff940300 {
1225 compatible = "rockchip,iommu";
1226 reg = <0xff940300 0x100>;
1227 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1228 interrupt-names = "vopl_mmu";
1229 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1230 clock-names = "aclk", "hclk";
1231 power-domains = <&power RK3288_PD_VIO>;
1233 status = "disabled";
1236 mipi_dsi: mipi@ff960000 {
1237 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1238 reg = <0xff960000 0x4000>;
1239 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1240 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1241 clock-names = "ref", "pclk";
1242 power-domains = <&power RK3288_PD_VIO>;
1243 rockchip,grf = <&grf>;
1244 #address-cells = <1>;
1246 status = "disabled";
1250 #address-cells = <1>;
1252 mipi_in_vopb: endpoint@0 {
1254 remote-endpoint = <&vopb_out_mipi>;
1256 mipi_in_vopl: endpoint@1 {
1258 remote-endpoint = <&vopl_out_mipi>;
1265 compatible = "rockchip,rk3288-dp";
1266 reg = <0xff970000 0x4000>;
1267 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1269 clock-names = "dp", "pclk";
1270 power-domains = <&power RK3288_PD_VIO>;
1273 resets = <&cru SRST_EDP>;
1275 rockchip,grf = <&grf>;
1276 status = "disabled";
1279 #address-cells = <1>;
1283 #address-cells = <1>;
1285 edp_in_vopb: endpoint@0 {
1287 remote-endpoint = <&vopb_out_edp>;
1289 edp_in_vopl: endpoint@1 {
1291 remote-endpoint = <&vopl_out_edp>;
1297 lvds: lvds@ff96c000 {
1298 compatible = "rockchip,rk3288-lvds";
1299 reg = <0xff96c000 0x4000>;
1300 clocks = <&cru PCLK_LVDS_PHY>;
1301 clock-names = "pclk_lvds";
1302 pinctrl-names = "default";
1303 pinctrl-0 = <&lcdc0_ctl>;
1304 power-domains = <&power RK3288_PD_VIO>;
1305 rockchip,grf = <&grf>;
1306 status = "disabled";
1309 #address-cells = <1>;
1315 #address-cells = <1>;
1318 lvds_in_vopb: endpoint@0 {
1320 remote-endpoint = <&vopb_out_lvds>;
1322 lvds_in_vopl: endpoint@1 {
1324 remote-endpoint = <&vopl_out_lvds>;
1330 hdmi: hdmi@ff980000 {
1331 compatible = "rockchip,rk3288-dw-hdmi";
1332 reg = <0xff980000 0x20000>;
1334 rockchip,grf = <&grf>;
1335 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1336 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1337 clock-names = "iahb", "isfr";
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&hdmi_ddc>;
1340 power-domains = <&power RK3288_PD_VIO>;
1341 status = "disabled";
1345 #address-cells = <1>;
1347 hdmi_in_vopb: endpoint@0 {
1349 remote-endpoint = <&vopb_out_hdmi>;
1351 hdmi_in_vopl: endpoint@1 {
1353 remote-endpoint = <&vopl_out_hdmi>;
1359 vpu: video-codec@ff9a0000 {
1360 compatible = "rockchip,rk3288-vpu";
1361 reg = <0xff9a0000 0x800>;
1362 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1364 interrupt-names = "vepu", "vdpu";
1365 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1366 clock-names = "aclk", "hclk";
1367 power-domains = <&power RK3288_PD_VIDEO>;
1368 iommus = <&vpu_mmu>;
1369 assigned-clocks = <&cru ACLK_VCODEC>;
1370 assigned-clock-rates = <400000000>;
1371 status = "disabled";
1374 vpu_service: vpu-service@ff9a0000 {
1375 compatible = "rockchip,vpu_service";
1376 reg = <0xff9a0000 0x800>;
1377 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1379 interrupt-names = "irq_enc", "irq_dec";
1380 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1381 clock-names = "aclk_vcodec", "hclk_vcodec";
1382 power-domains = <&power RK3288_PD_VIDEO>;
1383 rockchip,grf = <&grf>;
1384 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1385 reset-names = "video_a", "video_h";
1386 iommus = <&vpu_mmu>;
1387 iommu_enabled = <1>;
1389 status = "disabled";
1390 /* 0 means ion, 1 means drm */
1394 vpu_mmu: iommu@ff9a0800 {
1395 compatible = "rockchip,iommu";
1396 reg = <0xff9a0800 0x100>;
1397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1398 interrupt-names = "vpu_mmu";
1399 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1400 clock-names = "aclk", "hclk";
1401 power-domains = <&power RK3288_PD_VIDEO>;
1405 hevc_service: hevc-service@ff9c0000 {
1406 compatible = "rockchip,hevc_service";
1407 reg = <0xff9c0000 0x400>;
1408 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1409 interrupt-names = "irq_dec";
1410 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1411 <&cru SCLK_HEVC_CORE>,
1412 <&cru SCLK_HEVC_CABAC>;
1413 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1416 * The 4K hevc would also work well with 500/125/300/300,
1417 * no more err irq and reset request.
1419 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1420 <&cru SCLK_HEVC_CORE>,
1421 <&cru SCLK_HEVC_CABAC>;
1422 assigned-clock-rates = <400000000>, <100000000>,
1423 <300000000>, <300000000>;
1425 resets = <&cru SRST_HEVC>;
1426 reset-names = "video";
1427 power-domains = <&power RK3288_PD_HEVC>;
1428 rockchip,grf = <&grf>;
1430 iommus = <&hevc_mmu>;
1431 iommu_enabled = <1>;
1432 status = "disabled";
1433 /* 0 means ion, 1 means drm */
1437 hevc_mmu: iommu@ff9c0440 {
1438 compatible = "rockchip,iommu";
1439 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1440 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1441 interrupt-names = "hevc_mmu";
1442 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1443 <&cru SCLK_HEVC_CORE>,
1444 <&cru SCLK_HEVC_CABAC>;
1445 clock-names = "aclk", "hclk", "clk_core",
1447 power-domains = <&power RK3288_PD_HEVC>;
1452 compatible = "arm,malit764",
1456 reg = <0xffa30000 0x10000>;
1457 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1460 interrupt-names = "JOB", "MMU", "GPU";
1461 clocks = <&cru ACLK_GPU>;
1462 clock-names = "clk_mali";
1463 operating-points-v2 = <&gpu_opp_table>;
1464 #cooling-cells = <2>; /* min followed by max */
1465 power-domains = <&power RK3288_PD_GPU>;
1466 status = "disabled";
1469 downdifferential = <10>;
1471 gpu_power_model: power_model {
1472 compatible = "arm,mali-simple-power-model";
1475 static-power = <300>;
1476 dynamic-power = <396>;
1477 ts = <32000 4700 (-80) 2>;
1478 thermal-zone = "gpu_thermal";
1482 gpu_opp_table: opp-table1 {
1483 compatible = "operating-points-v2";
1486 opp-hz = /bits/ 64 <100000000>;
1487 opp-microvolt = <950000>;
1490 opp-hz = /bits/ 64 <200000000>;
1491 opp-microvolt = <950000>;
1494 opp-hz = /bits/ 64 <300000000>;
1495 opp-microvolt = <1000000>;
1498 opp-hz = /bits/ 64 <400000000>;
1499 opp-microvolt = <1100000>;
1502 opp-hz = /bits/ 64 <600000000>;
1503 opp-microvolt = <1250000>;
1507 noc: syscon@ffac0000 {
1508 compatible = "rockchip,rk3288-noc", "syscon";
1509 reg = <0xffac0000 0x2000>;
1512 efuse: efuse@ffb40000 {
1513 compatible = "rockchip,rockchip-efuse";
1514 reg = <0xffb40000 0x20>;
1515 #address-cells = <1>;
1517 clocks = <&cru PCLK_EFUSE256>;
1518 clock-names = "pclk_efuse";
1520 cpu_leakage: cpu_leakage@17 {
1525 gic: interrupt-controller@ffc01000 {
1526 compatible = "arm,gic-400";
1527 interrupt-controller;
1528 #interrupt-cells = <3>;
1529 #address-cells = <0>;
1531 reg = <0xffc01000 0x1000>,
1532 <0xffc02000 0x1000>,
1533 <0xffc04000 0x2000>,
1534 <0xffc06000 0x2000>;
1535 interrupts = <GIC_PPI 9 0xf04>;
1539 compatible = "rockchip,rk3288-pinctrl";
1540 rockchip,grf = <&grf>;
1541 rockchip,pmu = <&pmu>;
1542 #address-cells = <1>;
1546 gpio0: gpio0@ff750000 {
1547 compatible = "rockchip,gpio-bank";
1548 reg = <0xff750000 0x100>;
1549 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1550 clocks = <&cru PCLK_GPIO0>;
1555 interrupt-controller;
1556 #interrupt-cells = <2>;
1559 gpio1: gpio1@ff780000 {
1560 compatible = "rockchip,gpio-bank";
1561 reg = <0xff780000 0x100>;
1562 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1563 clocks = <&cru PCLK_GPIO1>;
1568 interrupt-controller;
1569 #interrupt-cells = <2>;
1572 gpio2: gpio2@ff790000 {
1573 compatible = "rockchip,gpio-bank";
1574 reg = <0xff790000 0x100>;
1575 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cru PCLK_GPIO2>;
1581 interrupt-controller;
1582 #interrupt-cells = <2>;
1585 gpio3: gpio3@ff7a0000 {
1586 compatible = "rockchip,gpio-bank";
1587 reg = <0xff7a0000 0x100>;
1588 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1589 clocks = <&cru PCLK_GPIO3>;
1594 interrupt-controller;
1595 #interrupt-cells = <2>;
1598 gpio4: gpio4@ff7b0000 {
1599 compatible = "rockchip,gpio-bank";
1600 reg = <0xff7b0000 0x100>;
1601 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1602 clocks = <&cru PCLK_GPIO4>;
1607 interrupt-controller;
1608 #interrupt-cells = <2>;
1611 gpio5: gpio5@ff7c0000 {
1612 compatible = "rockchip,gpio-bank";
1613 reg = <0xff7c0000 0x100>;
1614 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1615 clocks = <&cru PCLK_GPIO5>;
1620 interrupt-controller;
1621 #interrupt-cells = <2>;
1624 gpio6: gpio6@ff7d0000 {
1625 compatible = "rockchip,gpio-bank";
1626 reg = <0xff7d0000 0x100>;
1627 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1628 clocks = <&cru PCLK_GPIO6>;
1633 interrupt-controller;
1634 #interrupt-cells = <2>;
1637 gpio7: gpio7@ff7e0000 {
1638 compatible = "rockchip,gpio-bank";
1639 reg = <0xff7e0000 0x100>;
1640 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1641 clocks = <&cru PCLK_GPIO7>;
1646 interrupt-controller;
1647 #interrupt-cells = <2>;
1650 gpio8: gpio8@ff7f0000 {
1651 compatible = "rockchip,gpio-bank";
1652 reg = <0xff7f0000 0x100>;
1653 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1654 clocks = <&cru PCLK_GPIO8>;
1659 interrupt-controller;
1660 #interrupt-cells = <2>;
1664 hdmi_ddc: hdmi-ddc {
1665 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1666 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1670 pcfg_pull_up: pcfg-pull-up {
1674 pcfg_pull_down: pcfg-pull-down {
1678 pcfg_pull_none: pcfg-pull-none {
1682 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1684 drive-strength = <12>;
1688 global_pwroff: global-pwroff {
1689 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1692 ddrio_pwroff: ddrio-pwroff {
1693 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1696 ddr0_retention: ddr0-retention {
1697 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1700 ddr1_retention: ddr1-retention {
1701 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1707 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1712 i2c0_xfer: i2c0-xfer {
1713 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1714 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1719 i2c1_xfer: i2c1-xfer {
1720 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1721 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1726 i2c2_xfer: i2c2-xfer {
1727 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1728 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1733 i2c3_xfer: i2c3-xfer {
1734 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1735 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1740 i2c4_xfer: i2c4-xfer {
1741 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1742 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1747 i2c5_xfer: i2c5-xfer {
1748 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1749 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1754 i2s0_bus: i2s0-bus {
1755 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1756 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1757 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1758 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1759 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1760 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1765 lcdc0_ctl: lcdc0-ctl {
1766 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1767 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1768 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1769 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1774 sdmmc_clk: sdmmc-clk {
1775 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1778 sdmmc_cmd: sdmmc-cmd {
1779 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1782 sdmmc_cd: sdmcc-cd {
1783 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1786 sdmmc_bus1: sdmmc-bus1 {
1787 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1790 sdmmc_bus4: sdmmc-bus4 {
1791 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1792 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1793 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1794 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1799 sdio0_bus1: sdio0-bus1 {
1800 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1803 sdio0_bus4: sdio0-bus4 {
1804 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1805 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1806 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1807 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1810 sdio0_cmd: sdio0-cmd {
1811 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1814 sdio0_clk: sdio0-clk {
1815 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1818 sdio0_cd: sdio0-cd {
1819 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1822 sdio0_wp: sdio0-wp {
1823 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1826 sdio0_pwr: sdio0-pwr {
1827 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1830 sdio0_bkpwr: sdio0-bkpwr {
1831 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1834 sdio0_int: sdio0-int {
1835 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1840 sdio1_bus1: sdio1-bus1 {
1841 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1844 sdio1_bus4: sdio1-bus4 {
1845 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1846 <3 25 4 &pcfg_pull_up>,
1847 <3 26 4 &pcfg_pull_up>,
1848 <3 27 4 &pcfg_pull_up>;
1851 sdio1_cd: sdio1-cd {
1852 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1855 sdio1_wp: sdio1-wp {
1856 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1859 sdio1_bkpwr: sdio1-bkpwr {
1860 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1863 sdio1_int: sdio1-int {
1864 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1867 sdio1_cmd: sdio1-cmd {
1868 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1871 sdio1_clk: sdio1-clk {
1872 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1875 sdio1_pwr: sdio1-pwr {
1876 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1881 emmc_clk: emmc-clk {
1882 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1885 emmc_cmd: emmc-cmd {
1886 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1889 emmc_pwr: emmc-pwr {
1890 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1893 emmc_bus1: emmc-bus1 {
1894 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1897 emmc_bus4: emmc-bus4 {
1898 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1899 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1900 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1901 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1904 emmc_bus8: emmc-bus8 {
1905 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1906 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1907 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1908 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1909 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1910 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1911 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1912 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1917 spi0_clk: spi0-clk {
1918 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1920 spi0_cs0: spi0-cs0 {
1921 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1924 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1927 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1929 spi0_cs1: spi0-cs1 {
1930 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1934 spi1_clk: spi1-clk {
1935 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1937 spi1_cs0: spi1-cs0 {
1938 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1941 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1944 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1949 spi2_cs1: spi2-cs1 {
1950 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1952 spi2_clk: spi2-clk {
1953 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1955 spi2_cs0: spi2-cs0 {
1956 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1959 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1962 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1967 uart0_xfer: uart0-xfer {
1968 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1969 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1972 uart0_cts: uart0-cts {
1973 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1976 uart0_rts: uart0-rts {
1977 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1982 uart1_xfer: uart1-xfer {
1983 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1984 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1987 uart1_cts: uart1-cts {
1988 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1991 uart1_rts: uart1-rts {
1992 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1997 uart2_xfer: uart2-xfer {
1998 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1999 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2001 /* no rts / cts for uart2 */
2005 uart3_xfer: uart3-xfer {
2006 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2007 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2010 uart3_cts: uart3-cts {
2011 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2014 uart3_rts: uart3-rts {
2015 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2020 uart4_xfer: uart4-xfer {
2021 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2022 <5 13 3 &pcfg_pull_none>;
2025 uart4_cts: uart4-cts {
2026 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2029 uart4_rts: uart4-rts {
2030 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2035 otp_gpio: otp-gpio {
2036 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2040 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2045 pwm0_pin: pwm0-pin {
2046 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2051 pwm1_pin: pwm1-pin {
2052 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2057 pwm2_pin: pwm2-pin {
2058 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2063 pwm3_pin: pwm3-pin {
2064 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2069 rgmii_pins: rgmii-pins {
2070 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2071 <3 31 3 &pcfg_pull_none>,
2072 <3 26 3 &pcfg_pull_none>,
2073 <3 27 3 &pcfg_pull_none>,
2074 <3 28 3 &pcfg_pull_none_12ma>,
2075 <3 29 3 &pcfg_pull_none_12ma>,
2076 <3 24 3 &pcfg_pull_none_12ma>,
2077 <3 25 3 &pcfg_pull_none_12ma>,
2078 <4 0 3 &pcfg_pull_none>,
2079 <4 5 3 &pcfg_pull_none>,
2080 <4 6 3 &pcfg_pull_none>,
2081 <4 9 3 &pcfg_pull_none_12ma>,
2082 <4 4 3 &pcfg_pull_none_12ma>,
2083 <4 1 3 &pcfg_pull_none>,
2084 <4 3 3 &pcfg_pull_none>;
2087 rmii_pins: rmii-pins {
2088 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2089 <3 31 3 &pcfg_pull_none>,
2090 <3 28 3 &pcfg_pull_none>,
2091 <3 29 3 &pcfg_pull_none>,
2092 <4 0 3 &pcfg_pull_none>,
2093 <4 5 3 &pcfg_pull_none>,
2094 <4 4 3 &pcfg_pull_none>,
2095 <4 1 3 &pcfg_pull_none>,
2096 <4 2 3 &pcfg_pull_none>,
2097 <4 3 3 &pcfg_pull_none>;
2102 spdif_tx: spdif-tx {
2103 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2108 cif_dvp_d2d9: cif-dvp-d2d9 {
2109 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2110 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2111 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2112 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2113 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2114 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2115 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2116 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2117 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2118 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2119 <2 11 RK_FUNC_1 &pcfg_pull_none>;