arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/display/drm_mipi_dsi.h>
  50 #include "skeleton.dtsi"
  51
  52 / {
  53         compatible = "rockchip,rk3288";
  54
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 mshc0 = &emmc;
  66                 mshc1 = &sdmmc;
  67                 mshc2 = &sdio0;
  68                 mshc3 = &sdio1;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         arm-pmu {
  80                 compatible = "arm,cortex-a12-pmu";
  81                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  85                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  86         };
  87
  88         cpus {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 enable-method = "rockchip,rk3066-smp";
  92                 rockchip,pmu = <&pmu>;
  93
  94                 cpu0: cpu@500 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a12";
  97                         reg = <0x500>;
  98                         resets = <&cru SRST_CORE0>;
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         clocks = <&cru ARMCLK>;
 102                 };
 103                 cpu1: cpu@501 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a12";
 106                         reg = <0x501>;
 107                         resets = <&cru SRST_CORE1>;
 108                         operating-points-v2 = <&cpu0_opp_table>;
 109                 };
 110                 cpu2: cpu@502 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a12";
 113                         reg = <0x502>;
 114                         resets = <&cru SRST_CORE2>;
 115                         operating-points-v2 = <&cpu0_opp_table>;
 116                 };
 117                 cpu3: cpu@503 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a12";
 120                         reg = <0x503>;
 121                         resets = <&cru SRST_CORE3>;
 122                         operating-points-v2 = <&cpu0_opp_table>;
 123                 };
 124         };
 125
 126         cpu0_opp_table: opp_table0 {
 127                 compatible = "operating-points-v2";
 128                 opp-shared;
 129
 130                 opp@126000000 {
 131                         opp-hz = /bits/ 64 <126000000>;
 132                         opp-microvolt = <900000>;
 133                         clock-latency-ns = <40000>;
 134                 };
 135                 opp@216000000 {
 136                         opp-hz = /bits/ 64 <216000000>;
 137                         opp-microvolt = <900000>;
 138                         clock-latency-ns = <40000>;
 139                 };
 140                 opp@408000000 {
 141                         opp-hz = /bits/ 64 <408000000>;
 142                         opp-microvolt = <900000>;
 143                         clock-latency-ns = <40000>;
 144                 };
 145                 opp@600000000 {
 146                         opp-hz = /bits/ 64 <600000000>;
 147                         opp-microvolt = <900000>;
 148                         clock-latency-ns = <40000>;
 149                 };
 150                 opp@696000000 {
 151                         opp-hz = /bits/ 64 <696000000>;
 152                         opp-microvolt = <950000>;
 153                         clock-latency-ns = <40000>;
 154                 };
 155                 opp@816000000 {
 156                         opp-hz = /bits/ 64 <816000000>;
 157                         opp-microvolt = <1000000>;
 158                         clock-latency-ns = <40000>;
 159                         opp-suspend;
 160                 };
 161                 opp@1008000000 {
 162                         opp-hz = /bits/ 64 <1008000000>;
 163                         opp-microvolt = <1050000>;
 164                         clock-latency-ns = <40000>;
 165                 };
 166                 opp@1200000000 {
 167                         opp-hz = /bits/ 64 <1200000000>;
 168                         opp-microvolt = <1100000>;
 169                         clock-latency-ns = <40000>;
 170                 };
 171                 opp@1416000000 {
 172                         opp-hz = /bits/ 64 <1416000000>;
 173                         opp-microvolt = <1200000>;
 174                         clock-latency-ns = <40000>;
 175                 };
 176                 opp@1512000000 {
 177                         opp-hz = /bits/ 64 <1512000000>;
 178                         opp-microvolt = <1300000>;
 179                         clock-latency-ns = <40000>;
 180                 };
 181                 opp@1608000000 {
 182                         opp-hz = /bits/ 64 <1608000000>;
 183                         opp-microvolt = <1350000>;
 184                         clock-latency-ns = <40000>;
 185                 };
 186         };
 187
 188         cpu_avs: cpu-avs {
 189                 cluster0-avs {
 190                         cluster-id = <0>;
 191                         min-volt = <900000>; /* uV */
 192                         min-freq = <126000>; /* KHz */
 193                         leakage-adjust-volt = <
 194                         /*  mA        mA         uV */
 195                             0         254        0
 196                         >;
 197                         nvmem-cells = <&cpu_leakage>;
 198                         nvmem-cell-names = "cpu_leakage";
 199                 };
 200         };
 201
 202         amba {
 203                 compatible = "arm,amba-bus";
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges;
 207
 208                 dmac_peri: dma-controller@ff250000 {
 209                         compatible = "arm,pl330", "arm,primecell";
 210                         reg = <0xff250000 0x4000>;
 211                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 213                         #dma-cells = <1>;
 214                         arm,pl330-broken-no-flushp;
 215                         peripherals-req-type-burst;
 216                         clocks = <&cru ACLK_DMAC2>;
 217                         clock-names = "apb_pclk";
 218                 };
 219
 220                 dmac_bus_ns: dma-controller@ff600000 {
 221                         compatible = "arm,pl330", "arm,primecell";
 222                         reg = <0xff600000 0x4000>;
 223                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 225                         #dma-cells = <1>;
 226                         arm,pl330-broken-no-flushp;
 227                         peripherals-req-type-burst;
 228                         clocks = <&cru ACLK_DMAC1>;
 229                         clock-names = "apb_pclk";
 230                         status = "disabled";
 231                 };
 232
 233                 dmac_bus_s: dma-controller@ffb20000 {
 234                         compatible = "arm,pl330", "arm,primecell";
 235                         reg = <0xffb20000 0x4000>;
 236                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 238                         #dma-cells = <1>;
 239                         arm,pl330-broken-no-flushp;
 240                         peripherals-req-type-burst;
 241                         clocks = <&cru ACLK_DMAC1>;
 242                         clock-names = "apb_pclk";
 243                 };
 244         };
 245
 246         reserved-memory {
 247                 #address-cells = <1>;
 248                 #size-cells = <1>;
 249                 ranges;
 250
 251                 /*
 252                  * The rk3288 cannot use the memory area above 0xfe000000
 253                  * for dma operations for some reason. While there is
 254                  * probably a better solution available somewhere, we
 255                  * haven't found it yet and while devices with 2GB of ram
 256                  * are not affected, this issue prevents 4GB from booting.
 257                  * So to make these devices at least bootable, block
 258                  * this area for the time being until the real solution
 259                  * is found.
 260                  */
 261                 dma-unusable@fe000000 {
 262                         reg = <0xfe000000 0x1000000>;
 263                 };
 264         };
 265
 266         xin24m: oscillator {
 267                 compatible = "fixed-clock";
 268                 clock-frequency = <24000000>;
 269                 clock-output-names = "xin24m";
 270                 #clock-cells = <0>;
 271         };
 272
 273         timer {
 274                 compatible = "arm,armv7-timer";
 275                 arm,cpu-registers-not-fw-configured;
 276                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 277                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 278                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 279                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 280                 clock-frequency = <24000000>;
 281         };
 282
 283         timer: timer@ff810000 {
 284                 compatible = "rockchip,rk3288-timer";
 285                 reg = <0xff810000 0x20>;
 286                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 287                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 288                 clock-names = "timer", "pclk";
 289         };
 290
 291         display-subsystem {
 292                 compatible = "rockchip,display-subsystem";
 293                 ports = <&vopl_out>, <&vopb_out>;
 294         };
 295
 296         sdmmc: dwmmc@ff0c0000 {
 297                 compatible = "rockchip,rk3288-dw-mshc";
 298                 clock-freq-min-max = <400000 150000000>;
 299                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 300                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 301                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 302                 fifo-depth = <0x100>;
 303                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 304                 reg = <0xff0c0000 0x4000>;
 305                 status = "disabled";
 306         };
 307
 308         sdio0: dwmmc@ff0d0000 {
 309                 compatible = "rockchip,rk3288-dw-mshc";
 310                 clock-freq-min-max = <400000 150000000>;
 311                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 312                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 313                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 314                 fifo-depth = <0x100>;
 315                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 316                 reg = <0xff0d0000 0x4000>;
 317                 status = "disabled";
 318         };
 319
 320         sdio1: dwmmc@ff0e0000 {
 321                 compatible = "rockchip,rk3288-dw-mshc";
 322                 clock-freq-min-max = <400000 150000000>;
 323                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 324                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 325                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 326                 fifo-depth = <0x100>;
 327                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 328                 reg = <0xff0e0000 0x4000>;
 329                 status = "disabled";
 330         };
 331
 332         emmc: dwmmc@ff0f0000 {
 333                 compatible = "rockchip,rk3288-dw-mshc";
 334                 clock-freq-min-max = <400000 150000000>;
 335                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 336                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 337                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 338                 fifo-depth = <0x100>;
 339                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 340                 reg = <0xff0f0000 0x4000>;
 341                 status = "disabled";
 342                 supports-emmc;
 343         };
 344
 345         saradc: saradc@ff100000 {
 346                 compatible = "rockchip,saradc";
 347                 reg = <0xff100000 0x100>;
 348                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 349                 #io-channel-cells = <1>;
 350                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 351                 clock-names = "saradc", "apb_pclk";
 352                 resets = <&cru SRST_SARADC>;
 353                 reset-names = "saradc-apb";
 354                 status = "disabled";
 355         };
 356
 357         spi0: spi@ff110000 {
 358                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 359                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 360                 clock-names = "spiclk", "apb_pclk";
 361                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 362                 dma-names = "tx", "rx";
 363                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 366                 reg = <0xff110000 0x1000>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 status = "disabled";
 370         };
 371
 372         spi1: spi@ff120000 {
 373                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 374                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 377                 dma-names = "tx", "rx";
 378                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 381                 reg = <0xff120000 0x1000>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 status = "disabled";
 385         };
 386
 387         spi2: spi@ff130000 {
 388                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 389                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 390                 clock-names = "spiclk", "apb_pclk";
 391                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 392                 dma-names = "tx", "rx";
 393                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 396                 reg = <0xff130000 0x1000>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 status = "disabled";
 400         };
 401
 402         i2c0: i2c@ff650000 {
 403                 compatible = "rockchip,rk3288-i2c";
 404                 reg = <0xff650000 0x1000>;
 405                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C0>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c0_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         i2c1: i2c@ff140000 {
 416                 compatible = "rockchip,rk3288-i2c";
 417                 reg = <0xff140000 0x1000>;
 418                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 clock-names = "i2c";
 422                 clocks = <&cru PCLK_I2C1>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&i2c1_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         i2c3: i2c@ff150000 {
 429                 compatible = "rockchip,rk3288-i2c";
 430                 reg = <0xff150000 0x1000>;
 431                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 clock-names = "i2c";
 435                 clocks = <&cru PCLK_I2C3>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&i2c3_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         i2c4: i2c@ff160000 {
 442                 compatible = "rockchip,rk3288-i2c";
 443                 reg = <0xff160000 0x1000>;
 444                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clock-names = "i2c";
 448                 clocks = <&cru PCLK_I2C4>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&i2c4_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         i2c5: i2c@ff170000 {
 455                 compatible = "rockchip,rk3288-i2c";
 456                 reg = <0xff170000 0x1000>;
 457                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 458                 #address-cells = <1>;
 459                 #size-cells = <0>;
 460                 clock-names = "i2c";
 461                 clocks = <&cru PCLK_I2C5>;
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&i2c5_xfer>;
 464                 status = "disabled";
 465         };
 466
 467         uart0: serial@ff180000 {
 468                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 469                 reg = <0xff180000 0x100>;
 470                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 474                 clock-names = "baudclk", "apb_pclk";
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&uart0_xfer>;
 477                 status = "disabled";
 478         };
 479
 480         uart1: serial@ff190000 {
 481                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 482                 reg = <0xff190000 0x100>;
 483                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 484                 reg-shift = <2>;
 485                 reg-io-width = <4>;
 486                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 487                 clock-names = "baudclk", "apb_pclk";
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&uart1_xfer>;
 490                 status = "disabled";
 491         };
 492
 493         uart2: serial@ff690000 {
 494                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 495                 reg = <0xff690000 0x100>;
 496                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 497                 reg-shift = <2>;
 498                 reg-io-width = <4>;
 499                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 500                 clock-names = "baudclk", "apb_pclk";
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&uart2_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         uart3: serial@ff1b0000 {
 507                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 508                 reg = <0xff1b0000 0x100>;
 509                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 510                 reg-shift = <2>;
 511                 reg-io-width = <4>;
 512                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 513                 clock-names = "baudclk", "apb_pclk";
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&uart3_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         uart4: serial@ff1c0000 {
 520                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 521                 reg = <0xff1c0000 0x100>;
 522                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 523                 reg-shift = <2>;
 524                 reg-io-width = <4>;
 525                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 526                 clock-names = "baudclk", "apb_pclk";
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&uart4_xfer>;
 529                 status = "disabled";
 530         };
 531
 532         thermal-zones {
 533                 reserve_thermal: reserve_thermal {
 534                         polling-delay-passive = <1000>; /* milliseconds */
 535                         polling-delay = <5000>; /* milliseconds */
 536
 537                         thermal-sensors = <&tsadc 0>;
 538                 };
 539
 540                 cpu_thermal: cpu_thermal {
 541                         polling-delay-passive = <250>; /* milliseconds */
 542                         polling-delay = <5000>; /* milliseconds */
 543
 544                         thermal-sensors = <&tsadc 1>;
 545
 546                         trips {
 547                                 cpu_alert0: cpu_alert0 {
 548                                         temperature = <70000>; /* millicelsius */
 549                                         hysteresis = <2000>; /* millicelsius */
 550                                         type = "passive";
 551                                 };
 552                                 cpu_alert1: cpu_alert1 {
 553                                         temperature = <80000>; /* millicelsius */
 554                                         hysteresis = <2000>; /* millicelsius */
 555                                         type = "passive";
 556                                 };
 557                                 cpu_crit: cpu_crit {
 558                                         temperature = <90000>; /* millicelsius */
 559                                         hysteresis = <2000>; /* millicelsius */
 560                                         type = "critical";
 561                                 };
 562                         };
 563
 564                         cooling-maps {
 565                                 map0 {
 566                                         trip = <&cpu_alert0>;
 567                                         cooling-device =
 568                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 569                                 };
 570                                 map1 {
 571                                         trip = <&cpu_alert1>;
 572                                         cooling-device =
 573                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 574                                 };
 575                         };
 576                 };
 577
 578                 gpu_thermal: gpu_thermal {
 579                         polling-delay-passive = <250>; /* milliseconds */
 580                         polling-delay = <5000>; /* milliseconds */
 581
 582                         thermal-sensors = <&tsadc 2>;
 583
 584                         trips {
 585                                 gpu_alert0: gpu_alert0 {
 586                                         temperature = <80000>; /* millicelsius */
 587                                         hysteresis = <2000>; /* millicelsius */
 588                                         type = "passive";
 589                                 };
 590                                 gpu_crit: gpu_crit {
 591                                         temperature = <90000>; /* millicelsius */
 592                                         hysteresis = <2000>; /* millicelsius */
 593                                         type = "critical";
 594                                 };
 595                         };
 596
 597                         cooling-maps {
 598                                 map0 {
 599                                         trip = <&gpu_alert0>;
 600                                         cooling-device =
 601                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 602                                 };
 603                         };
 604                 };
 605         };
 606
 607         tsadc: tsadc@ff280000 {
 608                 compatible = "rockchip,rk3288-tsadc";
 609                 reg = <0xff280000 0x100>;
 610                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 611                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 612                 clock-names = "tsadc", "apb_pclk";
 613                 resets = <&cru SRST_TSADC>;
 614                 reset-names = "tsadc-apb";
 615                 pinctrl-names = "init", "default", "sleep";
 616                 pinctrl-0 = <&otp_gpio>;
 617                 pinctrl-1 = <&otp_out>;
 618                 pinctrl-2 = <&otp_gpio>;
 619                 #thermal-sensor-cells = <1>;
 620                 rockchip,hw-tshut-temp = <95000>;
 621                 status = "disabled";
 622         };
 623
 624         gmac: ethernet@ff290000 {
 625                 compatible = "rockchip,rk3288-gmac";
 626                 reg = <0xff290000 0x10000>;
 627                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 628                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 629                 interrupt-names = "macirq", "eth_wake_irq";
 630                 rockchip,grf = <&grf>;
 631                 clocks = <&cru SCLK_MAC>,
 632                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 633                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 634                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 635                 clock-names = "stmmaceth",
 636                         "mac_clk_rx", "mac_clk_tx",
 637                         "clk_mac_ref", "clk_mac_refout",
 638                         "aclk_mac", "pclk_mac";
 639                 resets = <&cru SRST_MAC>;
 640                 reset-names = "stmmaceth";
 641                 status = "disabled";
 642         };
 643
 644         usb_host0_ehci: usb@ff500000 {
 645                 compatible = "generic-ehci";
 646                 reg = <0xff500000 0x100>;
 647                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&cru HCLK_USBHOST0>;
 649                 clock-names = "usbhost";
 650                 phys = <&usbphy1>;
 651                 phy-names = "usb";
 652                 status = "disabled";
 653         };
 654
 655         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 656
 657         usb_host1: usb@ff540000 {
 658                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 659                                 "snps,dwc2";
 660                 reg = <0xff540000 0x40000>;
 661                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&cru HCLK_USBHOST1>;
 663                 clock-names = "otg";
 664                 dr_mode = "host";
 665                 phys = <&usbphy2>;
 666                 phy-names = "usb2-phy";
 667                 status = "disabled";
 668         };
 669
 670         usb_otg: usb@ff580000 {
 671                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 672                                 "snps,dwc2";
 673                 reg = <0xff580000 0x40000>;
 674                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 675                 clocks = <&cru HCLK_OTG0>;
 676                 clock-names = "otg";
 677                 dr_mode = "otg";
 678                 g-np-tx-fifo-size = <16>;
 679                 g-rx-fifo-size = <275>;
 680                 g-tx-fifo-size = <256 128 128 64 64 32>;
 681                 g-use-dma;
 682                 phys = <&usbphy0>;
 683                 phy-names = "usb2-phy";
 684                 status = "disabled";
 685         };
 686
 687         usb_hsic: usb@ff5c0000 {
 688                 compatible = "generic-ehci";
 689                 reg = <0xff5c0000 0x100>;
 690                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 691                 clocks = <&cru HCLK_HSIC>;
 692                 clock-names = "usbhost";
 693                 status = "disabled";
 694         };
 695
 696         dmc: dmc@ff610000 {
 697                 compatible = "rockchip,rk3288-dmc", "syscon";
 698                 rockchip,cru = <&cru>;
 699                 rockchip,grf = <&grf>;
 700                 rockchip,pmu = <&pmu>;
 701                 rockchip,sgrf = <&sgrf>;
 702                 rockchip,noc = <&noc>;
 703                 reg = <0xff610000 0x3fc
 704                        0xff620000 0x294
 705                        0xff630000 0x3fc
 706                        0xff640000 0x294>;
 707                 rockchip,sram = <&ddr_sram>;
 708                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 709                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 710                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 711                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 712                               "pclk_ddrupctl1", "pclk_publ1",
 713                               "arm_clk", "aclk_dmac1";
 714         };
 715
 716         i2c2: i2c@ff660000 {
 717                 compatible = "rockchip,rk3288-i2c";
 718                 reg = <0xff660000 0x1000>;
 719                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 720                 #address-cells = <1>;
 721                 #size-cells = <0>;
 722                 clock-names = "i2c";
 723                 clocks = <&cru PCLK_I2C2>;
 724                 pinctrl-names = "default";
 725                 pinctrl-0 = <&i2c2_xfer>;
 726                 status = "disabled";
 727         };
 728
 729         pwm0: pwm@ff680000 {
 730                 compatible = "rockchip,rk3288-pwm";
 731                 reg = <0xff680000 0x10>;
 732                 #pwm-cells = <3>;
 733                 pinctrl-names = "default";
 734                 pinctrl-0 = <&pwm0_pin>;
 735                 clocks = <&cru PCLK_PWM>;
 736                 clock-names = "pwm";
 737                 status = "disabled";
 738         };
 739
 740         pwm1: pwm@ff680010 {
 741                 compatible = "rockchip,rk3288-pwm";
 742                 reg = <0xff680010 0x10>;
 743                 #pwm-cells = <3>;
 744                 pinctrl-names = "default";
 745                 pinctrl-0 = <&pwm1_pin>;
 746                 clocks = <&cru PCLK_PWM>;
 747                 clock-names = "pwm";
 748                 status = "disabled";
 749         };
 750
 751         pwm2: pwm@ff680020 {
 752                 compatible = "rockchip,rk3288-pwm";
 753                 reg = <0xff680020 0x10>;
 754                 #pwm-cells = <3>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&pwm2_pin>;
 757                 clocks = <&cru PCLK_PWM>;
 758                 clock-names = "pwm";
 759                 status = "disabled";
 760         };
 761
 762         pwm3: pwm@ff680030 {
 763                 compatible = "rockchip,rk3288-pwm";
 764                 reg = <0xff680030 0x10>;
 765                 #pwm-cells = <2>;
 766                 pinctrl-names = "default";
 767                 pinctrl-0 = <&pwm3_pin>;
 768                 clocks = <&cru PCLK_PWM>;
 769                 clock-names = "pwm";
 770                 status = "disabled";
 771         };
 772
 773         bus_intmem@ff700000 {
 774                 compatible = "mmio-sram";
 775                 reg = <0xff700000 0x18000>;
 776                 #address-cells = <1>;
 777                 #size-cells = <1>;
 778                 ranges = <0 0xff700000 0x18000>;
 779                 smp-sram@0 {
 780                         compatible = "rockchip,rk3066-smp-sram";
 781                         reg = <0x00 0x10>;
 782                 };
 783                 ddr_sram: ddr-sram@1000 {
 784                         compatible = "rockchip,rk3288-ddr-sram";
 785                         reg = <0x1000 0x4000>;
 786                 };
 787         };
 788
 789         sram@ff720000 {
 790                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 791                 reg = <0xff720000 0x1000>;
 792         };
 793
 794         qos_gpu_r: qos@ffaa0000 {
 795                 compatible = "syscon";
 796                 reg = <0xffaa0000 0x20>;
 797         };
 798
 799         qos_gpu_w: qos@ffaa0080 {
 800                 compatible = "syscon";
 801                 reg = <0xffaa0080 0x20>;
 802         };
 803
 804         qos_vio1_vop: qos@ffad0000 {
 805                 compatible = "syscon";
 806                 reg = <0xffad0000 0x20>;
 807         };
 808
 809         qos_vio1_isp_w0: qos@ffad0100 {
 810                 compatible = "syscon";
 811                 reg = <0xffad0100 0x20>;
 812         };
 813
 814         qos_vio1_isp_w1: qos@ffad0180 {
 815                 compatible = "syscon";
 816                 reg = <0xffad0180 0x20>;
 817         };
 818
 819         qos_vio0_vop: qos@ffad0400 {
 820                 compatible = "syscon";
 821                 reg = <0xffad0400 0x20>;
 822         };
 823
 824         qos_vio0_vip: qos@ffad0480 {
 825                 compatible = "syscon";
 826                 reg = <0xffad0480 0x20>;
 827         };
 828
 829         qos_vio0_iep: qos@ffad0500 {
 830                 compatible = "syscon";
 831                 reg = <0xffad0500 0x20>;
 832         };
 833
 834         qos_vio2_rga_r: qos@ffad0800 {
 835                 compatible = "syscon";
 836                 reg = <0xffad0800 0x20>;
 837         };
 838
 839         qos_vio2_rga_w: qos@ffad0880 {
 840                 compatible = "syscon";
 841                 reg = <0xffad0880 0x20>;
 842         };
 843
 844         qos_vio1_isp_r: qos@ffad0900 {
 845                 compatible = "syscon";
 846                 reg = <0xffad0900 0x20>;
 847         };
 848
 849         qos_video: qos@ffae0000 {
 850                 compatible = "syscon";
 851                 reg = <0xffae0000 0x20>;
 852         };
 853
 854         qos_hevc_r: qos@ffaf0000 {
 855                 compatible = "syscon";
 856                 reg = <0xffaf0000 0x20>;
 857         };
 858
 859         qos_hevc_w: qos@ffaf0080 {
 860                 compatible = "syscon";
 861                 reg = <0xffaf0080 0x20>;
 862         };
 863
 864         pmu: power-management@ff730000 {
 865                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 866                 reg = <0xff730000 0x100>;
 867
 868                 power: power-controller {
 869                         compatible = "rockchip,rk3288-power-controller";
 870                         #power-domain-cells = <1>;
 871                         #address-cells = <1>;
 872                         #size-cells = <0>;
 873
 874                         /*
 875                          * Note: Although SCLK_* are the working clocks
 876                          * of device without including on the NOC, needed for
 877                          * synchronous reset.
 878                          *
 879                          * The clocks on the which NOC:
 880                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 881                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 882                          * ACLK_RGA is on ACLK_RGA_NIU.
 883                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 884                          *
 885                          * Which clock are device clocks:
 886                          *      clocks          devices
 887                          *      *_IEP           IEP:Image Enhancement Processor
 888                          *      *_ISP           ISP:Image Signal Processing
 889                          *      *_VIP           VIP:Video Input Processor
 890                          *      *_VOP*          VOP:Visual Output Processor
 891                          *      *_RGA           RGA
 892                          *      *_EDP*          EDP
 893                          *      *_LVDS_*        LVDS
 894                          *      *_HDMI          HDMI
 895                          *      *_MIPI_*        MIPI
 896                          */
 897                         pd_vio@RK3288_PD_VIO {
 898                                 reg = <RK3288_PD_VIO>;
 899                                 clocks = <&cru ACLK_IEP>,
 900                                          <&cru ACLK_ISP>,
 901                                          <&cru ACLK_RGA>,
 902                                          <&cru ACLK_VIP>,
 903                                          <&cru ACLK_VOP0>,
 904                                          <&cru ACLK_VOP1>,
 905                                          <&cru DCLK_VOP0>,
 906                                          <&cru DCLK_VOP1>,
 907                                          <&cru HCLK_IEP>,
 908                                          <&cru HCLK_ISP>,
 909                                          <&cru HCLK_RGA>,
 910                                          <&cru HCLK_VIP>,
 911                                          <&cru HCLK_VOP0>,
 912                                          <&cru HCLK_VOP1>,
 913                                          <&cru PCLK_EDP_CTRL>,
 914                                          <&cru PCLK_HDMI_CTRL>,
 915                                          <&cru PCLK_LVDS_PHY>,
 916                                          <&cru PCLK_MIPI_CSI>,
 917                                          <&cru PCLK_MIPI_DSI0>,
 918                                          <&cru PCLK_MIPI_DSI1>,
 919                                          <&cru SCLK_EDP_24M>,
 920                                          <&cru SCLK_EDP>,
 921                                          <&cru SCLK_ISP_JPE>,
 922                                          <&cru SCLK_ISP>,
 923                                          <&cru SCLK_RGA>;
 924                                 pm_qos = <&qos_vio0_iep>,
 925                                          <&qos_vio1_vop>,
 926                                          <&qos_vio1_isp_w0>,
 927                                          <&qos_vio1_isp_w1>,
 928                                          <&qos_vio0_vop>,
 929                                          <&qos_vio0_vip>,
 930                                          <&qos_vio2_rga_r>,
 931                                          <&qos_vio2_rga_w>,
 932                                          <&qos_vio1_isp_r>;
 933                         };
 934
 935                         /*
 936                          * Note: The following 3 are HEVC(H.265) clocks,
 937                          * and on the ACLK_HEVC_NIU (NOC).
 938                          */
 939                         pd_hevc@RK3288_PD_HEVC {
 940                                 reg = <RK3288_PD_HEVC>;
 941                                 clocks = <&cru ACLK_HEVC>,
 942                                          <&cru SCLK_HEVC_CABAC>,
 943                                          <&cru SCLK_HEVC_CORE>;
 944                                 pm_qos = <&qos_hevc_r>,
 945                                          <&qos_hevc_w>;
 946                         };
 947
 948                         /*
 949                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 950                          * (video endecoder & decoder) clocks that on the
 951                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 952                          */
 953                         pd_video@RK3288_PD_VIDEO {
 954                                 reg = <RK3288_PD_VIDEO>;
 955                                 clocks = <&cru ACLK_VCODEC>,
 956                                          <&cru HCLK_VCODEC>;
 957                                 pm_qos = <&qos_video>;
 958                         };
 959
 960                         /*
 961                          * Note: ACLK_GPU is the GPU clock,
 962                          * and on the ACLK_GPU_NIU (NOC).
 963                          */
 964                         pd_gpu@RK3288_PD_GPU {
 965                                 reg = <RK3288_PD_GPU>;
 966                                 clocks = <&cru ACLK_GPU>;
 967                                 pm_qos = <&qos_gpu_r>,
 968                                          <&qos_gpu_w>;
 969                         };
 970                 };
 971
 972                 reboot-mode {
 973                         compatible = "syscon-reboot-mode";
 974                         offset = <0x94>;
 975                         mode-normal = <BOOT_NORMAL>;
 976                         mode-recovery = <BOOT_RECOVERY>;
 977                         mode-bootloader = <BOOT_FASTBOOT>;
 978                         mode-loader = <BOOT_BL_DOWNLOAD>;
 979                         mode-ums = <BOOT_UMS>;
 980                 };
 981         };
 982
 983         sgrf: syscon@ff740000 {
 984                 compatible = "rockchip,rk3288-sgrf", "syscon";
 985                 reg = <0xff740000 0x1000>;
 986         };
 987
 988         cru: clock-controller@ff760000 {
 989                 compatible = "rockchip,rk3288-cru";
 990                 reg = <0xff760000 0x1000>;
 991                 rockchip,grf = <&grf>;
 992                 #clock-cells = <1>;
 993                 #reset-cells = <1>;
 994                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 995                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 996                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 997                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 998                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 999                                   <&cru PCLK_PERI>;
1000                 assigned-clock-rates = <0>, <0>,
1001                                        <594000000>, <400000000>,
1002                                        <500000000>, <300000000>,
1003                                        <150000000>, <75000000>,
1004                                        <300000000>, <150000000>,
1005                                        <75000000>;
1006                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
1007         };
1008
1009         grf: syscon@ff770000 {
1010                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
1011                 reg = <0xff770000 0x1000>;
1012
1013                 edp_phy: edp-phy {
1014                         compatible = "rockchip,rk3288-dp-phy";
1015                         clocks = <&cru SCLK_EDP_24M>;
1016                         clock-names = "24m";
1017                         #phy-cells = <0>;
1018                         status = "disabled";
1019                 };
1020
1021                 io_domains: io-domains {
1022                         compatible = "rockchip,rk3288-io-voltage-domain";
1023                         status = "disabled";
1024                 };
1025
1026                 usbphy: usbphy {
1027                         compatible = "rockchip,rk3288-usb-phy";
1028                         #address-cells = <1>;
1029                         #size-cells = <0>;
1030                         status = "disabled";
1031
1032                         usbphy0: usb-phy@320 {
1033                                 #phy-cells = <0>;
1034                                 reg = <0x320>;
1035                                 clocks = <&cru SCLK_OTGPHY0>;
1036                                 clock-names = "phyclk";
1037                                 #clock-cells = <0>;
1038                                 resets = <&cru SRST_USBOTG_PHY>;
1039                                 reset-names = "phy-reset";
1040                         };
1041
1042                         usbphy1: usb-phy@334 {
1043                                 #phy-cells = <0>;
1044                                 reg = <0x334>;
1045                                 clocks = <&cru SCLK_OTGPHY1>;
1046                                 clock-names = "phyclk";
1047                                 #clock-cells = <0>;
1048                         };
1049
1050                         usbphy2: usb-phy@348 {
1051                                 #phy-cells = <0>;
1052                                 reg = <0x348>;
1053                                 clocks = <&cru SCLK_OTGPHY2>;
1054                                 clock-names = "phyclk";
1055                                 #clock-cells = <0>;
1056                                 resets = <&cru SRST_USBHOST1_PHY>;
1057                                 reset-names = "phy-reset";
1058                         };
1059                 };
1060         };
1061
1062         wdt: watchdog@ff800000 {
1063                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1064                 reg = <0xff800000 0x100>;
1065                 clocks = <&cru PCLK_WDT>;
1066                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1067                 status = "disabled";
1068         };
1069
1070         spdif: sound@ff88b0000 {
1071                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1072                 reg = <0xff8b0000 0x10000>;
1073                 #sound-dai-cells = <0>;
1074                 clock-names = "hclk", "mclk";
1075                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1076                 dmas = <&dmac_bus_s 3>;
1077                 dma-names = "tx";
1078                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1079                 pinctrl-names = "default";
1080                 pinctrl-0 = <&spdif_tx>;
1081                 rockchip,grf = <&grf>;
1082                 status = "disabled";
1083         };
1084
1085         i2s: i2s@ff890000 {
1086                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1087                 reg = <0xff890000 0x10000>;
1088                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1089                 #address-cells = <1>;
1090                 #size-cells = <0>;
1091                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1092                 dma-names = "tx", "rx";
1093                 clock-names = "i2s_hclk", "i2s_clk";
1094                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1095                 pinctrl-names = "default";
1096                 pinctrl-0 = <&i2s0_bus>;
1097                 rockchip,playback-channels = <8>;
1098                 rockchip,capture-channels = <2>;
1099                 status = "disabled";
1100         };
1101
1102         cif_isp0: cif_isp@ff910000 {
1103                 compatible = "rockchip,rk3288-cif-isp";
1104                 rockchip,grf = <&grf>;
1105                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1106                 reg-names = "register", "csihost-register";
1107                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1108                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1109                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1110                         <&cru SCLK_MIPIDSI_24M>;
1111                 clock-names = "aclk_isp", "hclk_isp",
1112                         "sclk_isp", "sclk_isp_jpe",
1113                         "pclk_mipi_csi", "pclk_isp_in",
1114                         "sclk_mipidsi_24m";
1115                 resets = <&cru SRST_ISP>;
1116                 reset-names = "rst_isp";
1117                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1118                 interrupt-names = "cif_isp10_irq";
1119                 status = "disabled";
1120         };
1121
1122         rga: rga@ff920000 {
1123                 compatible = "rockchip,rk3288-rga";
1124                 reg = <0xff920000 0x180>;
1125                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1126                 interrupt-names = "rga";
1127                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1128                 clock-names = "aclk", "hclk", "sclk";
1129                 power-domains = <&power RK3288_PD_VIO>;
1130                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1131                 reset-names = "core", "axi", "ahb";
1132                 dma-coherent;
1133                 status = "disabled";
1134         };
1135
1136         vopb: vop@ff930000 {
1137                 compatible = "rockchip,rk3288-vop";
1138                 reg = <0xff930000 0x19c>;
1139                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1140                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1141                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1142                 power-domains = <&power RK3288_PD_VIO>;
1143                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1144                 reset-names = "axi", "ahb", "dclk";
1145                 iommus = <&vopb_mmu>;
1146                 status = "disabled";
1147
1148                 vopb_out: port {
1149                         #address-cells = <1>;
1150                         #size-cells = <0>;
1151
1152                         vopb_out_hdmi: endpoint@0 {
1153                                 reg = <0>;
1154                                 remote-endpoint = <&hdmi_in_vopb>;
1155                         };
1156
1157                         vopb_out_edp: endpoint@1 {
1158                                 reg = <1>;
1159                                 remote-endpoint = <&edp_in_vopb>;
1160                         };
1161
1162                         vopb_out_mipi: endpoint@2 {
1163                                 reg = <2>;
1164                                 remote-endpoint = <&mipi_in_vopb>;
1165                         };
1166
1167                         vopb_out_lvds: endpoint@3 {
1168                                 reg = <3>;
1169                                 remote-endpoint = <&lvds_in_vopb>;
1170                         };
1171                 };
1172         };
1173
1174         vopb_mmu: iommu@ff930300 {
1175                 compatible = "rockchip,iommu";
1176                 reg = <0xff930300 0x100>;
1177                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1178                 interrupt-names = "vopb_mmu";
1179                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1180                 clock-names = "aclk", "hclk";
1181                 power-domains = <&power RK3288_PD_VIO>;
1182                 #iommu-cells = <0>;
1183                 status = "disabled";
1184         };
1185
1186         vopl: vop@ff940000 {
1187                 compatible = "rockchip,rk3288-vop";
1188                 reg = <0xff940000 0x19c>;
1189                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1190                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1191                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1192                 power-domains = <&power RK3288_PD_VIO>;
1193                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1194                 reset-names = "axi", "ahb", "dclk";
1195                 iommus = <&vopl_mmu>;
1196                 status = "disabled";
1197
1198                 vopl_out: port {
1199                         #address-cells = <1>;
1200                         #size-cells = <0>;
1201
1202                         vopl_out_hdmi: endpoint@0 {
1203                                 reg = <0>;
1204                                 remote-endpoint = <&hdmi_in_vopl>;
1205                         };
1206
1207                         vopl_out_edp: endpoint@1 {
1208                                 reg = <1>;
1209                                 remote-endpoint = <&edp_in_vopl>;
1210                         };
1211
1212                         vopl_out_mipi: endpoint@2 {
1213                                 reg = <2>;
1214                                 remote-endpoint = <&mipi_in_vopl>;
1215                         };
1216
1217                         vopl_out_lvds: endpoint@3 {
1218                                 reg = <3>;
1219                                 remote-endpoint = <&lvds_in_vopl>;
1220                         };
1221
1222                 };
1223         };
1224
1225         vopl_mmu: iommu@ff940300 {
1226                 compatible = "rockchip,iommu";
1227                 reg = <0xff940300 0x100>;
1228                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1229                 interrupt-names = "vopl_mmu";
1230                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1231                 clock-names = "aclk", "hclk";
1232                 power-domains = <&power RK3288_PD_VIO>;
1233                 #iommu-cells = <0>;
1234                 status = "disabled";
1235         };
1236
1237         mipi_dsi: mipi@ff960000 {
1238                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1239                 reg = <0xff960000 0x4000>;
1240                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1241                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1242                 clock-names = "ref", "pclk";
1243                 power-domains = <&power RK3288_PD_VIO>;
1244                 rockchip,grf = <&grf>;
1245                 #address-cells = <1>;
1246                 #size-cells = <0>;
1247                 status = "disabled";
1248
1249                 ports {
1250                         mipi_in: port {
1251                                 #address-cells = <1>;
1252                                 #size-cells = <0>;
1253                                 mipi_in_vopb: endpoint@0 {
1254                                         reg = <0>;
1255                                         remote-endpoint = <&vopb_out_mipi>;
1256                                 };
1257                                 mipi_in_vopl: endpoint@1 {
1258                                         reg = <1>;
1259                                         remote-endpoint = <&vopl_out_mipi>;
1260                                 };
1261                         };
1262                 };
1263         };
1264
1265         edp: dp@ff970000 {
1266                 compatible = "rockchip,rk3288-dp";
1267                 reg = <0xff970000 0x4000>;
1268                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1269                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1270                 clock-names = "dp", "pclk";
1271                 power-domains = <&power RK3288_PD_VIO>;
1272                 phys = <&edp_phy>;
1273                 phy-names = "dp";
1274                 resets = <&cru SRST_EDP>;
1275                 reset-names = "dp";
1276                 rockchip,grf = <&grf>;
1277                 status = "disabled";
1278
1279                 ports {
1280                         #address-cells = <1>;
1281                         #size-cells = <0>;
1282                         edp_in: port@0 {
1283                                 reg = <0>;
1284                                 #address-cells = <1>;
1285                                 #size-cells = <0>;
1286                                 edp_in_vopb: endpoint@0 {
1287                                         reg = <0>;
1288                                         remote-endpoint = <&vopb_out_edp>;
1289                                 };
1290                                 edp_in_vopl: endpoint@1 {
1291                                         reg = <1>;
1292                                         remote-endpoint = <&vopl_out_edp>;
1293                                 };
1294                         };
1295                 };
1296         };
1297
1298         lvds: lvds@ff96c000 {
1299                 compatible = "rockchip,rk3288-lvds";
1300                 reg = <0xff96c000 0x4000>;
1301                 clocks = <&cru PCLK_LVDS_PHY>;
1302                 clock-names = "pclk_lvds";
1303                 pinctrl-names = "default";
1304                 pinctrl-0 = <&lcdc0_ctl>;
1305                 power-domains = <&power RK3288_PD_VIO>;
1306                 rockchip,grf = <&grf>;
1307                 status = "disabled";
1308
1309                 ports {
1310                         #address-cells = <1>;
1311                         #size-cells = <0>;
1312
1313                         lvds_in: port@0 {
1314                                 reg = <0>;
1315
1316                                 #address-cells = <1>;
1317                                 #size-cells = <0>;
1318
1319                                 lvds_in_vopb: endpoint@0 {
1320                                         reg = <0>;
1321                                         remote-endpoint = <&vopb_out_lvds>;
1322                                 };
1323                                 lvds_in_vopl: endpoint@1 {
1324                                         reg = <1>;
1325                                         remote-endpoint = <&vopl_out_lvds>;
1326                                 };
1327                         };
1328                 };
1329         };
1330
1331         hdmi: hdmi@ff980000 {
1332                 compatible = "rockchip,rk3288-dw-hdmi";
1333                 reg = <0xff980000 0x20000>;
1334                 reg-io-width = <4>;
1335                 rockchip,grf = <&grf>;
1336                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1337                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1338                 clock-names = "iahb", "isfr";
1339                 pinctrl-names = "default";
1340                 pinctrl-0 = <&hdmi_ddc>;
1341                 power-domains = <&power RK3288_PD_VIO>;
1342                 status = "disabled";
1343
1344                 ports {
1345                         hdmi_in: port {
1346                                 #address-cells = <1>;
1347                                 #size-cells = <0>;
1348                                 hdmi_in_vopb: endpoint@0 {
1349                                         reg = <0>;
1350                                         remote-endpoint = <&vopb_out_hdmi>;
1351                                 };
1352                                 hdmi_in_vopl: endpoint@1 {
1353                                         reg = <1>;
1354                                         remote-endpoint = <&vopl_out_hdmi>;
1355                                 };
1356                         };
1357                 };
1358         };
1359
1360         vpu: video-codec@ff9a0000 {
1361                 compatible = "rockchip,rk3288-vpu";
1362                 reg = <0xff9a0000 0x800>;
1363                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1364                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1365                 interrupt-names = "vepu", "vdpu";
1366                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1367                 clock-names = "aclk", "hclk";
1368                 power-domains = <&power RK3288_PD_VIDEO>;
1369                 iommus = <&vpu_mmu>;
1370                 assigned-clocks = <&cru ACLK_VCODEC>;
1371                 assigned-clock-rates = <400000000>;
1372                 status = "disabled";
1373         };
1374
1375         vpu_service: vpu-service@ff9a0000 {
1376                 compatible = "rockchip,vpu_service";
1377                 reg = <0xff9a0000 0x800>;
1378                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1379                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1380                 interrupt-names = "irq_enc", "irq_dec";
1381                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1382                 clock-names = "aclk_vcodec", "hclk_vcodec";
1383                 power-domains = <&power RK3288_PD_VIDEO>;
1384                 rockchip,grf = <&grf>;
1385                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1386                 reset-names = "video_a", "video_h";
1387                 iommus = <&vpu_mmu>;
1388                 iommu_enabled = <1>;
1389                 dev_mode = <0>;
1390                 status = "disabled";
1391                 /* 0 means ion, 1 means drm */
1392                 allocator = <1>;
1393         };
1394
1395         vpu_mmu: iommu@ff9a0800 {
1396                 compatible = "rockchip,iommu";
1397                 reg = <0xff9a0800 0x100>;
1398                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1399                 interrupt-names = "vpu_mmu";
1400                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1401                 clock-names = "aclk", "hclk";
1402                 power-domains = <&power RK3288_PD_VIDEO>;
1403                 #iommu-cells = <0>;
1404         };
1405
1406         hevc_service: hevc-service@ff9c0000 {
1407                 compatible = "rockchip,hevc_service";
1408                 reg = <0xff9c0000 0x400>;
1409                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1410                 interrupt-names = "irq_dec";
1411                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1412                         <&cru SCLK_HEVC_CORE>,
1413                         <&cru SCLK_HEVC_CABAC>;
1414                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1415                         "clk_cabac";
1416                 /*
1417                  * The 4K hevc would also work well with 500/125/300/300,
1418                  * no more err irq and reset request.
1419                  */
1420                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1421                                   <&cru SCLK_HEVC_CORE>,
1422                                   <&cru SCLK_HEVC_CABAC>;
1423                 assigned-clock-rates = <400000000>, <100000000>,
1424                                        <300000000>, <300000000>;
1425
1426                 resets = <&cru SRST_HEVC>;
1427                 reset-names = "video";
1428                 power-domains = <&power RK3288_PD_HEVC>;
1429                 rockchip,grf = <&grf>;
1430                 dev_mode = <1>;
1431                 iommus = <&hevc_mmu>;
1432                 iommu_enabled = <1>;
1433                 status = "disabled";
1434                 /* 0 means ion, 1 means drm */
1435                 allocator = <1>;
1436         };
1437
1438         hevc_mmu: iommu@ff9c0440 {
1439                 compatible = "rockchip,iommu";
1440                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1441                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1442                 interrupt-names = "hevc_mmu";
1443                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1444                         <&cru SCLK_HEVC_CORE>,
1445                         <&cru SCLK_HEVC_CABAC>;
1446                 clock-names = "aclk", "hclk", "clk_core",
1447                         "clk_cabac";
1448                 power-domains = <&power RK3288_PD_HEVC>;
1449                 #iommu-cells = <0>;
1450         };
1451
1452         gpu: gpu@ffa30000 {
1453                 compatible = "arm,malit764",
1454                              "arm,malit76x",
1455                              "arm,malit7xx",
1456                              "arm,mali-midgard";
1457                 reg = <0xffa30000 0x10000>;
1458                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1459                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1460                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1461                 interrupt-names = "JOB", "MMU", "GPU";
1462                 clocks = <&cru ACLK_GPU>;
1463                 clock-names = "clk_mali";
1464                 operating-points-v2 = <&gpu_opp_table>;
1465                 #cooling-cells = <2>; /* min followed by max */
1466                 power-domains = <&power RK3288_PD_GPU>;
1467                 status = "disabled";
1468
1469                 upthreshold = <75>;
1470                 downdifferential = <10>;
1471
1472                 gpu_power_model: power_model {
1473                         compatible = "arm,mali-simple-power-model";
1474                         voltage = <950>;
1475                         frequency = <500>;
1476                         static-power = <300>;
1477                         dynamic-power = <396>;
1478                         ts = <32000 4700 (-80) 2>;
1479                         thermal-zone = "gpu_thermal";
1480                 };
1481         };
1482
1483         gpu_opp_table: opp-table1 {
1484                 compatible = "operating-points-v2";
1485
1486                 opp@100000000 {
1487                         opp-hz = /bits/ 64 <100000000>;
1488                         opp-microvolt = <950000>;
1489                 };
1490                 opp@200000000 {
1491                         opp-hz = /bits/ 64 <200000000>;
1492                         opp-microvolt = <950000>;
1493                 };
1494                 opp@300000000 {
1495                         opp-hz = /bits/ 64 <300000000>;
1496                         opp-microvolt = <1000000>;
1497                 };
1498                 opp@400000000 {
1499                         opp-hz = /bits/ 64 <400000000>;
1500                         opp-microvolt = <1100000>;
1501                 };
1502                 opp@600000000 {
1503                         opp-hz = /bits/ 64 <600000000>;
1504                         opp-microvolt = <1250000>;
1505                 };
1506         };
1507
1508         noc: syscon@ffac0000 {
1509                 compatible = "rockchip,rk3288-noc", "syscon";
1510                 reg = <0xffac0000 0x2000>;
1511         };
1512
1513         efuse: efuse@ffb40000 {
1514                 compatible = "rockchip,rockchip-efuse";
1515                 reg = <0xffb40000 0x20>;
1516                 #address-cells = <1>;
1517                 #size-cells = <1>;
1518                 clocks = <&cru PCLK_EFUSE256>;
1519                 clock-names = "pclk_efuse";
1520
1521                 cpu_leakage: cpu_leakage@17 {
1522                         reg = <0x17 0x1>;
1523                 };
1524         };
1525
1526         gic: interrupt-controller@ffc01000 {
1527                 compatible = "arm,gic-400";
1528                 interrupt-controller;
1529                 #interrupt-cells = <3>;
1530                 #address-cells = <0>;
1531
1532                 reg = <0xffc01000 0x1000>,
1533                       <0xffc02000 0x1000>,
1534                       <0xffc04000 0x2000>,
1535                       <0xffc06000 0x2000>;
1536                 interrupts = <GIC_PPI 9 0xf04>;
1537         };
1538
1539         pinctrl: pinctrl {
1540                 compatible = "rockchip,rk3288-pinctrl";
1541                 rockchip,grf = <&grf>;
1542                 rockchip,pmu = <&pmu>;
1543                 #address-cells = <1>;
1544                 #size-cells = <1>;
1545                 ranges;
1546
1547                 gpio0: gpio0@ff750000 {
1548                         compatible = "rockchip,gpio-bank";
1549                         reg =   <0xff750000 0x100>;
1550                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1551                         clocks = <&cru PCLK_GPIO0>;
1552
1553                         gpio-controller;
1554                         #gpio-cells = <2>;
1555
1556                         interrupt-controller;
1557                         #interrupt-cells = <2>;
1558                 };
1559
1560                 gpio1: gpio1@ff780000 {
1561                         compatible = "rockchip,gpio-bank";
1562                         reg = <0xff780000 0x100>;
1563                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1564                         clocks = <&cru PCLK_GPIO1>;
1565
1566                         gpio-controller;
1567                         #gpio-cells = <2>;
1568
1569                         interrupt-controller;
1570                         #interrupt-cells = <2>;
1571                 };
1572
1573                 gpio2: gpio2@ff790000 {
1574                         compatible = "rockchip,gpio-bank";
1575                         reg = <0xff790000 0x100>;
1576                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1577                         clocks = <&cru PCLK_GPIO2>;
1578
1579                         gpio-controller;
1580                         #gpio-cells = <2>;
1581
1582                         interrupt-controller;
1583                         #interrupt-cells = <2>;
1584                 };
1585
1586                 gpio3: gpio3@ff7a0000 {
1587                         compatible = "rockchip,gpio-bank";
1588                         reg = <0xff7a0000 0x100>;
1589                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1590                         clocks = <&cru PCLK_GPIO3>;
1591
1592                         gpio-controller;
1593                         #gpio-cells = <2>;
1594
1595                         interrupt-controller;
1596                         #interrupt-cells = <2>;
1597                 };
1598
1599                 gpio4: gpio4@ff7b0000 {
1600                         compatible = "rockchip,gpio-bank";
1601                         reg = <0xff7b0000 0x100>;
1602                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1603                         clocks = <&cru PCLK_GPIO4>;
1604
1605                         gpio-controller;
1606                         #gpio-cells = <2>;
1607
1608                         interrupt-controller;
1609                         #interrupt-cells = <2>;
1610                 };
1611
1612                 gpio5: gpio5@ff7c0000 {
1613                         compatible = "rockchip,gpio-bank";
1614                         reg = <0xff7c0000 0x100>;
1615                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1616                         clocks = <&cru PCLK_GPIO5>;
1617
1618                         gpio-controller;
1619                         #gpio-cells = <2>;
1620
1621                         interrupt-controller;
1622                         #interrupt-cells = <2>;
1623                 };
1624
1625                 gpio6: gpio6@ff7d0000 {
1626                         compatible = "rockchip,gpio-bank";
1627                         reg = <0xff7d0000 0x100>;
1628                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1629                         clocks = <&cru PCLK_GPIO6>;
1630
1631                         gpio-controller;
1632                         #gpio-cells = <2>;
1633
1634                         interrupt-controller;
1635                         #interrupt-cells = <2>;
1636                 };
1637
1638                 gpio7: gpio7@ff7e0000 {
1639                         compatible = "rockchip,gpio-bank";
1640                         reg = <0xff7e0000 0x100>;
1641                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1642                         clocks = <&cru PCLK_GPIO7>;
1643
1644                         gpio-controller;
1645                         #gpio-cells = <2>;
1646
1647                         interrupt-controller;
1648                         #interrupt-cells = <2>;
1649                 };
1650
1651                 gpio8: gpio8@ff7f0000 {
1652                         compatible = "rockchip,gpio-bank";
1653                         reg = <0xff7f0000 0x100>;
1654                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1655                         clocks = <&cru PCLK_GPIO8>;
1656
1657                         gpio-controller;
1658                         #gpio-cells = <2>;
1659
1660                         interrupt-controller;
1661                         #interrupt-cells = <2>;
1662                 };
1663
1664                 hdmi {
1665                         hdmi_ddc: hdmi-ddc {
1666                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1667                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 pcfg_pull_up: pcfg-pull-up {
1672                         bias-pull-up;
1673                 };
1674
1675                 pcfg_pull_down: pcfg-pull-down {
1676                         bias-pull-down;
1677                 };
1678
1679                 pcfg_pull_none: pcfg-pull-none {
1680                         bias-disable;
1681                 };
1682
1683                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1684                         bias-disable;
1685                         drive-strength = <12>;
1686                 };
1687
1688                 sleep {
1689                         global_pwroff: global-pwroff {
1690                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1691                         };
1692
1693                         ddrio_pwroff: ddrio-pwroff {
1694                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1695                         };
1696
1697                         ddr0_retention: ddr0-retention {
1698                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1699                         };
1700
1701                         ddr1_retention: ddr1-retention {
1702                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1703                         };
1704                 };
1705
1706                 edp {
1707                         edp_hpd: edp-hpd {
1708                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1709                         };
1710                 };
1711
1712                 i2c0 {
1713                         i2c0_xfer: i2c0-xfer {
1714                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1715                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1716                         };
1717                 };
1718
1719                 i2c1 {
1720                         i2c1_xfer: i2c1-xfer {
1721                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1722                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1723                         };
1724                 };
1725
1726                 i2c2 {
1727                         i2c2_xfer: i2c2-xfer {
1728                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1729                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1730                         };
1731                 };
1732
1733                 i2c3 {
1734                         i2c3_xfer: i2c3-xfer {
1735                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1736                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1737                         };
1738                 };
1739
1740                 i2c4 {
1741                         i2c4_xfer: i2c4-xfer {
1742                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1743                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1744                         };
1745                 };
1746
1747                 i2c5 {
1748                         i2c5_xfer: i2c5-xfer {
1749                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1750                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1751                         };
1752                 };
1753
1754                 i2s0 {
1755                         i2s0_bus: i2s0-bus {
1756                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1757                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1758                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1759                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1760                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1761                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1762                         };
1763                 };
1764
1765                 lcdc0 {
1766                         lcdc0_ctl: lcdc0-ctl {
1767                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1768                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1769                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1770                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1771                         };
1772                 };
1773
1774                 sdmmc {
1775                         sdmmc_clk: sdmmc-clk {
1776                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778
1779                         sdmmc_cmd: sdmmc-cmd {
1780                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1781                         };
1782
1783                         sdmmc_cd: sdmcc-cd {
1784                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1785                         };
1786
1787                         sdmmc_bus1: sdmmc-bus1 {
1788                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1789                         };
1790
1791                         sdmmc_bus4: sdmmc-bus4 {
1792                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1793                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1794                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1795                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1796                         };
1797                 };
1798
1799                 sdio0 {
1800                         sdio0_bus1: sdio0-bus1 {
1801                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1802                         };
1803
1804                         sdio0_bus4: sdio0-bus4 {
1805                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1806                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1807                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1808                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1809                         };
1810
1811                         sdio0_cmd: sdio0-cmd {
1812                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1813                         };
1814
1815                         sdio0_clk: sdio0-clk {
1816                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1817                         };
1818
1819                         sdio0_cd: sdio0-cd {
1820                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1821                         };
1822
1823                         sdio0_wp: sdio0-wp {
1824                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1825                         };
1826
1827                         sdio0_pwr: sdio0-pwr {
1828                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1829                         };
1830
1831                         sdio0_bkpwr: sdio0-bkpwr {
1832                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1833                         };
1834
1835                         sdio0_int: sdio0-int {
1836                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1837                         };
1838                 };
1839
1840                 sdio1 {
1841                         sdio1_bus1: sdio1-bus1 {
1842                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1843                         };
1844
1845                         sdio1_bus4: sdio1-bus4 {
1846                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1847                                                 <3 25 4 &pcfg_pull_up>,
1848                                                 <3 26 4 &pcfg_pull_up>,
1849                                                 <3 27 4 &pcfg_pull_up>;
1850                         };
1851
1852                         sdio1_cd: sdio1-cd {
1853                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1854                         };
1855
1856                         sdio1_wp: sdio1-wp {
1857                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1858                         };
1859
1860                         sdio1_bkpwr: sdio1-bkpwr {
1861                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1862                         };
1863
1864                         sdio1_int: sdio1-int {
1865                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1866                         };
1867
1868                         sdio1_cmd: sdio1-cmd {
1869                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1870                         };
1871
1872                         sdio1_clk: sdio1-clk {
1873                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1874                         };
1875
1876                         sdio1_pwr: sdio1-pwr {
1877                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1878                         };
1879                 };
1880
1881                 emmc {
1882                         emmc_clk: emmc-clk {
1883                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1884                         };
1885
1886                         emmc_cmd: emmc-cmd {
1887                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1888                         };
1889
1890                         emmc_pwr: emmc-pwr {
1891                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1892                         };
1893
1894                         emmc_bus1: emmc-bus1 {
1895                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1896                         };
1897
1898                         emmc_bus4: emmc-bus4 {
1899                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1900                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1901                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1902                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1903                         };
1904
1905                         emmc_bus8: emmc-bus8 {
1906                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1907                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1908                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1909                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1910                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1911                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1912                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1913                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1914                         };
1915                 };
1916
1917                 spi0 {
1918                         spi0_clk: spi0-clk {
1919                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1920                         };
1921                         spi0_cs0: spi0-cs0 {
1922                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1923                         };
1924                         spi0_tx: spi0-tx {
1925                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1926                         };
1927                         spi0_rx: spi0-rx {
1928                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1929                         };
1930                         spi0_cs1: spi0-cs1 {
1931                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1932                         };
1933                 };
1934                 spi1 {
1935                         spi1_clk: spi1-clk {
1936                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1937                         };
1938                         spi1_cs0: spi1-cs0 {
1939                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1940                         };
1941                         spi1_rx: spi1-rx {
1942                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1943                         };
1944                         spi1_tx: spi1-tx {
1945                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1946                         };
1947                 };
1948
1949                 spi2 {
1950                         spi2_cs1: spi2-cs1 {
1951                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1952                         };
1953                         spi2_clk: spi2-clk {
1954                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1955                         };
1956                         spi2_cs0: spi2-cs0 {
1957                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1958                         };
1959                         spi2_rx: spi2-rx {
1960                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1961                         };
1962                         spi2_tx: spi2-tx {
1963                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1964                         };
1965                 };
1966
1967                 uart0 {
1968                         uart0_xfer: uart0-xfer {
1969                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1970                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1971                         };
1972
1973                         uart0_cts: uart0-cts {
1974                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1975                         };
1976
1977                         uart0_rts: uart0-rts {
1978                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1979                         };
1980                 };
1981
1982                 uart1 {
1983                         uart1_xfer: uart1-xfer {
1984                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1985                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1986                         };
1987
1988                         uart1_cts: uart1-cts {
1989                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1990                         };
1991
1992                         uart1_rts: uart1-rts {
1993                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1994                         };
1995                 };
1996
1997                 uart2 {
1998                         uart2_xfer: uart2-xfer {
1999                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
2000                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2001                         };
2002                         /* no rts / cts for uart2 */
2003                 };
2004
2005                 uart3 {
2006                         uart3_xfer: uart3-xfer {
2007                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2008                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2009                         };
2010
2011                         uart3_cts: uart3-cts {
2012                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2013                         };
2014
2015                         uart3_rts: uart3-rts {
2016                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2017                         };
2018                 };
2019
2020                 uart4 {
2021                         uart4_xfer: uart4-xfer {
2022                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2023                                                 <5 13 3 &pcfg_pull_none>;
2024                         };
2025
2026                         uart4_cts: uart4-cts {
2027                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2028                         };
2029
2030                         uart4_rts: uart4-rts {
2031                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2032                         };
2033                 };
2034
2035                 tsadc {
2036                         otp_gpio: otp-gpio {
2037                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2038                         };
2039
2040                         otp_out: otp-out {
2041                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2042                         };
2043                 };
2044
2045                 pwm0 {
2046                         pwm0_pin: pwm0-pin {
2047                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2048                         };
2049                 };
2050
2051                 pwm1 {
2052                         pwm1_pin: pwm1-pin {
2053                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2054                         };
2055                 };
2056
2057                 pwm2 {
2058                         pwm2_pin: pwm2-pin {
2059                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2060                         };
2061                 };
2062
2063                 pwm3 {
2064                         pwm3_pin: pwm3-pin {
2065                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2066                         };
2067                 };
2068
2069                 gmac {
2070                         rgmii_pins: rgmii-pins {
2071                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2072                                                 <3 31 3 &pcfg_pull_none>,
2073                                                 <3 26 3 &pcfg_pull_none>,
2074                                                 <3 27 3 &pcfg_pull_none>,
2075                                                 <3 28 3 &pcfg_pull_none_12ma>,
2076                                                 <3 29 3 &pcfg_pull_none_12ma>,
2077                                                 <3 24 3 &pcfg_pull_none_12ma>,
2078                                                 <3 25 3 &pcfg_pull_none_12ma>,
2079                                                 <4 0 3 &pcfg_pull_none>,
2080                                                 <4 5 3 &pcfg_pull_none>,
2081                                                 <4 6 3 &pcfg_pull_none>,
2082                                                 <4 9 3 &pcfg_pull_none_12ma>,
2083                                                 <4 4 3 &pcfg_pull_none_12ma>,
2084                                                 <4 1 3 &pcfg_pull_none>,
2085                                                 <4 3 3 &pcfg_pull_none>;
2086                         };
2087
2088                         rmii_pins: rmii-pins {
2089                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2090                                                 <3 31 3 &pcfg_pull_none>,
2091                                                 <3 28 3 &pcfg_pull_none>,
2092                                                 <3 29 3 &pcfg_pull_none>,
2093                                                 <4 0 3 &pcfg_pull_none>,
2094                                                 <4 5 3 &pcfg_pull_none>,
2095                                                 <4 4 3 &pcfg_pull_none>,
2096                                                 <4 1 3 &pcfg_pull_none>,
2097                                                 <4 2 3 &pcfg_pull_none>,
2098                                                 <4 3 3 &pcfg_pull_none>;
2099                         };
2100                 };
2101
2102                 spdif {
2103                         spdif_tx: spdif-tx {
2104                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2105                         };
2106                 };
2107
2108                 cif {
2109                         cif_dvp_d2d9: cif-dvp-d2d9 {
2110                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2111                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2112                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2113                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2114                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2115                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2116                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2117                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2118                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2119                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2120                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2121                         };
2122                 };
2123         };
2124 };