arch/arm/boot/dts/rk3288-veyron.dtsi

   1 /*
   2  * Google Veyron (and derivatives) board device tree source
   3  *
   4  * Copyright 2015 Google, Inc
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *  Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/rockchip,rk808.h>
  46 #include <dt-bindings/input/input.h>
  47 #include "rk3288.dtsi"
  48
  49 / {
  50         memory {
  51                 device_type = "memory";
  52                 reg = <0x0 0x80000000>;
  53         };
  54
  55         gpio_keys: gpio-keys {
  56                 compatible = "gpio-keys";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pwr_key_l>;
  62                 power {
  63                         label = "Power";
  64                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
  65                         linux,code = <KEY_POWER>;
  66                         debounce-interval = <100>;
  67                         gpio-key,wakeup;
  68                 };
  69         };
  70
  71         gpio-restart {
  72                 compatible = "gpio-restart";
  73                 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&ap_warm_reset_h>;
  76                 priority = <200>;
  77         };
  78
  79         emmc_pwrseq: emmc-pwrseq {
  80                 compatible = "mmc-pwrseq-emmc";
  81                 pinctrl-0 = <&emmc_reset>;
  82                 pinctrl-names = "default";
  83                 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
  84         };
  85
  86         sdio_pwrseq: sdio-pwrseq {
  87                 compatible = "mmc-pwrseq-simple";
  88                 clocks = <&rk808 RK808_CLKOUT1>;
  89                 clock-names = "ext_clock";
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
  92
  93                 /*
  94                  * On the module itself this is one of these (depending
  95                  * on the actual card populated):
  96                  * - SDIO_RESET_L_WL_REG_ON
  97                  * - PDN (power down when low)
  98                  */
  99                 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 100         };
 101
 102         vcc_5v: vcc-5v {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "vcc_5v";
 105                 regulator-always-on;
 106                 regulator-boot-on;
 107                 regulator-min-microvolt = <5000000>;
 108                 regulator-max-microvolt = <5000000>;
 109         };
 110
 111         vcc33_sys: vcc33-sys {
 112                 compatible = "regulator-fixed";
 113                 regulator-name = "vcc33_sys";
 114                 regulator-always-on;
 115                 regulator-boot-on;
 116                 regulator-min-microvolt = <3300000>;
 117                 regulator-max-microvolt = <3300000>;
 118         };
 119
 120         vcc50_hdmi: vcc50-hdmi {
 121                 compatible = "regulator-fixed";
 122                 regulator-name = "vcc50_hdmi";
 123                 regulator-always-on;
 124                 regulator-boot-on;
 125                 vin-supply = <&vcc_5v>;
 126         };
 127 };
 128
 129 &cpu0 {
 130         cpu0-supply = <&vdd_cpu>;
 131 };
 132
 133 &emmc {
 134         status = "okay";
 135
 136         bus-width = <8>;
 137         cap-mmc-highspeed;
 138         rockchip,default-sample-phase = <158>;
 139         disable-wp;
 140         mmc-hs200-1_8v;
 141         mmc-pwrseq = <&emmc_pwrseq>;
 142         non-removable;
 143         num-slots = <1>;
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 146 };
 147
 148 &hdmi {
 149         status = "okay";
 150 };
 151
 152 &i2c0 {
 153         status = "okay";
 154
 155         clock-frequency = <400000>;
 156         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 157         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 158
 159         rk808: pmic@1b {
 160                 compatible = "rockchip,rk808";
 161                 reg = <0x1b>;
 162                 clock-output-names = "xin32k", "wifibt_32kin";
 163                 interrupt-parent = <&gpio0>;
 164                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 165                 pinctrl-names = "default";
 166                 pinctrl-0 = <&pmic_int_l>;
 167                 rockchip,system-power-controller;
 168                 wakeup-source;
 169                 #clock-cells = <1>;
 170
 171                 vcc1-supply = <&vcc33_sys>;
 172                 vcc2-supply = <&vcc33_sys>;
 173                 vcc3-supply = <&vcc33_sys>;
 174                 vcc4-supply = <&vcc33_sys>;
 175                 vcc6-supply = <&vcc_5v>;
 176                 vcc7-supply = <&vcc33_sys>;
 177                 vcc8-supply = <&vcc33_sys>;
 178                 vcc12-supply = <&vcc_18>;
 179                 vddio-supply = <&vcc33_io>;
 180
 181                 regulators {
 182                         vdd_cpu: DCDC_REG1 {
 183                                 regulator-name = "vdd_arm";
 184                                 regulator-always-on;
 185                                 regulator-boot-on;
 186                                 regulator-min-microvolt = <750000>;
 187                                 regulator-max-microvolt = <1450000>;
 188                                 regulator-ramp-delay = <6001>;
 189                                 regulator-state-mem {
 190                                         regulator-off-in-suspend;
 191                                 };
 192                         };
 193
 194                         vdd_gpu: DCDC_REG2 {
 195                                 regulator-name = "vdd_gpu";
 196                                 regulator-always-on;
 197                                 regulator-boot-on;
 198                                 regulator-min-microvolt = <800000>;
 199                                 regulator-max-microvolt = <1250000>;
 200                                 regulator-ramp-delay = <6001>;
 201                                 regulator-state-mem {
 202                                         regulator-on-in-suspend;
 203                                         regulator-suspend-microvolt = <1000000>;
 204                                 };
 205                         };
 206
 207                         vcc135_ddr: DCDC_REG3 {
 208                                 regulator-name = "vcc135_ddr";
 209                                 regulator-always-on;
 210                                 regulator-boot-on;
 211                                 regulator-state-mem {
 212                                         regulator-on-in-suspend;
 213                                 };
 214                         };
 215
 216                         /*
 217                          * vcc_18 has several aliases.  (vcc18_flashio and
 218                          * vcc18_wl).  We'll add those aliases here just to
 219                          * make it easier to follow the schematic.  The signals
 220                          * are actually hooked together and only separated for
 221                          * power measurement purposes).
 222                          */
 223                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 224                                 regulator-name = "vcc_18";
 225                                 regulator-always-on;
 226                                 regulator-boot-on;
 227                                 regulator-min-microvolt = <1800000>;
 228                                 regulator-max-microvolt = <1800000>;
 229                                 regulator-state-mem {
 230                                         regulator-on-in-suspend;
 231                                         regulator-suspend-microvolt = <1800000>;
 232                                 };
 233                         };
 234
 235                         /*
 236                          * Note that both vcc33_io and vcc33_pmuio are always
 237                          * powered together. To simplify the logic in the dts
 238                          * we just refer to vcc33_io every time something is
 239                          * powered from vcc33_pmuio. In fact, on later boards
 240                          * (such as danger) they're the same net.
 241                          */
 242                         vcc33_io: LDO_REG1 {
 243                                 regulator-name = "vcc33_io";
 244                                 regulator-always-on;
 245                                 regulator-boot-on;
 246                                 regulator-min-microvolt = <3300000>;
 247                                 regulator-max-microvolt = <3300000>;
 248                                 regulator-state-mem {
 249                                         regulator-on-in-suspend;
 250                                         regulator-suspend-microvolt = <3300000>;
 251                                 };
 252                         };
 253
 254                         vdd_10: LDO_REG3 {
 255                                 regulator-name = "vdd_10";
 256                                 regulator-always-on;
 257                                 regulator-boot-on;
 258                                 regulator-min-microvolt = <1000000>;
 259                                 regulator-max-microvolt = <1000000>;
 260                                 regulator-state-mem {
 261                                         regulator-on-in-suspend;
 262                                         regulator-suspend-microvolt = <1000000>;
 263                                 };
 264                         };
 265
 266                         vdd10_lcd_pwren_h: LDO_REG7 {
 267                                 regulator-name = "vdd10_lcd_pwren_h";
 268                                 regulator-always-on;
 269                                 regulator-boot-on;
 270                                 regulator-min-microvolt = <2500000>;
 271                                 regulator-max-microvolt = <2500000>;
 272                                 regulator-state-mem {
 273                                         regulator-off-in-suspend;
 274                                 };
 275                         };
 276
 277                         vcc33_lcd: SWITCH_REG1 {
 278                                 regulator-name = "vcc33_lcd";
 279                                 regulator-always-on;
 280                                 regulator-boot-on;
 281                                 regulator-state-mem {
 282                                         regulator-off-in-suspend;
 283                                 };
 284                         };
 285                 };
 286         };
 287 };
 288
 289 &i2c1 {
 290         status = "okay";
 291
 292         clock-frequency = <400000>;
 293         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 294         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 295
 296         tpm: tpm@20 {
 297                 compatible = "infineon,slb9645tt";
 298                 reg = <0x20>;
 299                 powered-while-suspended;
 300         };
 301 };
 302
 303 &i2c2 {
 304         status = "okay";
 305
 306         /* 100kHz since 4.7k resistors don't rise fast enough */
 307         clock-frequency = <100000>;
 308         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 309         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 310 };
 311
 312 &i2c4 {
 313         status = "okay";
 314
 315         clock-frequency = <400000>;
 316         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 317         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 318 };
 319
 320 &io_domains {
 321         status = "okay";
 322
 323         bb-supply = <&vcc33_io>;
 324         dvp-supply = <&vcc_18>;
 325         flash0-supply = <&vcc18_flashio>;
 326         gpio1830-supply = <&vcc33_io>;
 327         gpio30-supply = <&vcc33_io>;
 328         lcdc-supply = <&vcc33_lcd>;
 329         wifi-supply = <&vcc18_wl>;
 330 };
 331
 332 &pwm1 {
 333         status = "okay";
 334 };
 335
 336 &sdio0 {
 337         status = "okay";
 338
 339         bus-width = <4>;
 340         cap-sd-highspeed;
 341         cap-sdio-irq;
 342         keep-power-in-suspend;
 343         mmc-pwrseq = <&sdio_pwrseq>;
 344         non-removable;
 345         num-slots = <1>;
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 348         sd-uhs-sdr12;
 349         sd-uhs-sdr25;
 350         sd-uhs-sdr50;
 351         sd-uhs-sdr104;
 352         vmmc-supply = <&vcc33_sys>;
 353         vqmmc-supply = <&vcc18_wl>;
 354 };
 355
 356 &spi2 {
 357         status = "okay";
 358
 359         rx-sample-delay-ns = <12>;
 360 };
 361
 362 &tsadc {
 363         status = "okay";
 364
 365         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 366         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 367 };
 368
 369 &uart0 {
 370         status = "okay";
 371
 372         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 373         assigned-clocks = <&cru SCLK_UART0>;
 374         assigned-clock-rates = <48000000>;
 375
 376         /* Pins don't include flow control by default; add that in */
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 379 };
 380
 381 &uart1 {
 382         status = "okay";
 383 };
 384
 385 &uart2 {
 386         status = "okay";
 387 };
 388
 389 &usbphy {
 390         status = "okay";
 391 };
 392
 393 &usb_host0_ehci {
 394         status = "okay";
 395
 396         needs-reset-on-resume;
 397 };
 398
 399 &usb_host1 {
 400         status = "okay";
 401 };
 402
 403 &usb_otg {
 404         status = "okay";
 405
 406         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 407         assigned-clock-parents = <&cru SCLK_OTGPHY0>;
 408         dr_mode = "host";
 409 };
 410
 411 &vopb {
 412         status = "okay";
 413 };
 414
 415 &vopb_mmu {
 416         status = "okay";
 417 };
 418
 419 &wdt {
 420         status = "okay";
 421 };
 422
 423 &pinctrl {
 424         pinctrl-names = "default", "sleep";
 425         pinctrl-0 = <
 426                 /* Common for sleep and wake, but no owners */
 427                 &global_pwroff
 428         >;
 429         pinctrl-1 = <
 430                 /* Common for sleep and wake, but no owners */
 431                 &global_pwroff
 432         >;
 433
 434         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 435                 bias-disable;
 436                 drive-strength = <8>;
 437         };
 438
 439         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 440                 bias-pull-up;
 441                 drive-strength = <8>;
 442         };
 443
 444         pcfg_output_high: pcfg-output-high {
 445                 output-high;
 446         };
 447
 448         pcfg_output_low: pcfg-output-low {
 449                 output-low;
 450         };
 451
 452         buttons {
 453                 pwr_key_l: pwr-key-l {
 454                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 455                 };
 456         };
 457
 458         emmc {
 459                 emmc_reset: emmc-reset {
 460                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 461                 };
 462
 463                 /*
 464                  * We run eMMC at max speed; bump up drive strength.
 465                  * We also have external pulls, so disable the internal ones.
 466                  */
 467                 emmc_clk: emmc-clk {
 468                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 469                 };
 470
 471                 emmc_cmd: emmc-cmd {
 472                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 473                 };
 474
 475                 emmc_bus8: emmc-bus8 {
 476                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 477                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 478                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 479                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 480                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 481                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 482                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 483                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 484                 };
 485         };
 486
 487         pmic {
 488                 pmic_int_l: pmic-int-l {
 489                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 490                 };
 491         };
 492
 493         reboot {
 494                 ap_warm_reset_h: ap-warm-reset-h {
 495                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 496                 };
 497         };
 498
 499         recovery-switch {
 500                 rec_mode_l: rec-mode-l {
 501                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 502                 };
 503         };
 504
 505         sdio0 {
 506                 wifi_enable_h: wifienable-h {
 507                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 508                 };
 509
 510                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 511                 bt_enable_l: bt-enable-l {
 512                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 513                 };
 514
 515                 /*
 516                  * We run sdio0 at max speed; bump up drive strength.
 517                  * We also have external pulls, so disable the internal ones.
 518                  */
 519                 sdio0_bus4: sdio0-bus4 {
 520                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 521                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 522                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 523                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 524                 };
 525
 526                 sdio0_cmd: sdio0-cmd {
 527                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 528                 };
 529
 530                 sdio0_clk: sdio0-clk {
 531                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 532                 };
 533         };
 534
 535         tpm {
 536                 tpm_int_h: tpm-int-h {
 537                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 538                 };
 539         };
 540
 541         write-protect {
 542                 fw_wp_ap: fw-wp-ap {
 543                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 544                 };
 545         };
 546 };