arch/arm/boot/dts/rk3288-fpga.dts

   1 /dts-v1/;
   2
   3 #include <dt-bindings/clock/ddr.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/rkfb/rk_fb.h>
   6 #include <dt-bindings/suspend/rockchip-pm.h>
   7 #include <dt-bindings/sensor-dev.h>
   8
   9 #include "skeleton.dtsi"
  10 #include "rk3288-pinctrl.dtsi"
  11
  12 / {
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 serial2 = &uart_dbg;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 i2c3 = &i2c3;
  21                 i2c4 = &i2c4;
  22                 i2c5 = &i2c5;
  23                 lcdc0 = &lcdc0;
  24                 lcdc1 = &lcdc1;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a15";
  34                         reg = <0x500>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0x501>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x502>;
  45                 };
  46                 cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x503>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@ffc01000 {
  54                 compatible = "arm,cortex-a15-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 #address-cells = <0>;
  58                 reg = <0xffc01000 0x1000>,
  59                       <0xffc02000 0x1000>;
  60         };
  61
  62         sram: sram@ff710000 {
  63                 compatible = "mmio-sram";
  64                 reg = <0xff710000 0x8000>; /* 32k */
  65                 map-exec;
  66         };
  67
  68         timer {
  69                 compatible = "arm,armv7-timer";
  70                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  71                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  72                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  73                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  74                 clock-frequency = <24000000>;
  75         };
  76
  77         timer@ff810000 {
  78                 compatible = "rockchip,timer";
  79                 reg = <0xff810000 0x20>;
  80                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  81                 rockchip,broadcast = <1>;
  82         };
  83
  84         timer@ff810020 {
  85                 compatible = "rockchip,timer";
  86                 reg = <0xff810020 0x20>;
  87                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  88                 rockchip,clocksource = <1>;
  89                 rockchip,count-up = <1>;
  90         };
  91
  92         uart_dbg: serial@ff690000 {
  93                 compatible = "rockchip,serial";
  94                 reg = <0xff690000 0x100>;
  95                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  96                 clock-frequency = <24000000>;
  97                 reg-shift = <2>;
  98                 reg-io-width = <4>;
  99                 status = "disabled";
 100         };
 101
 102         fiq-debugger {
 103                 compatible = "rockchip,fiq-debugger";
 104                 rockchip,serial-id = <2>;
 105                 rockchip,signal-irq = <106>;
 106                 rockchip,wake-irq = <0>;
 107                 status = "disabled";
 108         };
 109
 110         i2c0: i2c@ff650000 {
 111                 compatible = "rockchip,rk30-i2c";
 112                 reg = <0xff650000 0x1000>;
 113                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 114                 #address-cells = <1>;
 115                 #size-cells = <0>;
 116                 rockchip,check-idle = <0>;
 117                 status = "disabled";
 118         };
 119
 120         i2c1: i2c@ff140000 {
 121                 compatible = "rockchip,rk30-i2c";
 122                 reg = <0xff140000 0x1000>;
 123                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 124                 #address-cells = <1>;
 125                 #size-cells = <0>;
 126                 rockchip,check-idle = <0>;
 127                 status = "disabled";
 128         };
 129
 130         i2c2: i2c@ff660000 {
 131                 compatible = "rockchip,rk30-i2c";
 132                 reg = <0xff660000 0x1000>;
 133                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 rockchip,check-idle = <0>;
 137                 status = "disabled";
 138         };
 139
 140         i2c3: i2c@ff150000 {
 141                 compatible = "rockchip,rk30-i2c";
 142                 reg = <0xff150000 0x1000>;
 143                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146                 rockchip,check-idle = <0>;
 147                 status = "disabled";
 148         };
 149
 150         i2c4: i2c@ff160000 {
 151                 compatible = "rockchip,rk30-i2c";
 152                 reg = <0xff160000 0x1000>;
 153                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 154                 #address-cells = <1>;
 155                 #size-cells = <0>;
 156                 rockchip,check-idle = <0>;
 157                 status = "disabled";
 158         };
 159
 160         i2c5: i2c@ff170000 {
 161                 compatible = "rockchip,rk30-i2c";
 162                 reg = <0xff170000 0x1000>;
 163                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 164                 #address-cells = <1>;
 165                 #size-cells = <0>;
 166                 rockchip,check-idle = <0>;
 167                 status = "disabled";
 168         };
 169
 170         lvds: lvds@ff96c000 {
 171                 compatible = "rockchip, rk32-lvds";
 172                 reg = <0xff960000 0x20000>;
 173         };
 174
 175         edp: edp@ff970000 {
 176                 compatible = "rockchip,rk32-edp";
 177                 reg = <0xff970000 0x4000>;
 178                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 179         };
 180
 181         hdmi: hdmi@ff980000 {
 182                 compatible = "rockchip,rk3288-hdmi";
 183                 reg = <0xff980000 0x20000>;
 184                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 185                 rockchip,hdmi_lcdc_source = <1>;
 186                 pinctrl-names = "default", "gpio";
 187                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 188                 pinctrl-1 = <&i2c5_gpio>;
 189                 status = "disabled";
 190         };
 191
 192         fb: fb{
 193                 compatible = "rockchip,rk-fb";
 194                 rockchip,disp-mode = <DUAL>;
 195         };
 196
 197         rk_screen: rk_screen{
 198                         compatible = "rockchip,screen";
 199         };
 200
 201         lcdc1: lcdc@ff940000 {
 202                 compatible = "rockchip,rk3288-lcdc";
 203                 rockchip,prop = <PRMRY>;
 204                 rochchip,pwr18 = <0>;
 205                 reg = <0xff940000 0x10000>;
 206                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 207                 pinctrl-names = "default", "gpio";
 208                 pinctrl-0 = <&lcdc0_lcdc>;
 209                 pinctrl-1 = <&lcdc0_gpio>;
 210                 status = "disabled";
 211         };
 212
 213         lcdc0: lcdc@ff930000 {
 214                 compatible = "rockchip,rk3288-lcdc";
 215                 rockchip,prop = <EXTEND>;
 216                 rockchip,pwr18 = <0>;
 217                 reg = <0xff930000 0x10000>;
 218                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 219                 //pinctrl-names = "default", "gpio";
 220                 //pinctrl-0 = <&lcdc0_lcdc>;
 221                 //pinctrl-1 = <&lcdc0_gpio>;
 222                 status = "disabled";
 223         };
 224
 225         adc: adc@ff100000 {
 226                 compatible = "rockchip,saradc";
 227                 reg = <0xff100000 0x100>;
 228                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 229                 #io-channel-cells = <1>;
 230                 io-channel-ranges;
 231                 rockchip,adc-vref = <1800>;
 232                 clock-frequency = <1000000>;
 233                 clock-names = "saradc", "pclk_saradc";
 234                 status = "disabled";
 235         };
 236
 237         rga@ff920000 {
 238                 compatible = "rockchip,rga";
 239                 reg = <0xff920000 0x1000>;
 240                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 241                 clock-names = "hclk_rga", "aclk_rga";
 242         };
 243
 244         i2s: rockchip-i2s@0xff890000 {
 245                 compatible = "rockchip-i2s";
 246                 reg = <0xff890000 0x10000>;
 247                 i2s-id = <0>;
 248                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 249         //      dmas = <&pdma0 0>,
 250         //              <&pdma0 1>;
 251                 //#dma-cells = <2>;
 252         //      dma-names = "tx", "rx";
 253         };
 254
 255         spdif: rockchip-spdif@0xff8b0000 {
 256                 compatible = "rockchip-spdif";
 257                 reg = <0xff8b0000 0x10000>;     //8channel
 258                 //reg = <ff880000 0x2000>;//2channel
 259                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 260         //      dmas = <&pdma0 8>;
 261                 //#dma-cells = <1>;
 262         };
 263
 264         ion {
 265                 compatible = "rockchip,ion";
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 269                         compatible = "rockchip,ion-heap";
 270                         rockchip,ion_heap = <4>;
 271                         reg = <0x00000000 0x04000000>; /* 64MB */
 272                 };
 273                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
 274                         compatible = "rockchip,ion-heap";
 275                         rockchip,ion_heap = <0>;
 276                 };
 277         };
 278
 279         mmc: mshc@ff0c0000 {
 280                 compatible = "rockchip,rk_mmc";
 281                 reg = <0xff0c0000 0x4000>;
 282                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 clock-frequency = <50000000>;
 286                 clock-freq-min-max = <400000 50000000>;
 287                 num-slots = <1>;
 288                 supports-highspeed;
 289                 broken-cd;
 290                 card-detect-delay = <200>;
 291                 pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
 292                 fifo-depth = <0x100>;
 293                 emmc-compatible = <0>;
 294                 status = "okay";
 295         };
 296
 297         sdio0: mshc@ff0d0000 {
 298                 compatible = "rockchip,rk_mmc";
 299                 reg = <0xff0d0000 0x4000>;
 300                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 clock-frequency = <50000000>;
 304                 clock-freq-min-max = <400000 50000000>;
 305                 num-slots = <1>;
 306                 supports-highspeed;
 307                 fifo-depth = <0x100>;
 308                 emmc-compatible = <0>;
 309                 status = "disabled";
 310         };
 311
 312         sdio1: mshc@ff0e0000 {
 313                 compatible = "rockchip,rk_mmc";
 314                 reg = <0xff0e0000 0x4000>;
 315                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 clock-frequency = <50000000>;
 319                 clock-freq-min-max = <400000 50000000>;
 320                 num-slots = <1>;
 321                 supports-highspeed;
 322                 fifo-depth = <0x100>;
 323                 emmc-compatible = <0>;
 324                 status = "disabled";
 325         };
 326
 327         emmc: mshc@ff0f0000 {
 328                 compatible = "rockchip,rk_mmc";
 329                 reg = <0xff0f0000 0x4000>;
 330                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 clock-frequency = <50000000>;
 334                 clock-freq-min-max = <400000 50000000>;
 335                 num-slots = <1>;
 336                 supports-highspeed;
 337                 fifo-depth = <0x100>;
 338                 emmc-compatible = <1>;
 339                 status = "disabled";
 340         };
 341
 342         vpu: vpu_service@ff9a0000 {
 343                 compatible = "vpu_service";
 344                 reg = <0xff9a0000 0x800>;
 345                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 346                 interrupt-names = "irq_enc", "irq_dec";
 347                 name = "vpu_service";
 348                 status = "disabled";
 349         };
 350
 351         hevc: hevc_service@ff9c0000 {
 352                 compatible = "rockchip,hevc_service";
 353                 reg = <0xff9c0000 0x800>;
 354                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 355                 interrupt-names = "irq_dec";
 356                 name = "hevc_service";
 357                 status = "disabled";
 358         };
 359
 360         iep: iep@ff900000 {
 361                 compatible = "rockchip,iep";
 362                 reg = <0xff900000 0x800>;
 363                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 364                 status = "disabled";
 365         };
 366
 367         dwc_control_usb: dwc-control-usb@ff770284 {
 368                 compatible = "rockchip,rk3288-dwc-control-usb";
 369                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 370                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 371                       <0xff770320 0x14>, <0xff770334 0x14>,
 372                       <0xff770348 0x10>, <0xff770358 0x08>,
 373                       <0xff770360 0x08>;
 374                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 375                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 376                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 377                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 378                             "GRF_UOC4_BASE";
 379                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 380                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 381                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 382                 interrupt-names = "otg_id", "bvalid",
 383                                   "otg_linestate", "host0_linestate",
 384                                   "host1_linestate";
 385                 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
 386                 /*      <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
 387                 /*clocks = <&clk_gates4 5>;*/
 388                 /*clock-names = "hclk_usb_peri";*/
 389         };
 390
 391         usb1: usb@ff580000 {
 392                 compatible = "rockchip,rk3288_usb20_otg";
 393                 reg = <0xff580000 0x40000>;
 394                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 395         };
 396
 397         usb2: usb@ff540000 {
 398                 compatible = "rockchip,rk3288_usb20_host";
 399                 reg = <0xff540000 0x40000>;
 400                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 401         };
 402
 403         usb3: usb@ff520000 {
 404                 compatible = "rockchip,rk3288_rk_ohci_host";
 405                 reg = <0xff520000 0x20000>;
 406                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 407         };
 408
 409         usb4: usb@ff500000 {
 410                 compatible = "rockchip,rk3288_rk_ehci_host";
 411                 reg = <0xff500000 0x20000>;
 412                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 413         };
 414
 415         usb5: usb@ff5c0000 {
 416                 compatible = "rockchip,rk3288_rk_ehci1_host";
 417                 reg = <0xff5c0000 0x40000>;
 418                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 419         };
 420
 421         gmac: eth@ff290000 {
 422                 compatible = "rockchip,gmac";
 423                 reg = <0xff290000 0x10000>;
 424                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 425                 interrupt-names = "macirq";
 426                 phy-mode = "rmii";
 427                 //phy-mode = "gmii";
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 430         };
 431 };
 432
 433 #include "lcd-td043mgeal.dtsi"
 434
 435 / {
 436         compatible = "rockchip,rk3288-fpga";
 437
 438         memory {
 439                 device_type = "memory";
 440                 reg = <0x00000000 0x10000000>;
 441         };
 442
 443         chosen {
 444                 bootargs = "androidboot.console=ttyFIQ0 initrd=0x02000000,0x00800000";
 445         };
 446
 447         fiq-debugger {
 448                 status = "okay";
 449         };
 450
 451         rockchip-rt5631 {
 452                 compatible = "rockchip-rt5631";
 453                 dais {
 454                         dai0 {
 455                                 codec-name = "rt5631.0-001a";
 456                                 cpu-dai-name = "rockchip-i2s.0";
 457                                 format = "i2s";
 458                                 //continuous-clock;
 459                                 //bitclock-inversion;
 460                                 //frame-inversion;
 461                                 //bitclock-master;
 462                                 //frame-master;
 463                         };
 464                 };
 465         };
 466
 467         rockchip-rk610 {
 468                 compatible = "rockchip-rk610";
 469                 dais {
 470                         dai0 {
 471                                 codec-name = "rk610_codec.0-0060";
 472                                 cpu-dai-name = "rockchip-i2s.0";
 473                                 format = "i2s";
 474                                 //continuous-clock;
 475                                 //bitclock-inversion;
 476                                 //frame-inversion;
 477                                 //bitclock-master;
 478                                 //frame-master;
 479                         };
 480                 };
 481         };
 482
 483         codec-hdmi-spdif {
 484                 compatible = "hdmi-spdif";
 485         };
 486
 487         codec-hdmi-i2s {
 488                 compatible = "hdmi-i2s";
 489         };
 490
 491         codec-hdmi-spdif {
 492                 compatible = "hdmi-spdif";
 493         };
 494 };
 495
 496 &i2c0 {
 497         status = "okay";
 498         rt5631@1a {
 499                 compatible = "rt5631";
 500                 reg = <0x1a>;
 501         };
 502
 503         rk610ctl@40 {
 504                 compatible = "rk610_ctl";
 505                 reg = <0x40>;
 506                 rk610-reset-io = <&gpio3 GPIO_B2 GPIO_ACTIVE_HIGH>;
 507         //      clocks = <&clk_i2s>;
 508         //      clock-names = "i2s_clk";
 509         };
 510
 511         rk610codec@60 {//RK610_CODEC addr  from 0x60 to 0x80 (0x60~0x80)
 512                 compatible = "rk610_codec";
 513                 reg = <0x60>;
 514                 spk_ctl_io = <&gpio2 GPIO_D7 GPIO_ACTIVE_HIGH>;
 515                 boot_depop = <1>;
 516                 pa_enable_time = <1000>;
 517         };
 518
 519         ion {
 520                 compatible = "rockchip,ion";
 521                 #address-cells = <1>;
 522                 #size-cells = <0>;
 523                 rockchip,ion-heap@1 { /* CMA HEAP */
 524                         compatible = "rockchip,ion-reserve";
 525                         reg = <1>;
 526                         memory-reservation = <0x00000000 0x04000000>; /* 64MB */
 527                 };
 528                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 529                         reg = <3>;
 530                 };
 531         };
 532 };
 533
 534 &fb {
 535         rockchip,disp-mode = <DUAL>;
 536 };
 537
 538 &rk_screen {
 539          display-timings = <&disp_timings>;
 540 };
 541
 542 &lcdc0 {
 543         status = "okay";
 544         power_ctr: power_ctr {
 545                 rockchip,debug = <0>;
 546                 rockchip,mirror = <NO_MIRROR>;
 547                 /*lcd_en:lcd_en {
 548                         rockchip,power_type = <GPIO>;
 549                         gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
 550                         rockchip,delay = <10>;
 551                 };
 552
 553
 554                 lcd_cs:lcd_cs {
 555                         rockchip,power_type = <REGULATOR>;
 556                         rockchip,delay = <10>;
 557                 };
 558
 559                 lcd_rst:lcd_rst {
 560                         rockchip,power_type = <GPIO>;
 561                         gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
 562                         rockchip,delay = <5>;
 563                 };*/
 564
 565         };
 566 };
 567
 568 &lcdc1 {
 569         status = "disable";
 570 };
 571
 572 &hdmi {
 573         status = "okay";
 574         rockchips,hdmi_audio_source = <0>;
 575 };