arch/arm/boot/dts/rk3188-clocks.dtsi

   1 /*
   2  * Copyright (C) 2013 ROCKCHIP, Inc.
   3  * Author: chenxing <chenxing@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <dt-bindings/clock/rockchip,rk3188.h>
  16
  17 /{
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0 0x20000000 0x0100>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "fixed-clock";
  29                                 #clock-cells = <0>;
  30                                 clock-output-names = "xin24m";
  31                                 clock-frequency = <24000000>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "fixed-clock";
  36                                 #clock-cells = <0>;
  37                                 clocks = <&xin24m>;
  38                                 clock-output-names = "xin12m";
  39                                 clock-frequency = <12000000>;
  40                         };
  41
  42                         dummy: dummy {
  43                                 compatible = "fixed-clock";
  44                                 #clock-cells = <0>;
  45                                 clock-output-names = "dummy";
  46                                 clock-frequency = <0>;
  47                         };
  48
  49
  50                         rmii_clkin: rmii_clkin {
  51                                 compatible = "fixed-clock";
  52                                 #clock-cells = <0>;
  53                                 clock-output-names = "rmii_clkin";
  54                                 clock-frequency = <0>;
  55                         };
  56
  57                         clk_hsadc_ext: clk_hsadc_ext {
  58                                 compatible = "fixed-clock";
  59                                 #clock-cells = <0>;
  60                                 clock-output-names = "clk_hsadc_ext";
  61                                 clock-frequency = <0>;
  62                         };
  63
  64                         clk_cif_in: clk_cif_in {
  65                                 compatible = "fixed-clock";
  66                                 #clock-cells = <0>;
  67                                 clock-output-names = "clk_cif_in";
  68                                 clock-frequency = <0>;
  69                         };
  70
  71                 };
  72
  73                 fixed_factor_cons {
  74                         compatible = "rockchip,rk-fixed-factor-cons";
  75
  76                         otgphy0_480m: otgphy0_480m {
  77                                 compatible = "fixed-factor-clock";
  78                                 clocks = <&clk_gates1 5>;
  79                                 clock-output-names = "otgphy0_480m";
  80                                 clock-div = <1>;
  81                                 clock-mult = <20>;
  82                                 #clock-cells = <0>;
  83                         };
  84
  85                         otgphy1_480m: otgphy1_480m {
  86                                 compatible = "fixed-factor-clock";
  87                                 clocks = <&clk_gates1 6>;
  88                                 clock-output-names = "otgphy1_480m";
  89                                 clock-div = <1>;
  90                                 clock-mult = <20>;
  91                                 #clock-cells = <0>;
  92                         };
  93
  94                 };
  95
  96                 clock_regs {
  97                         compatible = "rockchip,rk-clock-regs";
  98                         reg = <0x0000 0x3ff>;
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges;
 102
 103                         /* PLL control regs */
 104                         pll_cons {
 105                                 compatible = "rockchip,rk-pll-cons";
 106                                 #address-cells = <1>;
 107                                 #size-cells = <1>;
 108                                 ranges ;
 109
 110                                 clk_apll: pll-clk@0000 {
 111                                         compatible = "rockchip,rk3188-pll-clk";
 112                                         reg = <0x0000 0x10>;
 113                                         mode-reg = <0x0040 0>;
 114                                         status-reg = <0x00ac 6>;
 115                                         clocks = <&xin24m>;
 116                                         clock-output-names = "clk_apll";
 117                                         rockchip,pll-type = <CLK_PLL_3188_APLL>;
 118                                         #clock-cells = <0>;
 119                                 };
 120
 121                                 clk_dpll: pll-clk@0010 {
 122                                         compatible = "rockchip,rk3188-pll-clk";
 123                                         reg = <0x0010 0x10>;
 124                                         mode-reg = <0x0040 4>;
 125                                         status-reg = <0x00ac 5>;
 126                                         clocks = <&xin24m>;
 127                                         clock-output-names = "clk_dpll";
 128                                         rockchip,pll-type = <CLK_PLL_3188>;
 129                                         #clock-cells = <0>;
 130                                 };
 131
 132                                 clk_cpll: pll-clk@0020 {
 133                                         compatible = "rockchip,rk3188-pll-clk";
 134                                         reg = <0x0020 0x10>;
 135                                         mode-reg = <0x0040 8>;
 136                                         status-reg = <0x00ac 7>;
 137                                         clocks = <&xin24m>;
 138                                         clock-output-names = "clk_cpll";
 139                                         rockchip,pll-type = <CLK_PLL_3188>;
 140                                         #clock-cells = <0>;
 141                                         #clock-init-cells = <1>;
 142                                 };
 143
 144                                 clk_gpll: pll-clk@0030 {
 145                                         compatible = "rockchip,rk3188-pll-clk";
 146                                         reg = <0x0030 0x10>;
 147                                         mode-reg = <0x0040 12>;
 148                                         status-reg = <0x00ac 8>;
 149                                         clocks = <&xin24m>;
 150                                         clock-output-names = "clk_gpll";
 151                                         rockchip,pll-type = <CLK_PLL_3188>;
 152                                         #clock-cells = <0>;
 153                                         #clock-init-cells = <1>;
 154                                 };
 155                         };
 156
 157                         /* Select control regs */
 158                         clk_sel_cons {
 159                                 compatible = "rockchip,rk-sel-cons";
 160                                 #address-cells = <1>;
 161                                 #size-cells = <1>;
 162                                 ranges;
 163
 164                                 clk_sel_con0: sel-con@0044 {
 165                                         compatible = "rockchip,rk3188-selcon";
 166                                         reg = <0x0044 0x4>;
 167                                         #address-cells = <1>;
 168                                         #size-cells = <1>;
 169
 170                                         aclk_cpu_div: aclk_cpu_div {
 171                                                 compatible = "rockchip,rk3188-div-con";
 172                                                 rockchip,bits = <0 5>;
 173                                                 clocks = <&aclk_cpu>;
 174                                                 clock-output-names = "aclk_cpu";
 175                                                 #clock-cells = <0>;
 176                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 177                                                 rockchip,clkops-idx =
 178                                                         <CLKOPS_RATE_MUX_DIV>;
 179                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 180                                         };
 181
 182                                         aclk_cpu: aclk_cpu_mux {
 183                                                 compatible = "rockchip,rk3188-mux-con";
 184                                                 rockchip,bits = <5 1>;
 185                                                 clocks = <&clk_apll>, <&clk_gpll>;
 186                                                 clock-output-names = "aclk_cpu";
 187                                                 #clock-cells = <0>;
 188                                                 #clock-init-cells = <1>;
 189                                         };
 190
 191                                         clk_core_peri: clk_core_peri_div {
 192                                                 compatible = "rockchip,rk3188-div-con";
 193                                                 rockchip,bits = <6 2>;
 194                                                 clocks = <&clk_core>;
 195                                                 clock-output-names = "clk_core_peri";
 196                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 197                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 198                                                 #clock-cells = <0>;
 199                                                 rockchip,div-relations = <0x0 2
 200                                                                  0x1 4
 201                                                                  0x2 8
 202                                                                  0x3 16>;
 203                                         };
 204
 205                                         clk_core: clk_core_mux {
 206                                                 compatible = "rockchip,rk3188-mux-con";
 207                                                 rockchip,bits = <8 1>;
 208                                                 clocks = <&clk_apll>,
 209                                                        <&clk_gates0 1>;
 210                                                 clock-output-names = "clk_core";
 211                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 212                                                                         CLK_SET_RATE_NO_REPARENT)>;
 213                                                 #clock-cells = <0>;
 214                                                 #clock-init-cells = <1>;
 215                                         };
 216
 217                                         clk_core_div: clk_core_div {
 218                                                 compatible = "rockchip,rk3188-div-con";
 219                                                 rockchip,bits = <9 5>;
 220                                                 clocks = <&clk_core>;
 221                                                 clock-output-names = "clk_core";
 222                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 223                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 224                                                 #clock-cells = <0>;
 225                                         };
 226
 227                                         /* reg[15:14]: reserved */
 228
 229                                 };
 230
 231                                 clk_sel_con1: sel-con@0048 {
 232                                         compatible = "rockchip,rk3188-selcon";
 233                                         reg = <0x0048 0x4>;
 234                                         #address-cells = <1>;
 235                                         #size-cells = <1>;
 236
 237                                         /* reg[2:0]: reserved */
 238
 239                                         aclk_core: aclk_core_div {
 240                                                 compatible = "rockchip,rk3188-div-con";
 241                                                 rockchip,bits = <3 3>;
 242                                                 clocks = <&clk_core>;
 243                                                 clock-output-names = "aclk_core";
 244                                                 #clock-cells = <0>;
 245                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 246                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 247                                                 rockchip,div-relations = <0x0 1
 248                                                                  0x1 2
 249                                                                  0x2 3
 250                                                                  0x3 4
 251                                                                  0x4 8>;
 252                                         };
 253
 254                                         /* reg[7:6]: reserved */
 255
 256                                         hclk_cpu: hclk_cpu_div {
 257                                                 compatible = "rockchip,rk3188-div-con";
 258                                                 rockchip,bits = <8 2>;
 259                                                 clocks = <&aclk_cpu>;
 260                                                 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
 261                                                 clock-output-names = "hclk_cpu";
 262                                                 #clock-cells = <0>;
 263                                                 #clock-init-cells = <1>;
 264                                         };
 265
 266                                         /* reg[11:10]: reserved */
 267
 268                                         pclk_cpu: pclk_cpu_div {
 269                                                 compatible = "rockchip,rk3188-div-con";
 270                                                 rockchip,bits = <12 2>;
 271                                                 clocks = <&aclk_cpu>;
 272                                                 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
 273                                                 clock-output-names = "pclk_cpu";
 274                                                 #clock-cells = <0>;
 275                                                 #clock-init-cells = <1>;
 276                                         };
 277
 278                                         pclk_ahb2apb: pclk_ahb2apb_div {
 279                                                 compatible = "rockchip,rk3188-div-con";
 280                                                 rockchip,bits = <14 2>;
 281                                                 clocks = <&hclk_cpu>;
 282                                                 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
 283                                                 clock-output-names = "pclk_ahb2apb";
 284                                                 #clock-cells = <0>;
 285                                                 #clock-init-cells = <1>;
 286                                         };
 287
 288                                 };
 289                                 clk_sel_con2: sel-con@004c {
 290                                         compatible = "rockchip,rk3188-selcon";
 291                                         reg = <0x004c 0x4>;
 292                                         #address-cells = <1>;
 293                                         #size-cells = <1>;
 294
 295                                         /* reg[14:0]: reserved */
 296
 297                                         clk_i2s_pll_mux: clk_i2s_pll_mux {
 298                                                 compatible = "rockchip,rk3188-mux-con";
 299                                                 rockchip,bits = <15 1>;
 300                                                 clocks = <&clk_gpll>, <&clk_cpll>;
 301                                                 clock-output-names = "clk_i2s_pll";
 302                                                 #clock-cells = <0>;
 303                                                 #clock-init-cells = <1>;
 304                                         };
 305                                 };
 306
 307                                 clk_sel_con3: sel-con@0050 {
 308                                         compatible = "rockchip,rk3188-selcon";
 309                                         reg = <0x0050 0x4>;
 310                                         #address-cells = <1>;
 311                                         #size-cells = <1>;
 312
 313                                         clk_i2s_div: clk_i2s_div {
 314                                                 compatible = "rockchip,rk3188-div-con";
 315                                                 rockchip,bits = <0 7>;
 316                                                 clocks = <&clk_i2s_pll_mux>;
 317                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 318                                                 clock-output-names = "clk_i2s_div";
 319                                                 #clock-cells = <0>;
 320                                         };
 321
 322                                         /* reg[7]: reserved */
 323
 324                                         clk_i2s: clk_i2s_mux {
 325                                                 compatible = "rockchip,rk3188-mux-con";
 326                                                 rockchip,bits = <8 2>;
 327                                                 clocks = <&clk_i2s_div>, <&clk_i2s_frac>, <&xin12m>;
 328                                                 clock-output-names = "clk_i2s";
 329                                                 rockchip,clkops-idx = <CLKOPS_RATE_I2S>;
 330                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 331                                                 #clock-cells = <0>;
 332                                         };
 333
 334                                         /* reg[15:10]: reserved */
 335                                 };
 336
 337                                 /* clk_sel_con4: reserved */
 338
 339                                 clk_sel_con5: sel-con@0058 {
 340                                         compatible = "rockchip,rk3188-selcon";
 341                                         reg = <0x0058 0x4>;
 342                                         #address-cells = <1>;
 343                                         #size-cells = <1>;
 344
 345                                         clk_spdif_div: clk_spdif_div {
 346                                                 compatible = "rockchip,rk3188-div-con";
 347                                                 rockchip,bits = <0 7>;
 348                                                 clocks = <&clk_i2s_pll_mux>;
 349                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 350                                                 clock-output-names = "clk_spdif_div";
 351                                                 /* spdif same as i2s */
 352                                                 #clock-cells = <0>;
 353                                         };
 354
 355                                         /* reg[7]: reserved */
 356
 357                                         clk_spdif: clk_spdif_mux {
 358                                                 compatible = "rockchip,rk3188-mux-con";
 359                                                 rockchip,bits = <8 2>;
 360                                                 clocks = <&clk_spdif_div>, <&clk_spdif_frac>, <&xin12m>;
 361                                                 clock-output-names = "clk_spdif";
 362                                                 rockchip,clkops-idx = <CLKOPS_RATE_I2S>;
 363                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 364                                                 #clock-cells = <0>;
 365                                         };
 366
 367                                         /* reg[15:10]: reserved */
 368                                 };
 369
 370                                 /* clk_sel_con6: reserved */
 371
 372                                 clk_sel_con7: sel-con@0060 {
 373                                         compatible = "rockchip,rk3188-selcon";
 374                                         reg = <0x0060 0x4>;
 375                                         #address-cells = <1>;
 376                                         #size-cells = <1>;
 377                                         clk_i2s_frac: clk_i2s_frac {
 378                                                 compatible = "rockchip,rk3188-frac-con";
 379                                                 clocks = <&clk_i2s_div>;
 380                                                 clock-output-names = "clk_i2s_frac";
 381                                                 /* numerator    denominator */
 382                                                 rockchip,bits = <0 32>;
 383                                                 #clock-cells = <0>;
 384                                                 rockchip,clkops-idx =
 385                                                         <CLKOPS_RATE_I2S_FRAC>;
 386                                         };
 387                                 };
 388
 389                                 /* clk_sel_con8: reserved */
 390
 391                                 clk_sel_con9: sel-con@0068 {
 392                                         compatible = "rockchip,rk3188-selcon";
 393                                         reg = <0x0068 0x4>;
 394                                         #address-cells = <1>;
 395                                         #size-cells = <1>;
 396                                         clk_spdif_frac: clk_spdif_frac {
 397                                                 compatible = "rockchip,rk3188-frac-con";
 398                                                 clocks = <&clk_spdif_div>;
 399                                                 clock-output-names = "clk_spdif_frac";
 400                                                 /* numerator    denominator */
 401                                                 rockchip,bits = <0 32>;
 402                                                 #clock-cells = <0>;
 403                                                 rockchip,clkops-idx =
 404                                                         <CLKOPS_RATE_I2S_FRAC>;
 405                                         };
 406                                 };
 407
 408                                 clk_sel_con10: sel-con@006c {
 409                                         compatible = "rockchip,rk3188-selcon";
 410                                         reg = <0x006c 0x4>;
 411                                         #address-cells = <1>;
 412                                         #size-cells = <1>;
 413
 414                                         aclk_peri_div: aclk_peri_div {
 415                                                 compatible = "rockchip,rk3188-div-con";
 416                                                 rockchip,bits = <0 5>;
 417                                                 clocks = <&aclk_peri>;
 418                                                 clock-output-names = "aclk_peri";
 419                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 420                                                 #clock-cells = <0>;
 421                                                 #clock-init-cells = <1>;
 422                                                 rockchip,clkops-idx =
 423                                                         <CLKOPS_RATE_MUX_DIV>;
 424                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 425                                         };
 426
 427                                         /* reg[7:5]: reserved */
 428
 429                                         hclk_peri: hclk_peri_div {
 430                                                 compatible = "rockchip,rk3188-div-con";
 431                                                 rockchip,bits = <8 2>;
 432                                                 clocks = <&aclk_peri>;
 433                                                 clock-output-names = "hclk_peri";
 434                                                 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
 435                                                 #clock-cells = <0>;
 436                                                 #clock-init-cells = <1>;
 437                                         };
 438
 439                                         /* reg[11:10]: reserved */
 440
 441                                         pclk_peri: pclk_peri_div {
 442                                                 compatible = "rockchip,rk3188-div-con";
 443                                                 rockchip,bits = <12 2>;
 444                                                 clocks = <&aclk_peri>;
 445                                                 clock-output-names = "pclk_peri";
 446                                                 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
 447                                                 #clock-cells = <0>;
 448                                                 #clock-init-cells = <1>;
 449                                         };
 450
 451                                         /* reg[14]: reserved */
 452
 453                                         aclk_peri: aclk_peri_mux {
 454                                                 compatible = "rockchip,rk3188-mux-con";
 455                                                 rockchip,bits = <15 1>;
 456                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 457                                                 clock-output-names = "aclk_peri";
 458                                                 #clock-cells = <0>;
 459                                                 #clock-init-cells = <1>;
 460                                         };
 461                                 };
 462
 463                                 clk_sel_con11: sel-con@0070 {
 464                                         compatible = "rockchip,rk3188-selcon";
 465                                         reg = <0x0070 0x4>;
 466                                         #address-cells = <1>;
 467                                         #size-cells = <1>;
 468
 469                                         clk_sdmmc: clk_sdmmc_div {
 470                                                 compatible = "rockchip,rk3188-div-con";
 471                                                 rockchip,bits = <0 6>;
 472                                                 clocks = <&hclk_peri>;
 473                                                 clock-output-names = "clk_sdmmc";
 474                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 475                                                 rockchip,clkops-idx =
 476                                                         <CLKOPS_RATE_EVENDIV>;
 477                                                 #clock-cells = <0>;
 478                                         };
 479
 480                                         /* reg[7:6]: reserved */
 481
 482                                         clk_ehci1phy12m: ehci1_phy_div {
 483                                                 compatible = "rockchip,rk3188-div-con";
 484                                                 rockchip,bits = <8 6>;
 485                                                 clocks = <&clk_ehci1phy480m>;
 486                                                 clock-output-names = "clk_ehci1phy12m";
 487                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 488                                                 #clock-cells = <0>;
 489                                         };
 490
 491                                         /* reg[15:14]: reserved */
 492
 493                                 };
 494
 495                                 clk_sel_con12: sel-con@0074 {
 496                                         compatible = "rockchip,rk3188-selcon";
 497                                         reg = <0x0074 0x4>;
 498                                         #address-cells = <1>;
 499                                         #size-cells = <1>;
 500
 501                                         clk_sdio: clk_sdio_div {
 502                                                 compatible = "rockchip,rk3188-div-con";
 503                                                 rockchip,bits = <0 6>;
 504                                                 clocks = <&hclk_peri>;
 505                                                 clock-output-names = "clk_sdio";
 506                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 507                                                 rockchip,clkops-idx =
 508                                                         <CLKOPS_RATE_EVENDIV>;
 509                                                 #clock-cells = <0>;
 510                                         };
 511
 512                                         /* reg[7:6]: reserved */
 513
 514                                         clk_emmc: clk_emmc_div {
 515                                                 compatible = "rockchip,rk3188-div-con";
 516                                                 rockchip,bits = <8 6>;
 517                                                 clocks = <&hclk_peri>;
 518                                                 clock-output-names = "clk_emmc";
 519                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 520                                                 rockchip,clkops-idx =
 521                                                         <CLKOPS_RATE_EVENDIV>;
 522                                                 #clock-cells = <0>;
 523                                         };
 524
 525                                         /* reg[14]: reserved */
 526
 527                                         clk_uart_pll_mux: clk_uart_pll_mux {
 528                                                 compatible = "rockchip,rk3188-mux-con";
 529                                                 rockchip,bits = <15 1>;
 530                                                 clocks = <&clk_gpll>, <&clk_cpll>;
 531                                                 clock-output-names = "clk_uart_pll";
 532                                                 #clock-cells = <0>;
 533                                                 #clock-init-cells = <1>;
 534                                         };
 535                                 };
 536
 537                                 clk_sel_con13: sel-con@0078 {
 538                                         compatible = "rockchip,rk3188-selcon";
 539                                         reg = <0x0078 0x4>;
 540                                         #address-cells = <1>;
 541                                         #size-cells = <1>;
 542
 543                                         clk_uart0_div: clk_uart0_div {
 544                                                 compatible = "rockchip,rk3188-div-con";
 545                                                 rockchip,bits = <0 7>;
 546                                                 clocks = <&clk_uart_pll_mux>;
 547                                                 clock-output-names = "clk_uart0_div";
 548                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 549                                                 #clock-cells = <0>;
 550                                         };
 551
 552                                         /* reg[7]: reserved */
 553
 554                                         clk_uart0: clk_uart0_mux {
 555                                                 compatible = "rockchip,rk3188-mux-con";
 556                                                 rockchip,bits = <8 2>;
 557                                                 clocks = <&clk_uart0_div>, <&clk_uart0_frac>,
 558                                                        <&xin24m>;
 559                                                 rockchip,clkops-idx =
 560                                                         <CLKOPS_RATE_UART>;
 561                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 562                                                 clock-output-names = "clk_uart0";
 563                                                 #clock-cells = <0>;
 564                                         };
 565
 566                                         /* reg[15:10]: reserved */
 567
 568                                 };
 569
 570                                 clk_sel_con14: sel-con@007c {
 571                                         compatible = "rockchip,rk3188-selcon";
 572                                         reg = <0x007c 0x4>;
 573                                         #address-cells = <1>;
 574                                         #size-cells = <1>;
 575
 576                                         clk_uart1_div: clk_uart1_div {
 577                                                 compatible = "rockchip,rk3188-div-con";
 578                                                 rockchip,bits = <0 7>;
 579                                                 clocks = <&clk_uart_pll_mux>;
 580                                                 clock-output-names = "clk_uart1_div";
 581                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 582                                                 #clock-cells = <0>;
 583                                         };
 584
 585                                         /* reg[7]: reserved */
 586
 587                                         clk_uart1: clk_uart1_mux {
 588                                                 compatible = "rockchip,rk3188-mux-con";
 589                                                 rockchip,bits = <8 2>;
 590                                                 clocks = <&clk_uart1_div>, <&clk_uart1_frac>,
 591                                                        <&xin24m>;
 592                                                 rockchip,clkops-idx =
 593                                                         <CLKOPS_RATE_UART>;
 594                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 595                                                 clock-output-names = "clk_uart1";
 596                                                 #clock-cells = <0>;
 597                                         };
 598
 599                                         /* reg[15:10]: reserved */
 600
 601                                 };
 602
 603                                 clk_sel_con15: sel-con@0080 {
 604                                         compatible = "rockchip,rk3188-selcon";
 605                                         reg = <0x0080 0x4>;
 606                                         #address-cells = <1>;
 607                                         #size-cells = <1>;
 608
 609                                         clk_uart2_div: clk_uart2_div {
 610                                                 compatible = "rockchip,rk3188-div-con";
 611                                                 rockchip,bits = <0 7>;
 612                                                 clocks = <&clk_uart_pll_mux>;
 613                                                 clock-output-names = "clk_uart2_div";
 614                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 615                                                 #clock-cells = <0>;
 616                                         };
 617
 618                                         /* reg[7]: reserved */
 619
 620                                         clk_uart2: clk_uart2_mux {
 621                                                 compatible = "rockchip,rk3188-mux-con";
 622                                                 rockchip,bits = <8 2>;
 623                                                 clocks = <&clk_uart2_div>, <&clk_uart2_frac>,
 624                                                        <&xin24m>;
 625                                                 rockchip,clkops-idx =
 626                                                         <CLKOPS_RATE_UART>;
 627                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 628                                                 clock-output-names = "clk_uart2";
 629                                                 #clock-cells = <0>;
 630                                         };
 631
 632                                         /* reg[15:10]: reserved */
 633
 634                                 };
 635
 636                                 clk_sel_con16: sel-con@0084 {
 637                                         compatible = "rockchip,rk3188-selcon";
 638                                         reg = <0x0084 0x4>;
 639                                         #address-cells = <1>;
 640                                         #size-cells = <1>;
 641
 642                                         clk_uart3_div: clk_uart3_div {
 643                                                 compatible = "rockchip,rk3188-div-con";
 644                                                 rockchip,bits = <0 7>;
 645                                                 clocks = <&clk_uart_pll_mux>;
 646                                                 clock-output-names = "clk_uart3_div";
 647                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 648                                                 #clock-cells = <0>;
 649                                         };
 650
 651                                         /* reg[7]: reserved */
 652
 653                                         clk_uart3: clk_uart3_mux {
 654                                                 compatible = "rockchip,rk3188-mux-con";
 655                                                 rockchip,bits = <8 2>;
 656                                                 clocks = <&clk_uart3_div>, <&clk_uart3_frac>,
 657                                                        <&xin24m>;
 658                                                 rockchip,clkops-idx =
 659                                                         <CLKOPS_RATE_UART>;
 660                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 661                                                 clock-output-names = "clk_uart3";
 662                                                 #clock-cells = <0>;
 663                                         };
 664
 665                                         /* reg[15:10]: reserved */
 666
 667                                 };
 668
 669                                 clk_sel_con17: sel-con@0088 {
 670                                         compatible = "rockchip,rk3188-selcon";
 671                                         reg = <0x0088 0x4>;
 672                                         #address-cells = <1>;
 673                                         #size-cells = <1>;
 674                                         clk_uart0_frac: clk_uart0_frac {
 675                                                 compatible = "rockchip,rk3188-frac-con";
 676                                                 clocks = <&clk_uart0_div>;
 677                                                 clock-output-names = "clk_uart0_frac";
 678                                                 /* numerator    denominator */
 679                                                 rockchip,bits = <0 32>;
 680                                                 rockchip,clkops-idx =
 681                                                         <CLKOPS_RATE_FRAC>;
 682                                                 #clock-cells = <0>;
 683                                         };
 684                                 };
 685                                 clk_sel_con18: sel-con@008c {
 686                                         compatible = "rockchip,rk3188-selcon";
 687                                         reg = <0x008c 0x4>;
 688                                         #address-cells = <1>;
 689                                         #size-cells = <1>;
 690                                         clk_uart1_frac: clk_uart1_frac {
 691                                                 compatible = "rockchip,rk3188-frac-con";
 692                                                 clocks = <&clk_uart1_div>;
 693                                                 clock-output-names = "clk_uart1_frac";
 694                                                 /* numerator    denominator */
 695                                                 rockchip,bits = <0 32>;
 696                                                 rockchip,clkops-idx =
 697                                                         <CLKOPS_RATE_FRAC>;
 698                                                 #clock-cells = <0>;
 699                                         };
 700                                 };
 701                                 clk_sel_con19: sel-con@0090 {
 702                                         compatible = "rockchip,rk3188-selcon";
 703                                         reg = <0x0090 0x4>;
 704                                         #address-cells = <1>;
 705                                         #size-cells = <1>;
 706                                         clk_uart2_frac: clk_uart2_frac {
 707                                                 compatible = "rockchip,rk3188-frac-con";
 708                                                 clocks = <&clk_uart2_div>;
 709                                                 clock-output-names = "clk_uart2_frac";
 710                                                 /* numerator    denominator */
 711                                                 rockchip,bits = <0 32>;
 712                                                 rockchip,clkops-idx =
 713                                                         <CLKOPS_RATE_FRAC>;
 714                                                 #clock-cells = <0>;
 715                                         };
 716                                 };
 717                                 clk_sel_con20: sel-con@0094 {
 718                                         compatible = "rockchip,rk3188-selcon";
 719                                         reg = <0x0094 0x4>;
 720                                         #address-cells = <1>;
 721                                         #size-cells = <1>;
 722                                         clk_uart3_frac: clk_uart3_frac {
 723                                                 compatible = "rockchip,rk3188-frac-con";
 724                                                 clocks = <&clk_uart3_div>;
 725                                                 clock-output-names = "clk_uart3_frac";
 726                                                 /* numerator    denominator */
 727                                                 rockchip,bits = <0 32>;
 728                                                 rockchip,clkops-idx =
 729                                                         <CLKOPS_RATE_FRAC>;
 730                                                 #clock-cells = <0>;
 731                                         };
 732                                 };
 733
 734                                 clk_sel_con21: sel-con@0098 {
 735                                         compatible = "rockchip,rk3188-selcon";
 736                                         reg = <0x0098 0x4>;
 737                                         #address-cells = <1>;
 738                                         #size-cells = <1>;
 739
 740                                         clk_mac_pll_mux: clk_mac_pll_mux {
 741                                                 compatible = "rockchip,rk3188-mux-con";
 742                                                 rockchip,bits = <0 1>;
 743                                                 clocks = <&clk_gpll>, <&clk_dpll>;
 744                                                 clock-output-names = "clk_mac_pll";
 745                                                 #clock-cells = <0>;
 746                                         };
 747
 748                                         /* reg[3:1]: reserved */
 749
 750                                         clk_mac: clk_mac_mux {
 751                                                 compatible = "rockchip,rk3188-mux-con";
 752                                                 rockchip,bits = <4 1>;
 753                                                 clocks = <&clk_mac_pll_mux>, <&rmii_clkin>;
 754                                                 rockchip,clkops-idx =
 755                                                         <CLKOPS_RATE_MAC_REF>;
 756                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 757                                                 clock-output-names = "clk_mac";
 758                                                 #clock-cells = <0>;
 759                                         };
 760
 761                                         /* reg[7:5]: reserved */
 762
 763                                         clk_mac_pll_div: clk_mac_pll_div {
 764                                                 compatible = "rockchip,rk3188-div-con";
 765                                                 rockchip,bits = <8 5>;
 766                                                 clocks = <&clk_mac_pll_mux>;
 767                                                 clock-output-names = "clk_mac_pll";
 768                                                 rockchip,clkops-idx =
 769                                                         <CLKOPS_RATE_MUX_DIV>;
 770                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 771                                                 #clock-cells = <0>;
 772                                         };
 773
 774                                         /* reg[15:13]: reserved */
 775                                 };
 776
 777                                 clk_sel_con22: sel-con@009c {
 778                                         compatible = "rockchip,rk3188-selcon";
 779                                         reg = <0x009c 0x4>;
 780                                         #address-cells = <1>;
 781                                         #size-cells = <1>;
 782
 783                                         clk_hsadc_pll_mux: clk_hsadc_pll_mux {
 784                                                 compatible = "rockchip,rk3188-mux-con";
 785                                                 rockchip,bits = <0 1>;
 786                                                 clocks = <&clk_gpll>, <&clk_cpll>;
 787                                                 clock-output-names = "clk_hsadc_pll";
 788                                                 #clock-cells = <0>;
 789                                         };
 790
 791                                         /* reg[3:1]: reserved */
 792
 793                                         clk_hsadc: clk_hsadc_mux {
 794                                                 compatible = "rockchip,rk3188-mux-con";
 795                                                 rockchip,bits = <4 2>;
 796                                                 clocks = <&clk_hsadc_pll_mux>, <&clk_hsadc_frac>,
 797                                                          <&clk_hsadc_ext>;
 798                                                 rockchip,clkops-idx =
 799                                                         <CLKOPS_RATE_HSADC>;
 800                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 801                                                 clock-output-names = "clk_hsadc";
 802                                                 #clock-cells = <0>;
 803                                         };
 804
 805                                         /* reg[6]: reserved */
 806
 807                                         clk_hsadc_inv: clk_hsadc_inv {
 808                                                 compatible = "rockchip,rk3188-inv-con";
 809                                                 rockchip,bits = <7 1>;
 810                                                 clocks = <&clk_hsadc>;
 811                                         };
 812
 813                                         clk_hsadc_div: clk_hsadc_div {
 814                                                 compatible = "rockchip,rk3188-div-con";
 815                                                 rockchip,bits = <8 8>;
 816                                                 clocks = <&clk_hsadc_pll_mux>;
 817                                                 clock-output-names = "clk_hsadc_pll";
 818                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 819                                                 #clock-cells = <0>;
 820                                         };
 821                                 };
 822
 823                                 clk_sel_con23: sel-con@00a0 {
 824                                         compatible = "rockchip,rk3188-selcon";
 825                                         reg = <0x00a0 0x4>;
 826                                         #address-cells = <1>;
 827                                         #size-cells = <1>;
 828
 829                                         clk_hsadc_frac: clk_hsadc_frac{
 830                                                 compatible = "rockchip,rk3188-frac-con";
 831                                                 clocks = <&clk_hsadc_pll_mux>;
 832                                                 clock-output-names = "clk_hsadc_frac";
 833                                                 /* numerator    denominator */
 834                                                 rockchip,bits = <0 32>;
 835                                                 rockchip,clkops-idx =
 836                                                         <CLKOPS_RATE_FRAC>;
 837                                                 #clock-cells = <0>;
 838                                         };
 839                                 };
 840
 841                                 clk_sel_con24: sel-con@00a4 {
 842                                         compatible = "rockchip,rk3188-selcon";
 843                                         reg = <0x00a4 0x4>;
 844                                         #address-cells = <1>;
 845                                         #size-cells = <1>;
 846                                         clk_saradc: clk_saradc_div {
 847                                                 compatible = "rockchip,rk3188-div-con";
 848                                                 rockchip,bits = <8 8>;
 849                                                 clocks = <&xin24m>;
 850                                                 clock-output-names = "clk_saradc";
 851                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 852                                                 #clock-cells = <0>;
 853                                         };
 854                                 };
 855
 856                                 clk_sel_con25: sel-con@00a8 {
 857                                         compatible = "rockchip,rk3188-selcon";
 858                                         reg = <0x00a8 0x4>;
 859                                         #address-cells = <1>;
 860                                         #size-cells = <1>;
 861
 862                                         clk_spi0: clk_spi0_div {
 863                                                 compatible = "rockchip,rk3188-div-con";
 864                                                 rockchip,bits = <0 7>;
 865                                                 clocks = <&pclk_peri>;
 866                                                 clock-output-names = "clk_spi0";
 867                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 868                                                 #clock-cells = <0>;
 869                                         };
 870                                         /* reg[7]: reserved */
 871                                         clk_spi1: clk_spi1_div {
 872                                                 compatible = "rockchip,rk3188-div-con";
 873                                                 rockchip,bits = <8 7>;
 874                                                 clocks = <&pclk_peri>;
 875                                                 clock-output-names = "clk_spi1";
 876                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 877                                                 #clock-cells = <0>;
 878                                         };
 879                                         /* reg[15]: reserved */
 880                                 };
 881
 882                                 clk_sel_con26: sel-con@00ac {
 883                                         compatible = "rockchip,rk3188-selcon";
 884                                         reg = <0x00ac 0x4>;
 885                                         #address-cells = <1>;
 886                                         #size-cells = <1>;
 887
 888                                         clk_ddr_div: clk_ddr_div {
 889                                                 compatible = "rockchip,rk3188-div-con";
 890                                                 rockchip,bits = <0 2>;
 891                                                 clocks = <&clk_ddr>;
 892                                                 clock-output-names = "clk_ddr";
 893                                                 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
 894                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
 895                                                 #clock-cells = <0>;
 896                                         };
 897
 898                                         /* reg[7:2]: reserved */
 899
 900                                         clk_ddr: clk_ddr_mux {
 901                                                 compatible = "rockchip,rk3188-mux-con";
 902                                                 rockchip,bits = <8 1>;
 903                                                 clocks = <&clk_dpll>,
 904                                                        <&clk_gates1 7>;
 905                                                 clock-output-names = "clk_ddr";
 906                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 907                                                                         CLK_SET_RATE_NO_REPARENT)>;
 908                                                 #clock-cells = <0>;
 909                                         };
 910
 911                                         /* reg[15:9]: reserved */
 912                                 };
 913
 914                                 clk_sel_con27: sel-con@00b0 {
 915                                         compatible = "rockchip,rk3188-selcon";
 916                                         reg = <0x00b0 0x4>;
 917                                         #address-cells = <1>;
 918                                         #size-cells = <1>;
 919
 920                                         dclk_lcdc0: dclk_lcdc0_mux {
 921                                                 compatible = "rockchip,rk3188-mux-con";
 922                                                 rockchip,bits = <0 1>;
 923                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 924                                                 clock-output-names = "dclk_lcdc0";
 925                                                 #clock-cells = <0>;
 926                                         };
 927
 928                                         /* reg[7:1]: reserved */
 929
 930                                         dclk_lcdc0_div: dclk_lcdc0_div {
 931                                                 compatible = "rockchip,rk3188-div-con";
 932                                                 rockchip,bits = <8 8>;
 933                                                 clocks = <&dclk_lcdc0>;
 934                                                 clock-output-names = "dclk_lcdc0";
 935                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 936                                                 rockchip,clkops-idx =
 937                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 938                                                 #clock-cells = <0>;
 939                                         };
 940                                 };
 941
 942
 943                                 clk_sel_con28: sel-con@00b4 {
 944                                         compatible = "rockchip,rk3188-selcon";
 945                                         reg = <0x00b4 0x4>;
 946                                         #address-cells = <1>;
 947                                         #size-cells = <1>;
 948
 949                                         dclk_lcdc1: dclk_lcdc1_mux {
 950                                                 compatible = "rockchip,rk3188-mux-con";
 951                                                 rockchip,bits = <0 1>;
 952                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 953                                                 clock-output-names = "dclk_lcdc1";
 954                                                 #clock-cells = <0>;
 955                                         };
 956
 957                                         /* reg[7:1]: reserved */
 958
 959                                         dclk_lcdc1_div: dclk_lcdc1_div {
 960                                                 compatible = "rockchip,rk3188-div-con";
 961                                                 rockchip,bits = <8 8>;
 962                                                 clocks = <&dclk_lcdc1>;
 963                                                 clock-output-names = "dclk_lcdc1";
 964                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 965                                                 rockchip,clkops-idx =
 966                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 967                                                 #clock-cells = <0>;
 968                                         };
 969                                 };
 970
 971                                 clk_sel_con29: sel-con@00b8 {
 972                                         compatible = "rockchip,rk3188-selcon";
 973                                         reg = <0x00b8 0x4>;
 974                                         #address-cells = <1>;
 975                                         #size-cells = <1>;
 976
 977                                         cif_out_pll_mux: cif_out_pll_mux {
 978                                                 compatible = "rockchip,rk3188-mux-con";
 979                                                 rockchip,bits = <0 1>;
 980                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 981                                                 clock-output-names = "cif_out_pll";
 982                                                 #clock-cells = <0>;
 983                                         };
 984
 985                                         cif0_out_div: cif0_out_div {
 986                                                 compatible = "rockchip,rk3188-div-con";
 987                                                 rockchip,bits = <1 5>;
 988                                                 clocks = <&cif_out_pll_mux>;
 989                                                 clock-output-names = "cif_out_pll";
 990                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 991                                                 rockchip,clkops-idx =
 992                                                         <CLKOPS_RATE_MUX_DIV>;
 993                                                 #clock-cells = <0>;
 994                                         };
 995
 996                                         /* reg[6]: reserved */
 997
 998                                         clk_cif0: cif0_out_mux {
 999                                                 compatible = "rockchip,rk3188-mux-con";
1000                                                 rockchip,bits = <7 1>;
1001                                                 clocks = <&cif_out_pll_mux>, <&xin24m>;
1002                                                 rockchip,clkops-idx =
1003                                                         <CLKOPS_RATE_CIFOUT>;
1004                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1005                                                 clock-output-names = "clk_cif0";
1006                                                 #clock-cells = <0>;
1007                                         };
1008
1009                                         /* reg[15:8]: reserved */
1010                                 };
1011
1012                                 clk_sel_con30: sel-con@00bc {
1013                                         compatible = "rockchip,rk3188-selcon";
1014                                         reg = <0x00bc 0x4>;
1015                                         #address-cells = <1>;
1016                                         #size-cells = <1>;
1017
1018                                         clk_ehci1phy480m: clk_ehci1phy480m_mux {
1019                                                 compatible = "rockchip,rk3188-mux-con";
1020                                                 rockchip,bits = <0 2>;
1021                                                 clocks = <&otgphy0_480m>, <&otgphy1_480m>,
1022                                                          <&clk_gpll>, <&clk_cpll>;
1023                                                 clock-output-names = "clk_ehci1phy480m";
1024                                                 #clock-cells = <0>;
1025                                         };
1026
1027                                         /* reg[7:2]: reserved */
1028
1029                                         /* inv here?????? */
1030
1031                                         /* reg[15:9]: reserved */
1032                                 };
1033
1034                                 clk_sel_con31: sel-con@00c0 {
1035                                         compatible = "rockchip,rk3188-selcon";
1036                                         reg = <0x00c0 0x4>;
1037                                         #address-cells = <1>;
1038                                         #size-cells = <1>;
1039
1040                                         aclk_lcdc0_pre_div: aclk_lcdc0_pre_div {
1041                                                 compatible = "rockchip,rk3188-div-con";
1042                                                 rockchip,bits = <0 5>;
1043                                                 clocks = <&aclk_lcdc0>;
1044                                                 clock-output-names = "aclk_lcdc0";
1045                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1046                                                 rockchip,clkops-idx =
1047                                                         <CLKOPS_RATE_MUX_DIV>;
1048                                                 #clock-cells = <0>;
1049                                         };
1050
1051                                         /* reg[6:5]: reserved */
1052
1053                                         aclk_lcdc0: aclk_lcdc0_pre_mux {
1054                                                 compatible = "rockchip,rk3188-mux-con";
1055                                                 rockchip,bits = <7 1>;
1056                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1057                                                 clock-output-names = "aclk_lcdc0";
1058                                                 #clock-cells = <0>;
1059                                                 #clock-init-cells = <1>;
1060                                         };
1061
1062                                         aclk_lcdc1_pre_div: aclk_lcdc1_pre_div {
1063                                                 compatible = "rockchip,rk3188-div-con";
1064                                                 rockchip,bits = <8 5>;
1065                                                 clocks = <&aclk_lcdc1>;
1066                                                 clock-output-names = "aclk_lcdc1";
1067                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1068                                                 rockchip,clkops-idx =
1069                                                         <CLKOPS_RATE_MUX_DIV>;
1070                                                 #clock-cells = <0>;
1071                                         };
1072
1073                                         /* reg[14:13]: reserved */
1074
1075                                         aclk_lcdc1: aclk_lcdc1_pre_mux {
1076                                                 compatible = "rockchip,rk3188-mux-con";
1077                                                 rockchip,bits = <15 1>;
1078                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1079                                                 clock-output-names = "aclk_lcdc1";
1080                                                 #clock-cells = <0>;
1081                                                 #clock-init-cells = <1>;
1082                                         };
1083                                 };
1084
1085                                 clk_sel_con32: sel-con@00c4 {
1086                                         compatible = "rockchip,rk3188-selcon";
1087                                         reg = <0x00c4 0x4>;
1088                                         #address-cells = <1>;
1089                                         #size-cells = <1>;
1090
1091                                         aclk_vepu_div: aclk_vepu_div {
1092                                                 compatible = "rockchip,rk3188-div-con";
1093                                                 rockchip,bits = <0 5>;
1094                                                 clocks = <&clk_vepu>;
1095                                                 clock-output-names = "clk_vepu";
1096                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1097                                                 rockchip,clkops-idx =
1098                                                         <CLKOPS_RATE_MUX_DIV>;
1099                                                 #clock-cells = <0>;
1100                                         };
1101
1102                                         /* reg[6:5]: reserved */
1103
1104                                         clk_vepu: aclk_vepu_mux {
1105                                                 compatible = "rockchip,rk3188-mux-con";
1106                                                 rockchip,bits = <7 1>;
1107                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1108                                                 clock-output-names = "clk_vepu";
1109                                                 #clock-cells = <0>;
1110                                         };
1111
1112                                         aclk_vdpu_div: aclk_vdpu_div {
1113                                                 compatible = "rockchip,rk3188-div-con";
1114                                                 rockchip,bits = <8 5>;
1115                                                 clocks = <&clk_vdpu>;
1116                                                 clock-output-names = "clk_vdpu";
1117                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1118                                                 rockchip,clkops-idx =
1119                                                         <CLKOPS_RATE_MUX_DIV>;
1120                                                 #clock-cells = <0>;
1121                                         };
1122
1123                                         /* reg[14:13]: reserved */
1124
1125                                         clk_vdpu: aclk_vdpu_mux {
1126                                                 compatible = "rockchip,rk3188-mux-con";
1127                                                 rockchip,bits = <15 1>;
1128                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1129                                                 clock-output-names = "clk_vdpu";
1130                                                 #clock-cells = <0>;
1131                                         };
1132                                 };
1133
1134                                 clk_sel_con34: sel-con@00cc {
1135                                         compatible = "rockchip,rk3188-selcon";
1136                                         reg = <0x00cc 0x4>;
1137                                         #address-cells = <1>;
1138                                         #size-cells = <1>;
1139
1140                                         aclk_gpu_div: aclk_gpu_div {
1141                                                 compatible = "rockchip,rk3188-div-con";
1142                                                 rockchip,bits = <0 5>;
1143                                                 clocks = <&clk_gpu>;
1144                                                 clock-output-names = "clk_gpu";
1145                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1146                                                 rockchip,clkops-idx =
1147                                                         <CLKOPS_RATE_MUX_DIV>;
1148                                                 #clock-cells = <0>;
1149                                         };
1150
1151                                         /* reg[6:5]: reserved */
1152
1153                                         clk_gpu: aclk_gpu_mux {
1154                                                 compatible = "rockchip,rk3188-mux-con";
1155                                                 rockchip,bits = <7 1>;
1156                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1157                                                 clock-output-names = "clk_gpu";
1158                                                 #clock-cells = <0>;
1159                                                 #clock-init-cells = <1>;
1160                                         };
1161
1162                                         /* reg[15:8]: reserved */
1163                                 };
1164                         };
1165
1166                         /* Gate control regs */
1167                         clk_gate_cons {
1168                                 compatible = "rockchip,rk-gate-cons";
1169                                 #address-cells = <1>;
1170                                 #size-cells = <1>;
1171                                 ranges ;
1172
1173                                 clk_gates0: gate-clk@00d0 {
1174                                         compatible = "rockchip,rk3188-gate-clk";
1175                                         reg = <0x00d0 0x4>;
1176                                         clocks = <&clk_core_peri>,      <&clk_gpll>,
1177                                                  <&clk_dpll>,           <&aclk_cpu>,
1178
1179                                                  <&hclk_cpu>,           <&pclk_cpu>,
1180                                                  <&pclk_cpu>,           <&aclk_core>,
1181
1182                                                  <&dummy>,              <&clk_i2s_div>,
1183                                                  <&clk_i2s_frac>,       <&dummy>,
1184
1185                                                  <&dummy>,              <&clk_spdif_div>,
1186                                                  <&clk_spdif_frac>,     <&dummy>;
1187
1188                                         clock-output-names =
1189                                                 "clk_core_peri",        "clk_arm_gpll",
1190                                                 "clk_dpll",             "aclk_cpu",
1191
1192                                                 "hclk_cpu",             "pclk_cpu",
1193                                                 "g_atclk_cpu",          "aclk_core",
1194
1195                                                 "reserved",             "clk_i2s_div",
1196                                                 "clk_i2s_frac",         "reserved",
1197
1198                                                 "reserved",             "clk_spdif_div",
1199                                                 "clk_spdif_frac",       "g_testclk";
1200                                                 rockchip,suspend-clkgating-setting=<0x00bf 0x00bf>;
1201
1202                                         #clock-cells = <1>;
1203                                 };
1204
1205                                 clk_gates1: gate-clk@00d4 {
1206                                         compatible = "rockchip,rk3188-gate-clk";
1207                                         reg = <0x00d4 0x4>;
1208                                         clocks = <&xin24m>,             <&xin24m>,
1209                                                  <&xin24m>,             <&dummy>,
1210
1211                                                  <&aclk_lcdc1>,         <&xin24m>,
1212                                                  <&xin24m>,             <&clk_gpll>,
1213
1214                                                  <&clk_uart0_div>,      <&clk_uart0_frac>,
1215                                                  <&clk_uart1_div>,      <&clk_uart1_frac>,
1216
1217                                                  <&clk_uart2_div>,      <&clk_uart2_frac>,
1218                                                  <&clk_uart3_div>,      <&clk_uart3_frac>;
1219
1220                                         clock-output-names =
1221                                                 "timer0",               "timer1",
1222                                                 "timer3",               "g_jtag",
1223
1224                                                 "aclk_lcdc1",           "g_otgphy0",
1225                                                 "g_otgphy1",            "clk_ddr_gpll",
1226
1227                                                 "clk_uart0_div",        "clk_uart0_frac",
1228                                                 "clk_uart1_div",        "clk_uart1_frac",
1229
1230                                                 "clk_uart2_div",        "clk_uart2_frac",
1231                                                 "clk_uart3_div",        "clk_uart3_frac";
1232                                                 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1233
1234                                         #clock-cells = <1>;
1235                                 };
1236
1237                                 clk_gates2: gate-clk@00d8 {
1238                                         compatible = "rockchip,rk3188-gate-clk";
1239                                         reg = <0x00d8 0x4>;
1240                                         clocks = <&aclk_peri>,  <&aclk_peri>,
1241                                                  <&hclk_peri>,          <&pclk_peri>,
1242
1243                                                  <&hclk_peri>,          <&clk_mac_pll_mux>,
1244                                                  <&clk_hsadc_pll_mux>,  <&clk_hsadc_frac>,
1245
1246                                                  <&clk_saradc>,         <&clk_spi0>,
1247                                                  <&clk_spi1>,           <&clk_sdmmc>,
1248
1249                                                  <&dummy>,              <&clk_sdio>,
1250                                                  <&clk_emmc>,           <&dummy>;
1251
1252                                         clock-output-names =
1253                                                 "aclk_peri",            "g_aclk_peri",
1254                                                 "hclk_peri",            "pclk_peri",
1255
1256                                                 "g_smc_src",            "clk_mac_pll",
1257                                                 "clk_hsadc_pll",        "clk_hsadc_frac",
1258
1259                                                 "clk_saradc",           "clk_spi0",
1260                                                 "clk_spi1",             "clk_sdmmc",
1261
1262                                                 "g_mac_lbtest",         "clk_sdio",
1263                                                 "clk_emmc",             "reserved";
1264                                                 //rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
1265                                                 rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
1266
1267                                         #clock-cells = <1>;
1268                                 };
1269
1270                                 clk_gates3: gate-clk@00dc {
1271                                         compatible = "rockchip,rk3188-gate-clk";
1272                                         reg = <0x00dc 0x4>;
1273                                         clocks = <&aclk_lcdc0>,         <&dclk_lcdc0>,
1274                                                  <&dclk_lcdc1>,         <&clk_cif_in>,
1275
1276                                                  <&xin24m>,                     <&xin24m>,
1277                                                  <&clk_ehci1phy480m>,   <&clk_cif0>,
1278
1279                                                  <&xin24m>,             <&clk_vepu>,
1280                                                  <&clk_vepu>,           <&clk_vdpu>,
1281
1282                                                  <&clk_vdpu>,           <&dummy>,
1283                                                  <&xin24m>,             <&clk_gpu>;
1284
1285                                         clock-output-names =
1286                                                 "aclk_lcdc0",           "dclk_lcdc0",
1287                                                 "dclk_lcdc1",           "g_clk_cif_in",
1288
1289                                                 /*
1290                                                  * FIXME: cif_out_pll can be set to
1291                                                  * clk_cif as virtual
1292                                                  */
1293                                                 "timer2",               "timer4",
1294                                                 "clk_ehci1phy480m",     "clk_cif0",
1295
1296                                                 "timer5",               "clk_vepu",
1297                                                 "g_h_vepu",             "clk_vdpu",
1298
1299                                                 "g_h_vdpu",             "reserved",
1300                                                 "timer6",               "clk_gpu";
1301                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1302
1303                                         #clock-cells = <1>;
1304                                 };
1305
1306                                 clk_gates4: gate-clk@00e0 {
1307                                         compatible = "rockchip,rk3188-gate-clk";
1308                                         reg = <0x00e0 0x4>;
1309                                         clocks = <&hclk_peri>,          <&pclk_peri>,
1310                                                  <&aclk_peri>,          <&aclk_peri>,
1311
1312                                                  <&aclk_peri>,          <&hclk_peri>,
1313                                                  <&hclk_peri>,          <&hclk_peri>,
1314
1315                                                  <&hclk_cpu>,           <&hclk_cpu>,
1316                                                  <&aclk_cpu>,           <&dummy>,
1317
1318                                                  <&aclk_cpu>,           <&dummy>,
1319                                                  <&hclk_cpu>,           <&hclk_cpu>;
1320
1321                                         /*
1322                                          * g_ap: gate_aclk_peri_...
1323                                          * g_hp: gate_hclk_peri_...
1324                                          * g_pp: gate_pclk_peri_...
1325                                          */
1326                                         clock-output-names =
1327                                                 "g_hp_axi_matrix",      "g_pp_axi_matrix",
1328                                                 "g_a_cpu_peri",         "g_ap_axi_matrix",
1329
1330                                                 "g_a_peri_niu",         "g_h_usb_peri",
1331                                                 "g_hp_ahb_arbi",        "g_h_emem_peri",
1332
1333                                                 "g_h_cpubus",           "g_h_ahb2apb",
1334                                                 "g_a_strc_sys",         "reserved",
1335
1336                                                 "g_a_intmem",           "reserved",
1337                                                 "g_h_imem1",            "g_h_imem0";
1338
1339                                         //rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
1340                                         rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
1341                                         #clock-cells = <1>;
1342                                 };
1343
1344                                 clk_gates5: gate-clk@00e4 {
1345                                         compatible = "rockchip,rk3188-gate-clk";
1346                                         reg = <0x00e4 0x4>;
1347                                         clocks = <&aclk_cpu>,           <&aclk_peri>,
1348                                                  <&pclk_cpu>,           <&pclk_cpu>,
1349
1350                                                  <&pclk_cpu>,           <&pclk_cpu>,
1351                                                  <&hclk_cpu>,           <&pclk_cpu>,
1352
1353                                                  <&aclk_peri>,          <&hclk_peri>,
1354                                                  <&hclk_peri>,          <&hclk_peri>,
1355
1356                                                  <&hclk_peri>,          <&hclk_peri>;
1357
1358                                         clock-output-names =
1359                                                 "g_a_dmac1",            "g_a_dmac2",
1360                                                 "g_p_efuse",            "g_p_tzpc",
1361
1362                                                 "g_p_grf",              "g_p_pmu",
1363                                                 "g_h_rom",              "g_p_ddrupctl",
1364
1365                                                 "g_a_smc",              "g_h_nandc",
1366                                                 "g_h_sdmmc0",           "g_h_sdio",
1367
1368                                                 "g_h_emmc",             "g_h_otg0";
1369                                         rockchip,suspend-clkgating-setting=<0x80 0x80>;
1370
1371                                         #clock-cells = <1>;
1372                                 };
1373
1374                                 clk_gates6: gate-clk@00e8 {
1375                                         compatible = "rockchip,rk3188-gate-clk";
1376                                         reg = <0x00e8 0x4>;
1377                                         clocks = <&clk_gates6 13>,      <&hclk_cpu>,
1378                                                  <&hclk_cpu>,           <&clk_gates9 5>,
1379
1380                                                  <&hclk_cpu>,           <&clk_gates6 13>,
1381                                                  <&dummy>,              <&dummy>,
1382
1383                                                  <&clk_gates6 13>,      <&hclk_cpu>,
1384                                                  <&hclk_cpu>,           <&clk_gates9 5>,
1385
1386                                                  <&hclk_cpu>,           <&aclk_lcdc0>;
1387
1388                                         clock-output-names =
1389                                                 "g_a_lcdc0",            "g_h_lcdc0",
1390                                                 "g_h_lcdc1",            "g_a_lcdc1",
1391
1392                                                 "g_h_cif0",             "g_a_cif0",
1393                                                 "reserved",             "reserved",
1394
1395                                                 "g_a_ipp",              "g_h_ipp",
1396                                                 "g_h_rga",              "g_a_rga",
1397
1398                                                 "g_h_vio_bus",          "g_a_vio0";
1399
1400                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1401                                         #clock-cells = <1>;
1402                                 };
1403
1404                                 clk_gates7: gate-clk@00ec {
1405                                         compatible = "rockchip,rk3188-gate-clk";
1406                                         reg = <0x00ec 0x4>;
1407                                         clocks = <&hclk_peri>,          <&hclk_cpu>,
1408                                                  <&hclk_cpu>,           <&hclk_peri>,
1409
1410                                                  <&hclk_peri>,          <&hclk_peri>,
1411                                                  <&hclk_peri>,          <&pclk_cpu>,
1412
1413                                                  <&dummy>,              <&pclk_cpu>,
1414                                                  <&pclk_cpu>,           <&pclk_peri>,
1415
1416                                                  <&pclk_peri>,          <&pclk_peri>,
1417                                                  <&pclk_peri>,          <&pclk_peri>;
1418
1419                                         clock-output-names =
1420                                                 "g_h_emac",             "g_h_spdif",
1421                                                 "g_h_i2s0_2ch",         "g_h_otg1",
1422
1423                                                 "g_h_ehci1",            "g_h_hsadc",
1424                                                 "g_h_pidf",             "g_p_timer0",
1425
1426                                                 "reserved",             "g_p_timer2",
1427                                                 "g_p_pwm01",            "g_p_pwm23",
1428
1429                                                 "g_p_spi0",             "g_p_spi1",
1430                                                 "g_p_saradc",           "g_p_wdt";
1431                                         rockchip,suspend-clkgating-setting=<0x0 0x0>;
1432
1433                                         #clock-cells = <1>;
1434                                 };
1435
1436                                 clk_gates8: gate-clk@00f0 {
1437                                         compatible = "rockchip,rk3188-gate-clk";
1438                                         reg = <0x00f0 0x4>;
1439                                         clocks = <&pclk_ahb2apb>,       <&pclk_ahb2apb>,
1440                                                  <&pclk_peri>,          <&pclk_peri>,
1441
1442                                                  <&pclk_cpu>,           <&pclk_cpu>,
1443                                                  <&pclk_peri>,          <&pclk_peri>,
1444
1445                                                  <&pclk_peri>,          <&pclk_cpu>,
1446                                                  <&pclk_cpu>,           <&pclk_cpu>,
1447
1448                                                  <&pclk_peri>,          <&aclk_peri>;
1449
1450                                         clock-output-names =
1451                                                 "g_p_uart0",            "g_p_uart1",
1452                                                 "g_p_uart2",            "g_p_uart3",
1453
1454                                                 "g_p_i2c0",             "g_p_i2c1",
1455                                                 "g_p_i2c2",             "g_p_i2c3",
1456
1457                                                 "g_p_i2c4",             "g_p_gpio0",
1458                                                 "g_p_gpio1",            "g_p_gpio2",
1459
1460                                                 "g_p_gpio3",            "g_a_gps";
1461                                                 rockchip,suspend-clkgating-setting=<0x200 0x200>;
1462
1463                                         #clock-cells = <1>;
1464                                 };
1465
1466                                 clk_gates9: gate-clk@00f4 {
1467                                         compatible = "rockchip,rk3188-gate-clk";
1468                                         reg = <0x00f4 0x4>;
1469                                         clocks = <&clk_core>,           <&pclk_cpu>,
1470                                                  <&clk_gates0 6>,       <&clk_gates0 6>,
1471
1472                                                  <&clk_core>,           <&aclk_lcdc1>,
1473                                                  <&pclk_cpu>,           <&clk_gpu>;
1474
1475                                         clock-output-names =
1476                                                 "g_clk_core_dbg",       "g_p_dbg",
1477                                                 "g_clk_trace",          "g_atclk",
1478
1479                                                 "g_clk_l2c",            "g_a_vio1",
1480                                                 "g_p_ddrpubl",          "g_a_gpu";
1481                                         rockchip,suspend-clkgating-setting=<0x50 0x50>;
1482
1483                                         #clock-cells = <1>;
1484                                 };
1485                         };
1486                 };
1487         };
1488 };