arch/arm/boot/dts/rk312x.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/sensor-dev.h>
   4 #include <dt-bindings/clock/rk_system_status.h>
   5 #include <dt-bindings/rkfb/rk_fb.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk312x-clocks.dtsi"
   9 #include "rk312x-pinctrl.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk312x";
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 serial1 = &uart1;
  19                 serial2 = &uart2;
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 lcdc = &lcdc;
  25                 spi0 = &spi0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <0xf00>;
  36                 };
  37                 cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0xf01>;
  41                 };
  42                 cpu@2 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a7";
  45                         reg = <0xf02>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         reg = <0xf03>;
  51                 };
  52         };
  53
  54         gic: interrupt-controller@10139000 {
  55                 compatible = "arm,cortex-a15-gic";
  56                 interrupt-controller;
  57                 #interrupt-cells = <3>;
  58                 #address-cells = <0>;
  59                 reg = <0x10139000 0x1000>,
  60                       <0x1013a000 0x1000>;
  61         };
  62
  63         arm-pmu {
  64                 compatible = "arm,cortex-a7-pmu";
  65                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  67                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  68                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  69         };
  70
  71         cpu_axi_bus: cpu_axi_bus {
  72                 compatible = "rockchip,cpu_axi_bus";
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 ranges;
  76
  77                 qos {
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         ranges;
  81
  82                         crypto {
  83                                 reg = <0x10128080 0x20>;
  84                         };
  85                         core {
  86                                 reg = <0x1012a000 0x20>;
  87                         };
  88                         peri {
  89                                 reg = <0x1012c000 0x20>;
  90                         };
  91                         gpu {
  92                                 reg = <0x1012d000 0x20>;
  93                         };
  94                         vpu {
  95                                 reg = <0x1012e000 0x20>;
  96                         };
  97                         rga {
  98                                 reg = <0x1012f000 0x20>;
  99                         };
 100                         ebc {
 101                                 reg = <0x1012f080 0x20>;
 102                         };
 103                         iep {
 104                                 reg = <0x1012f100 0x20>;
 105                         };
 106                         lcdc {
 107                                 reg = <0x1012f180 0x20>;
 108                                 rockchip,priority = <3 3>;
 109                         };
 110                         vip {
 111                                 reg = <0x1012f200 0x20>;
 112                                 rockchip,priority = <3 3>;
 113                         };
 114                 };
 115
 116                 msch {
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119                         ranges;
 120
 121                         msch@10128000 {
 122                                 reg = <0x10128000 0x20>;
 123                                 rockchip,read-latency = <0x3f>;
 124                         };
 125                 };
 126         };
 127
 128         sram: sram@10080400 {
 129                 compatible = "mmio-sram";
 130                 reg = <0x10080400 0x1C00>;
 131                 map-exec;
 132                 map-cacheable;
 133         };
 134
 135         timer {
 136                 compatible = "arm,armv7-timer";
 137                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 138                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 139                 clock-frequency = <24000000>;
 140         };
 141
 142         timer@20044000 {
 143                 compatible = "rockchip,timer";
 144                 reg = <0x20044000 0x20>;
 145                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 146                 rockchip,broadcast = <1>;
 147         };
 148
 149         watchdog: wdt@2004c000 {
 150                 compatible = "rockchip,watch dog";
 151                 reg = <0x2004c000 0x100>;
 152         //      clocks = <&clk_gates7 15>;
 153                 clock-names = "pclk_wdt";
 154                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 155                 rockchip,irq = <1>;
 156                 rockchip,timeout = <60>;
 157                 rockchip,atboot = <1>;
 158                 rockchip,debug = <0>;
 159                 status = "disabled";
 160         };
 161
 162         amba {
 163                 #address-cells = <1>;
 164                 #size-cells = <1>;
 165                 compatible = "arm,amba-bus";
 166                 interrupt-parent = <&gic>;
 167                 ranges;
 168
 169                 pdma: pdma@20078000 {
 170                         compatible = "arm,pl330", "arm,primecell";
 171                         reg = <0x20078000 0x4000>;
 172                         clocks = <&clk_gates5 1>;
 173                         clock-names = "apb_pclk";
 174                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 175                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 176                         #dma-cells = <1>;
 177                 };
 178         };
 179
 180         reset: reset@20000110 {
 181                 compatible = "rockchip,reset";
 182                 reg = <0x20000110 0x24>;
 183                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 184                 #reset-cells = <1>;
 185         };
 186
 187         nandc: nandc@10500000 {
 188                 compatible = "rockchip,rk-nandc";
 189                 reg = <0x10500000 0x4000>;
 190                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 191                 //pinctrl-names = "default";
 192                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 193                 nandc_id = <0>;
 194                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
 195                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 196         };
 197
 198         nandc0reg: nandc0@10500000 {
 199                 compatible = "rockchip,rk-nandc";
 200                 reg = <0x10500000 0x4000>;
 201         };
 202         uart0: serial@20060000 {
 203                 compatible = "rockchip,serial";
 204                 reg = <0x20060000 0x100>;
 205                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 206                 clock-frequency = <24000000>;
 207                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 208                 clock-names = "sclk_uart", "pclk_uart";
 209                 reg-shift = <2>;
 210                 reg-io-width = <4>;
 211                 dmas = <&pdma 2>, <&pdma 3>;
 212                 #dma-cells = <2>;
 213                 pinctrl-names = "default";
 214                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 215                 status = "disabled";
 216         };
 217
 218         uart1: serial@20064000 {
 219                 compatible = "rockchip,serial";
 220                 reg = <0x20064000 0x100>;
 221                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 222                 clock-frequency = <24000000>;
 223                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 224                 clock-names = "sclk_uart", "pclk_uart";
 225                 reg-shift = <2>;
 226                 reg-io-width = <4>;
 227                 dmas = <&pdma 4>, <&pdma 5>;
 228                 #dma-cells = <2>;
 229                 pinctrl-names = "default";
 230                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 231                 status = "disabled";
 232         };
 233
 234         uart2: serial@20068000 {
 235                 compatible = "rockchip,serial";
 236                 reg = <0x20068000 0x100>;
 237                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 238                 clock-frequency = <24000000>;
 239                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 240                 clock-names = "sclk_uart", "pclk_uart";
 241                 reg-shift = <2>;
 242                 reg-io-width = <4>;
 243                 dmas = <&pdma 6>, <&pdma 7>;
 244                 #dma-cells = <2>;
 245                 pinctrl-names = "default";
 246                 pinctrl-0 = <&uart2_xfer>;
 247                 status = "disabled";
 248         };
 249
 250         gmac: eth@2008c000 {
 251                 compatible = "rockchip,rk312x-gmac";
 252                 reg = <0x2008c000 0x4000>;
 253                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;  /*irq=88*/
 254                 interrupt-names = "macirq";
 255                 clocks = <&clk_mac_ref>, <&clk_gates2 6>,
 256                         <&clk_gates2 7>, <&clk_gates2 4>,
 257                         <&clk_gates2 5>, <&clk_gates10 10>,
 258                         <&clk_gates10 11>;
 259                 clock-names = "clk_mac", "mac_clk_rx",
 260                         "mac_clk_tx", "clk_mac_ref",
 261                         "clk_mac_refout", "aclk_mac",
 262                         "pclk_mac";
 263                 phy-mode = "rgmii";
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&gmac_rxdv &gmac_txclk &gmac_crs &gmac_rxclk &gmac_mdio &gmac_txen &gmac_clk &gmac_rxer &gmac_rxd1 &gmac_rxd0 &gmac_txd1 &gmac_txd0 &gmac_rxd3 &gmac_rxd2 &gmac_txd2 &gmac_txd3 &gmac_col_gpio &gmac_mdc>;
 266         };
 267
 268         fiq-debugger {
 269                 compatible = "rockchip,fiq-debugger";
 270                 rockchip,serial-id = <2>;
 271                 rockchip,signal-irq = <106>;
 272                 rockchip,wake-irq = <0>;
 273                 status = "disabled";
 274         };
 275
 276         rockchip_clocks_init: clocks-init{
 277                 compatible = "rockchip,clocks-init";
 278                 rockchip,clocks-init-parent =
 279                         <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
 280                         <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
 281                         <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
 282                         <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 283                         <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
 284                         <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
 285                         <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
 286                         <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll_div2>,
 287                         <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
 288                         <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
 289                         <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
 290                         <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
 291                         <&clk_mac_pll &clk_cpll>;
 292                 rockchip,clocks-init-rate =
 293                         <&clk_core 600000000>, <&clk_gpll 594000000>,
 294                         <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
 295                         <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
 296                         <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
 297                         <&pclk_peri_pre 75000000>, <&clk_gpu 300000000>,
 298                         <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
 299                         <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
 300                         <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
 301                         <&clk_mac_ref 125000000>;
 302         /*      rockchip,clocks-uboot-has-init =
 303                         <&aclk_vio1>;*/
 304         };
 305         gpu {
 306                 compatible = "arm,mali400";
 307                 reg = <0x10091000 0x200>,
 308                       <0x10090000 0x100>,
 309                       <0x10093000 0x100>,
 310                       <0x10098000 0x1100>,
 311                       <0x10094000 0x100>,
 312                       <0x1009A000 0x1100>,
 313                       <0x10095000 0x100>;
 314
 315                 reg-names = "Mali_L2",
 316                             "Mali_GP",
 317                             "Mali_GP_MMU",
 318                             "Mali_PP0",
 319                             "Mali_PP0_MMU",
 320                             "Mali_PP1",
 321                             "Mali_PP1_MMU";
 322
 323                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 328                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 329
 330                 interrupt-names = "Mali_GP_IRQ",
 331                                   "Mali_GP_MMU_IRQ",
 332                                   "Mali_PP0_IRQ",
 333                                   "Mali_PP0_MMU_IRQ",
 334                                   "Mali_PP1_IRQ",
 335                                   "Mali_PP1_MMU_IRQ";
 336           };
 337
 338         clocks-enable {
 339                 compatible = "rockchip,clocks-enable";
 340                 clocks =
 341                                 /*PD_CORE*/
 342                                 <&clk_gates0 6>,<&clk_gates0 0>,
 343                                 <&clk_gates0 7>,
 344
 345                                 /*PD_CPU*/
 346                                 <&clk_gates0 1>, <&clk_gates0 3>,
 347                                 <&clk_gates0 4>, <&clk_gates0 5>,
 348                                 <&clk_gates0 12>,
 349
 350                                 /*TIMER*/
 351                                 <&clk_gates10 3>, <&clk_gates10 4>,
 352                                 <&clk_gates10 5>, <&clk_gates10 6>,
 353                                 <&clk_gates10 7>, <&clk_gates10 8>,
 354
 355                                 /*PD_PERI*/
 356                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 357                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 358
 359                                 /*aclk_cpu_pre*/
 360                                 <&clk_gates4 12>,/*aclk_intmem*/
 361                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 362
 363                                 /*hclk_cpu_pre*/
 364                                 //<&clk_gates5 6>,/*hclk_rom*/
 365                                 <&clk_gates3 5>,/*hclk_crypto*/
 366
 367                                 /*pclk_cpu_pre*/
 368                                 <&clk_gates5 4>,/*pclk_grf*/
 369                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 370                                 //<&clk_gates5 14>,/*pclk_acodec*/
 371                                 //<&clk_gates3 8>,/*pclk_hdmi*/
 372
 373                                 /*aclk_peri_pre*/
 374                                 //<&clk_gates10 10>,/*aclk_gmac*/
 375                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 376                                 //<&clk_gates5 1>,/*aclk_dmac2*/
 377                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 378                                 <&clk_gates9 2>,/*g_pclk_pmu*/
 379                                 <&clk_gates9 3>,/*g_pclk_pmu_noc*/
 380                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 381
 382                                 /*hclk_peri_pre*/
 383                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 384                                 //<&clk_gates9 13>,/*hclk_usb_peri*/
 385                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 386
 387                                 /*pclk_peri_pre*/
 388                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 389
 390                                 /*hclk_vio_pre*/
 391                                 //<&clk_gates6 12>,/*hclk_vio_niu*/
 392                                 //<&clk_gates6 1>,/*hclk_lcdc*/
 393
 394                                 /*aclk_vio0_pre*/
 395                                 //<&clk_gates6 13>,/*aclk_vio*/
 396                                 //<&clk_gates6 0>,/*aclk_lcdc*/
 397
 398                                 /*aclk_vio1_pre*/
 399                                 //<&clk_gates9 10>,/*aclk_vio1_niu*/
 400
 401                                 /*UART*/
 402                                 <&clk_gates1 12>,
 403                                 <&clk_gates1 13>,
 404                                 <&clk_gates8 2>,/*pclk_uart2*/
 405
 406                                 //<&clk_gpu>,
 407
 408                                 /*jtag*/
 409                                 //<&clk_gates1 3>,/*clk_jtag*/
 410
 411                                 /*pmu*/
 412                                 <&clk_gates1 0>;/*pclk_pmu_pre*/
 413         };
 414
 415         i2c0: i2c@20072000 {
 416                 compatible = "rockchip,rk30-i2c";
 417                 reg = <0x20072000 0x1000>;
 418                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 pinctrl-names = "default", "gpio";
 422                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 423                 pinctrl-1 = <&i2c0_gpio>;
 424                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 425                 clocks = <&clk_gates8 4>;
 426                 rockchip,check-idle = <1>;
 427                 status = "disabled";
 428         };
 429
 430         i2c1: i2c@20056000 {
 431                 compatible = "rockchip,rk30-i2c";
 432                 reg = <0x20056000 0x1000>;
 433                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 pinctrl-names = "default", "gpio";
 437                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 438                 pinctrl-1 = <&i2c1_gpio>;
 439                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 440                 clocks = <&clk_gates8 5>;
 441                 rockchip,check-idle = <1>;
 442                 status = "disabled";
 443         };
 444
 445         i2c2: i2c@2005a000 {
 446                 compatible = "rockchip,rk30-i2c";
 447                 reg = <0x2005a000 0x1000>;
 448                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 pinctrl-names = "default", "gpio";
 452                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 453                 pinctrl-1 = <&i2c2_gpio>;
 454                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 455                 clocks = <&clk_gates8 6>;
 456                 rockchip,check-idle = <1>;
 457                 status = "disabled";
 458         };
 459
 460         i2c3: i2c@2005e000 {
 461                 compatible = "rockchip,rk30-i2c";
 462                 reg = <0x2005e000 0x1000>;
 463                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 pinctrl-names = "default", "gpio";
 467                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 468                 pinctrl-1 = <&i2c3_gpio>;
 469                 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
 470                 clocks = <&clk_gates8 7>;
 471                 rockchip,check-idle = <1>;
 472                 status = "disabled";
 473         };
 474
 475         i2s0: i2s0@10220000 {
 476                 compatible = "rockchip-i2s";
 477                 reg = <0x10220000 0x1000>;
 478                 i2s-id = <0>;
 479                 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
 480                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 481                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 482                 dmas = <&pdma 0>, <&pdma 1>;
 483                 //#dma-cells = <2>;
 484                 dma-names = "tx", "rx";
 485                 //pinctrl-names = "default", "sleep";
 486                 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 487                 //pinctrl-1 = <&i2s0_gpio>;
 488                 status = "disabled";
 489         };
 490
 491         i2s1: i2s1@10200000 {
 492                 compatible = "rockchip-i2s";
 493                 reg = <0x10200000 0x1000>;
 494                 i2s-id = <1>;
 495                 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
 496                 clock-names = "i2s_clk", "i2s_hclk";
 497                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 498                 dmas = <&pdma 14>, <&pdma 15>;
 499                 //#dma-cells = <2>;
 500                 dma-names = "tx", "rx";
 501         };
 502
 503         spdif: spdif@10204000 {
 504                 compatible = "rockchip-spdif";
 505                 reg = <0x10204000 0x1000>;
 506                 clocks = <&clk_spdif>, <&clk_gates10 9>;
 507                 clock-names = "spdif_mclk", "spdif_hclk";
 508                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 509                 dmas = <&pdma 13>;
 510                 //#dma-cells = <1>;
 511                 dma-names = "tx";
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&spdif_tx>;
 514         };
 515
 516         dsihost0: mipi@10110000{
 517                 compatible = "rockchip,rk312x-dsi";
 518                 rockchip,prop = <0>;
 519                 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
 520                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 521                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 522                 clocks = <&clk_gates2 15>, <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>, <&pd_mipidsi>;
 523                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "hclk_vio_h2p", "pd_mipi_dsi";
 524                 status = "okay";
 525         };
 526
 527         emmc: rksdmmc@1021c000 {
 528                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 529                 reg = <0x1021c000 0x4000>;
 530                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 //pinctrl-names = "default",,"suspend";
 534                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 535                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 536                 clock-names = "clk_mmc", "hclk_mmc";
 537                 dmas = <&pdma 12>;
 538                 dma-names = "dw_mci";
 539                 num-slots = <1>;
 540                 fifo-depth = <0x100>;
 541                 bus-width = <8>;
 542                 cru_regsbase = <0x124>;
 543                 cru_reset_offset = <3>;
 544         };
 545
 546
 547         sdmmc: rksdmmc@10214000 {
 548                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 549                 reg = <0x10214000 0x4000>;
 550                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 pinctrl-names = "default", "idle", "udbg";
 554                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd  &sdmmc0_dectn &sdmmc0_bus4>;
 555                 pinctrl-1 = <&sdmmc0_gpio>;
 556                 pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
 557                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 558                 clock-names = "clk_mmc", "hclk_mmc";
 559                 dmas = <&pdma 10>;
 560                 dma-names = "dw_mci";
 561                 num-slots = <1>;
 562                 fifo-depth = <0x100>;
 563                 bus-width = <4>;
 564                 cru_regsbase = <0x124>;
 565                 cru_reset_offset = <1>;
 566         };
 567
 568         sdio: rksdmmc@10218000 {
 569                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 570                 reg = <0x10218000 0x4000>;
 571                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 pinctrl-names = "default","idle";
 575                 pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>;
 576                 pinctrl-1 = <&sdio0_gpio>;
 577                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 578                 clock-names = "clk_mmc", "hclk_mmc";
 579                 dmas = <&pdma 11>;
 580                 dma-names = "dw_mci";
 581                 num-slots = <1>;
 582                 fifo-depth = <0x100>;
 583                 bus-width = <4>;
 584                 cru_regsbase = <0x124>;
 585                 cru_reset_offset = <2>;
 586         };
 587
 588         spi0: spi@20074000 {
 589                 compatible = "rockchip,rockchip-spi";
 590                 reg = <0x20074000 0x1000>;
 591                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
 596                 //pinctrl-0 = <&spi0_txd_mux1 &spi0_rxd_mux1 &spi0_clk_mux1 &spi0_cs0_mux1 &spi0_cs1_mux1>;
 597                 //pinctrl-0 = <&spi0_txd_mux2 &spi0_rxd_mux2 &spi0_clk_mux2 &spi0_cs0_mux2>;
 598                 rockchip,spi-src-clk = <0>;
 599                 num-cs = <2>;
 600                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 601                 clock-names = "spi","pclk_spi0";
 602                 dmas = <&pdma 8>, <&pdma 9>;
 603                 #dma-cells = <2>;
 604                 dma-names = "tx", "rx";
 605                 status = "disabled";
 606         };
 607
 608         adc: adc@2006c000 {
 609                 compatible = "rockchip,saradc";
 610                 reg = <0x2006c000 0x100>;
 611                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 612                 #io-channel-cells = <1>;
 613                 io-channel-ranges;
 614                 rockchip,adc-vref = <1800>;
 615                 clock-frequency = <1000000>;
 616                 clocks = <&clk_saradc>, <&clk_gates7 14>;
 617                 clock-names = "saradc", "pclk_saradc";
 618                 status = "disabled";
 619         };
 620
 621         pwm0: pwm@20050000 {
 622                 compatible = "rockchip,rk-pwm";
 623                 reg = <0x20050000 0x10>;
 624                 #pwm-cells = <2>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&pwm0_pin>;
 627                 clocks = <&clk_gates7 10>;
 628                 clock-names = "pclk_pwm";
 629                 status = "disabled";
 630         };
 631
 632         pwm1: pwm@20050010 {
 633                 compatible = "rockchip,rk-pwm";
 634                 reg = <0x20050010 0x10>;
 635                 #pwm-cells = <2>;
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&pwm1_pin>;
 638                 clocks = <&clk_gates7 10>;
 639                 clock-names = "pclk_pwm";
 640                 status = "disabled";
 641         };
 642
 643         pwm2: pwm@20050020 {
 644                 compatible = "rockchip,rk-pwm";
 645                 reg = <0x20050020 0x10>;
 646                 #pwm-cells = <2>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&pwm2_pin>;
 649                 clocks = <&clk_gates7 10>;
 650                 clock-names = "pclk_pwm";
 651                 status = "disabled";
 652         };
 653
 654         pwm3: pwm@20050030 {
 655                 compatible = "rockchip,rk-pwm";
 656                 reg = <0x20050030 0x10>;
 657                 #pwm-cells = <2>;
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&pwm3_pin>;
 660                 clocks = <&clk_gates7 10>;
 661                 clock-names = "pclk_pwm";
 662                 status = "disabled";
 663         };
 664
 665         remotectl: pwm@20050030 {
 666                 compatible = "rockchip,remotectl-pwm";
 667                 reg = <0x20050030 0x10>;
 668                 #pwm-cells = <2>;
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&pwm3_pin>;
 671                 clocks = <&clk_gates7 10>;
 672                 clock-names = "pclk_pwm";
 673                 remote_pwm_id = <3>;
 674                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 675                 status = "okay";
 676         };
 677         dwc_control_usb: dwc-control-usb@20008000 {
 678                 compatible = "rockchip,rk3126-dwc-control-usb";
 679                 reg = <0x20008000 0x4>;
 680                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 681                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 682                              <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 683                 interrupt-names = "otg_bvalid",
 684                                   "otg0_linestate",
 685                                   "otg1_linestate";
 686                 clocks = <&clk_gates9 13>;
 687                 clock-names = "hclk_usb_peri";
 688                 rockchip,remote_wakeup;
 689                 rockchip,usb_irq_wakeup;
 690                 resets = <&reset RK3128_RST_USBPOR>;
 691                 reset-names = "usbphy_por";
 692                 usb_bc{
 693                         compatible = "inno,phy";
 694                         regbase = &dwc_control_usb;
 695                         rk_usb,bvalid     = <0x14c  5 1>;
 696                         rk_usb,iddig      = <0x14c  8 1>;
 697                         rk_usb,vdmsrcen   = <0x184 12 1>;
 698                         rk_usb,vdpsrcen   = <0x184 11 1>;
 699                         rk_usb,rdmpden    = <0x184 10 1>;
 700                         rk_usb,idpsrcen   = <0x184  9 1>;
 701                         rk_usb,idmsinken  = <0x184  8 1>;
 702                         rk_usb,idpsinken  = <0x184  7 1>;
 703                         rk_usb,dpattach   = <0x2c0  7 1>;
 704                         rk_usb,cpdet      = <0x2c0  6 1>;
 705                         rk_usb,dcpattach  = <0x2c0  5 1>;
 706                 };
 707         };
 708
 709         usb0: usb@10180000 {
 710                 compatible = "rockchip,rk3126_usb20_otg";
 711                 reg = <0x10180000 0x40000>;
 712                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 713                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 714                 clock-names = "clk_usbphy0", "hclk_usb0";
 715                 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_UTMI0>,
 716                                 <&reset RK3128_RST_OTGC0>;
 717                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 718                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 719                 rockchip,usb-mode = <0>;
 720         };
 721
 722         ehci: usb@101c0000 {
 723                 compatible = "rockchip,rk3126_ehci";
 724                 reg = <0x101c0000 0x20000>;
 725                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 726                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 727                 clock-names = "clk_usbphy1", "hclk_host0";
 728                 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
 729                                 <&reset RK3128_RST_OTGC1>;
 730                 reset-names = "host_ahb", "host_phy", "host_controller";
 731         };
 732
 733         ohci: usb@101e0000 {
 734                 compatible = "rockchip,rk3126_ohci";
 735                 reg = <0x101e0000 0x20000>;
 736                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 737         };
 738
 739         fb: fb{
 740                 compatible = "rockchip,rk-fb";
 741                 rockchip,disp-mode = <ONE_DUAL>;
 742         };
 743
 744         rk_screen: rk_screen{
 745                 compatible = "rockchip,screen";
 746         };
 747
 748         lvds: lvds@20038000 {
 749                 compatible = "rockchip,rk31xx-lvds";
 750                 reg = <0x20038000 0x4000>, <0x101100b0 0x01>;
 751                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 752                 clocks = <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>;
 753                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "hclk_vio_h2p";
 754                 status = "disabled";
 755         };
 756
 757         lcdc: lcdc@1010e000 {
 758                 compatible = "rockchip,rk312x-lcdc";
 759                 rockchip,prop = <PRMRY>;
 760                 reg = <0x1010e000 0x1000>;
 761                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 762                 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>, <&pd_vop>, <&clk_cpll>;
 763                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc", "pd_lcdc", "sclk_pll";
 764                 rockchip,iommu-enabled = <1>;
 765                 status = "disabled";
 766         };
 767
 768         hdmi: hdmi@20034000 {
 769                 compatible = "rockchip,rk312x-hdmi";
 770                 reg = <0x20034000 0x4000>;
 771                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 772                 rockchip,hdmi_lcdc_source = <0>;
 773                 pinctrl-names = "default", "gpio";
 774                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 775                 pinctrl-1 = <&hdmi_gpio>;
 776                 clocks = <&clk_gates3 8>, <&pd_hdmi>;
 777                 clock-names = "pclk_hdmi", "pd_hdmi";
 778                 rockchip,hdcp_enable = <0>;
 779                 rockchip,cec_enable = <0>;
 780                 status = "disabled";
 781         };
 782
 783         tve: tve{
 784                 compatible = "rockchip,rk312x-tve";
 785                 reg = <0x1010e200 0x100>;
 786                 status = "disabled";
 787         };
 788
 789         vpu: vpu_service {
 790                 compatible = "rockchip,vpu_sub";
 791                 iommu_enabled = <1>;
 792                 reg = <0x10106000 0x800>;
 793                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 794                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 795                 interrupt-names = "irq_enc", "irq_dec";
 796                 dev_mode = <0>;
 797                 name = "vpu_service";
 798         };
 799
 800         hevc: hevc_service {
 801                 compatible = "rockchip,hevc_sub";
 802                 iommu_enabled = <1>;
 803                 reg = <0x10104000 0x400>;
 804                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 805                 interrupt-names = "irq_dec";
 806                 dev_mode = <1>;
 807                 name = "hevc_service";
 808         };
 809
 810         vpu_combo: vpu_combo@ff9a0000 {
 811                 compatible = "rockchip,vpu_combo";
 812                 subcnt = <2>;
 813                 rockchip,sub = <&vpu>, <&hevc>;
 814                 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
 815                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 816                 resets = <&reset RK3128_RST_VCODEC_H>, <&reset RK3128_RST_VCODEC_A>,
 817                         <&reset RK3128_RST_HEVC>;
 818                 reset-names = "video_h", "video_a", "video";
 819                 mode_bit = <15>;
 820                 mode_ctrl = <0x144>;
 821                 name = "vpu_combo";
 822                 status = "okay";
 823         };
 824
 825         iep: iep@10108000 {
 826                 compatible = "rockchip,iep";
 827                 iommu_enabled = <1>;
 828                 reg = <0x10108000 0x800>;
 829                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 830                 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
 831                 clock-names = "aclk_iep", "hclk_iep";
 832                 version = <1>;
 833                 status = "okay";
 834         };
 835
 836         rga: rga@1010c000 {
 837                 compatible = "rockchip,rk312x-rga";
 838                 reg = <0x1010c000 0x1000>;
 839                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 840                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 841                 clock-names = "hclk_rga", "aclk_rga";
 842                 status = "okay";
 843         };
 844
 845   vop_mmu {
 846                 dbgname = "vop";
 847                 compatible = "rockchip,vop_mmu";
 848                 reg = <0x1010e300 0x100>;
 849                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 850                 interrupt-names = "vop_mmu";
 851           };
 852
 853           hevc_mmu {
 854                 dbgname = "hevc";
 855                 compatible = "rockchip,hevc_mmu";
 856                 reg = <0x10104440 0x40>,
 857                       <0x10104480 0x40>;
 858                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 859                 interrupt-names = "hevc_mmu";
 860           };
 861
 862           vpu_mmu {
 863                 dbgname = "vpu";
 864                 compatible = "rockchip,vpu_mmu";
 865                 reg = <0x10106800 0x100>;
 866                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 867                 interrupt-names = "vpu_mmu";
 868           };
 869
 870           iep_mmu {
 871                 dbgname = "iep";
 872                 compatible = "rockchip,iep_mmu";
 873                 reg = <0x10108800 0x100>;
 874                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 875                 interrupt-names = "iep_mmu";
 876           };
 877
 878           dvfs {
 879                 vd_arm: vd_arm {
 880                         regulator_name = "vdd_arm";
 881                         pd_core {
 882                                 clk_core_dvfs_table: clk_core {
 883                                         operating-points = <
 884                                                 /* KHz    uV */
 885                                                 312000 1100000
 886                                                 504000 1100000
 887                                                 816000 1100000
 888                                                 1008000 1100000
 889                                                 >;
 890                                         temp-limit-enable = <0>;
 891                                         target-temp = <80>;
 892                                         temp-channel = <1>;
 893                                         normal-temp-limit = <
 894                                         /*delta-temp    delta-freq*/
 895                                                 3       96000
 896                                                 6       144000
 897                                                 9       192000
 898                                                 15      384000
 899                                                 >;
 900                                         performance-temp-limit = <
 901                                                 /*temp    freq*/
 902                                                 110     816000
 903                                                 >;
 904                                         status = "okay";
 905                                         regu-mode-table = <
 906                                                 /*freq     mode*/
 907                                                 1008000    4
 908                                                 0          3
 909                                         >;
 910                                         regu-mode-en = <0>;
 911                                         lkg_adjust_volt_en = <1>;
 912                                         channel = <0>;
 913                                         def_table_lkg = <35>;
 914                                         min_adjust_freq = <1200000>;
 915                                         lkg_adjust_volt_table = <
 916                                                 /*lkg(mA)  volt(uV)*/
 917                                                 60         25000
 918                                                 >;
 919                                 };
 920                         };
 921                 };
 922
 923                 vd_logic: vd_logic {
 924                         regulator_name = "vdd_logic";
 925                         pd_ddr {
 926                                 clk_ddr_dvfs_table: clk_ddr {
 927                                         operating-points = <
 928                                                 /* KHz    uV */
 929                                                 200000 1200000
 930                                                 300000 1200000
 931                                                 400000 1200000
 932                                                 >;
 933                                         status = "disabled";
 934                                 };
 935                         };
 936
 937                         pd_gpu {
 938                                 clk_gpu_dvfs_table: clk_gpu {
 939                                         operating-points = <
 940                                                 /* KHz    uV */
 941                                                 200000 1200000
 942                                                 300000 1200000
 943                                                 400000 1200000
 944                                                 >;
 945                                         status = "okay";
 946                                         regu-mode-table = <
 947                                                 /*freq     mode*/
 948                                                 200000     4
 949                                                 0          3
 950                                         >;
 951                                         regu-mode-en = <0>;
 952                                 };
 953                         };
 954                 };
 955         };
 956         ion {
 957                 compatible = "rockchip,ion";
 958                 #address-cells = <1>;
 959                 #size-cells = <0>;
 960
 961                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 962                         compatible = "rockchip,ion-heap";
 963                         rockchip,ion_heap = <4>;
 964                         reg = <0x00000000 0x800000>; /* 8MB */
 965                 };
 966                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
 967                         compatible = "rockchip,ion-heap";
 968                         rockchip,ion_heap = <0>;
 969                 };
 970         };
 971         cif: cif@1010a000 {
 972              compatible = "rockchip,cif";
 973              reg = <0x1010a000 0x2000>;
 974              interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 975              clocks = <&pd_vip>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
 976              clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
 977              status = "okay";
 978              };
 979
 980         codec_hdmi_spdif: codec-hdmi-spdif {
 981                 compatible = "hdmi-spdif";
 982         };
 983
 984         rockchip-hdmi-spdif {
 985                 compatible = "rockchip-hdmi-spdif";
 986                 dais {
 987                         dai0 {
 988                                 audio-codec = <&codec_hdmi_spdif>;
 989                                 audio-controller = <&spdif>;
 990                         };
 991                 };
 992         };
 993         codec: codec@20030000 {
 994                 compatible = "rk312x-codec";
 995                 reg = <0x20030000 0x4000>;
 996                 //pinctrl-names = "default";
 997                 //pinctrl-0 = <&i2s_gpio>;
 998                 boot_depop = <1>;
 999                 pa_enable_time = <1000>;
1000                 clocks = <&clk_gates5 14>;
1001                 clock-names = "g_pclk_acodec";
1002         };
1003         rockchip_audio: audio-rk312x {
1004                 compatible = "audio-rk312x";
1005                 dais {
1006                         dai0 {
1007                                 audio-codec = <&codec>;
1008                                 audio-controller = <&i2s1>;
1009                                 format = "i2s";
1010                                 //continuous-clock;
1011                                 //bitclock-inversion;
1012                                 //frame-inversion;
1013                                 //bitclock-master;
1014                                 //frame-master;
1015                         };
1016                         dai1 {
1017                                 audio-codec = <&codec>;
1018                                 audio-controller = <&i2s1>;
1019                                 format = "i2s";
1020                                 //continuous-clock;
1021                                 //bitclock-inversion;
1022                                 //frame-inversion;
1023                                 //bitclock-master;
1024                                 //frame-master;
1025                         };
1026                 };
1027         };
1028 };