rk312x: add psci support
[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / rk312x.dtsi
1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/sensor-dev.h>
4 #include <dt-bindings/clock/rk_system_status.h>
5 #include <dt-bindings/rkfb/rk_fb.h>
6
7 #include "skeleton.dtsi"
8 #include "rk312x-clocks.dtsi"
9 #include "rk312x-pinctrl.dtsi"
10
11 / {
12         compatible = "rockchip,rk312x";
13         rockchip,sram = <&sram>;
14         interrupt-parent = <&gic>;
15
16         aliases {
17                 serial0 = &uart0;
18                 serial1 = &uart1;
19                 serial2 = &uart2;
20                 i2c0 = &i2c0;
21                 i2c1 = &i2c1;
22                 i2c2 = &i2c2;
23                 i2c3 = &i2c3;
24                 lcdc = &lcdc;
25                 spi0 = &spi0;
26         };
27
28         cpus {
29                 #address-cells = <1>;
30                 #size-cells = <0>;
31
32                 cpu@0 {
33                         device_type = "cpu";
34                         compatible = "arm,cortex-a7";
35                         reg = <0xf00>;
36                 };
37                 cpu@1 {
38                         device_type = "cpu";
39                         compatible = "arm,cortex-a7";
40                         reg = <0xf01>;
41                 };
42                 cpu@2 {
43                         device_type = "cpu";
44                         compatible = "arm,cortex-a7";
45                         reg = <0xf02>;
46                 };
47                 cpu@3 {
48                         device_type = "cpu";
49                         compatible = "arm,cortex-a7";
50                         reg = <0xf03>;
51                 };
52         };
53
54         psci {
55                 compatible      = "arm,psci";
56                 method          = "smc";
57                 cpu_suspend     = <0x84000001>;
58                 cpu_off         = <0x84000002>;
59                 cpu_on          = <0x84000003>;
60                 migrate         = <0x84000005>;
61         };
62
63         gic: interrupt-controller@10139000 {
64                 compatible = "arm,cortex-a15-gic";
65                 interrupt-controller;
66                 #interrupt-cells = <3>;
67                 #address-cells = <0>;
68                 reg = <0x10139000 0x1000>,
69                       <0x1013a000 0x1000>;
70         };
71
72         arm-pmu {
73                 compatible = "arm,cortex-a7-pmu";
74                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
75                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
76                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
77                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
78         };
79
80         cpu_axi_bus: cpu_axi_bus {
81                 compatible = "rockchip,cpu_axi_bus";
82                 #address-cells = <1>;
83                 #size-cells = <1>;
84                 ranges;
85
86                 qos {
87                         #address-cells = <1>;
88                         #size-cells = <1>;
89                         ranges;
90
91                         crypto {
92                                 reg = <0x10128080 0x20>;
93                         };
94                         core {
95                                 reg = <0x1012a000 0x20>;
96                         };
97                         peri {
98                                 reg = <0x1012c000 0x20>;
99                         };
100                         gpu {
101                                 reg = <0x1012d000 0x20>;
102                         };
103                         vpu {
104                                 reg = <0x1012e000 0x20>;
105                         };
106                         rga {
107                                 reg = <0x1012f000 0x20>;
108                         };
109                         ebc {
110                                 reg = <0x1012f080 0x20>;
111                         };
112                         iep {
113                                 reg = <0x1012f100 0x20>;
114                         };
115                         lcdc {
116                                 reg = <0x1012f180 0x20>;
117                                 rockchip,priority = <3 3>;
118                         };
119                         vip {
120                                 reg = <0x1012f200 0x20>;
121                                 rockchip,priority = <3 3>;
122                         };
123                 };
124
125                 msch {
126                         #address-cells = <1>;
127                         #size-cells = <1>;
128                         ranges;
129
130                         msch@10128000 {
131                                 reg = <0x10128000 0x20>;
132                                 rockchip,read-latency = <0x3f>;
133                         };
134                 };
135         };
136
137         sram: sram@10080400 {
138                 compatible = "mmio-sram";
139                 reg = <0x10080400 0x1C00>;
140                 map-exec;
141                 map-cacheable;
142         };
143
144         timer {
145                 compatible = "arm,armv7-timer";
146                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
148                 clock-frequency = <24000000>;
149         };
150
151         timer@20044000 {
152                 compatible = "rockchip,timer";
153                 reg = <0x20044000 0x20>;
154                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
155                 rockchip,broadcast = <1>;
156         };
157
158         watchdog: wdt@2004c000 {
159                 compatible = "rockchip,watch dog";
160                 reg = <0x2004c000 0x100>;
161         //      clocks = <&clk_gates7 15>;
162                 clock-names = "pclk_wdt";
163                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
164                 rockchip,irq = <1>;
165                 rockchip,timeout = <60>;
166                 rockchip,atboot = <1>;
167                 rockchip,debug = <0>;
168                 status = "disabled";
169         };
170
171         amba {
172                 #address-cells = <1>;
173                 #size-cells = <1>;
174                 compatible = "arm,amba-bus";
175                 interrupt-parent = <&gic>;
176                 ranges;
177
178                 pdma: pdma@20078000 {
179                         compatible = "arm,pl330", "arm,primecell";
180                         reg = <0x20078000 0x4000>;
181                         clocks = <&clk_gates5 1>;
182                         clock-names = "apb_pclk";
183                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
184                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
185                         #dma-cells = <1>;
186                 };
187         };
188
189         reset: reset@20000110 {
190                 compatible = "rockchip,reset";
191                 reg = <0x20000110 0x24>;
192                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
193                 #reset-cells = <1>;
194         };
195
196         nandc: nandc@10500000 {
197                 compatible = "rockchip,rk-nandc";
198                 reg = <0x10500000 0x4000>;
199                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
200                 //pinctrl-names = "default";
201                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
202                 nandc_id = <0>;
203                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
204                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
205         };
206         
207         nandc0reg: nandc0@10500000 {
208                 compatible = "rockchip,rk-nandc";
209                 reg = <0x10500000 0x4000>;
210         };
211         uart0: serial@20060000 {
212                 compatible = "rockchip,serial";
213                 reg = <0x20060000 0x100>;
214                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
215                 clock-frequency = <24000000>;
216                 clocks = <&clk_uart0>, <&clk_gates8 0>;
217                 clock-names = "sclk_uart", "pclk_uart";
218                 reg-shift = <2>;
219                 reg-io-width = <4>;
220                 dmas = <&pdma 2>, <&pdma 3>;
221                 #dma-cells = <2>;
222                 pinctrl-names = "default";
223                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
224                 status = "disabled";
225         };
226
227         uart1: serial@20064000 {
228                 compatible = "rockchip,serial";
229                 reg = <0x20064000 0x100>;
230                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
231                 clock-frequency = <24000000>;
232                 clocks = <&clk_uart1>, <&clk_gates8 1>;
233                 clock-names = "sclk_uart", "pclk_uart";
234                 reg-shift = <2>;
235                 reg-io-width = <4>;
236                 dmas = <&pdma 4>, <&pdma 5>;
237                 #dma-cells = <2>;
238                 pinctrl-names = "default";
239                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
240                 status = "disabled";
241         };
242
243         uart2: serial@20068000 {
244                 compatible = "rockchip,serial";
245                 reg = <0x20068000 0x100>;
246                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
247                 clock-frequency = <24000000>;
248                 clocks = <&clk_uart2>, <&clk_gates8 2>;
249                 clock-names = "sclk_uart", "pclk_uart";
250                 reg-shift = <2>;
251                 reg-io-width = <4>;
252                 dmas = <&pdma 6>, <&pdma 7>;
253                 #dma-cells = <2>;
254                 pinctrl-names = "default";
255                 pinctrl-0 = <&uart2_xfer>;
256                 status = "disabled";
257         };
258
259         gmac: eth@2008c000 {
260                 compatible = "rockchip,rk312x-gmac";
261                 reg = <0x2008c000 0x4000>;
262                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;  /*irq=88*/
263                 interrupt-names = "macirq";
264                 clocks = <&clk_mac_ref>, <&clk_gates2 6>,
265                         <&clk_gates2 7>, <&clk_gates2 4>,
266                         <&clk_gates2 5>, <&clk_gates10 10>,
267                         <&clk_gates10 11>;
268                 clock-names = "clk_mac", "mac_clk_rx",
269                         "mac_clk_tx", "clk_mac_ref",
270                         "clk_mac_refout", "aclk_mac",
271                         "pclk_mac";
272                 phy-mode = "rgmii";
273                 pinctrl-names = "default";
274                 pinctrl-0 = <&gmac_rxdv &gmac_txclk &gmac_crs &gmac_rxclk &gmac_mdio &gmac_txen &gmac_clk &gmac_rxer &gmac_rxd1 &gmac_rxd0 &gmac_txd1 &gmac_txd0 &gmac_rxd3 &gmac_rxd2 &gmac_txd2 &gmac_txd3 &gmac_col_gpio &gmac_mdc>;
275         };
276
277         fiq-debugger {
278                 compatible = "rockchip,fiq-debugger";
279                 rockchip,serial-id = <2>;
280                 rockchip,signal-irq = <106>;
281                 rockchip,wake-irq = <0>;
282                 status = "disabled";
283         };
284
285         rockchip_clocks_init: clocks-init{
286                 compatible = "rockchip,clocks-init";
287                 rockchip,clocks-init-parent =
288                         <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
289                         <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
290                         <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
291                         <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
292                         <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
293                         <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
294                         <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
295                         <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll_div2>,
296                         <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
297                         <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
298                         <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
299                         <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
300                         <&clk_mac_pll &clk_cpll>;
301                 rockchip,clocks-init-rate =
302                         <&clk_core 600000000>, <&clk_gpll 594000000>,
303                         <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
304                         <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
305                         <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
306                         <&pclk_peri_pre 75000000>, <&clk_gpu 300000000>,
307                         <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
308                         <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
309                         <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
310                         <&clk_mac_ref 125000000>;
311         /*      rockchip,clocks-uboot-has-init =
312                         <&aclk_vio1>;*/
313         };
314         gpu {
315                 compatible = "arm,mali400";
316                 reg = <0x10091000 0x200>,
317                       <0x10090000 0x100>,
318                       <0x10093000 0x100>,
319                       <0x10098000 0x1100>,
320                       <0x10094000 0x100>,
321                       <0x1009A000 0x1100>,
322                       <0x10095000 0x100>;
323                 
324                 reg-names = "Mali_L2",
325                             "Mali_GP",
326                             "Mali_GP_MMU",
327                             "Mali_PP0",
328                             "Mali_PP0_MMU",
329                             "Mali_PP1",
330                             "Mali_PP1_MMU";
331
332                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
333                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
334                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
335                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
336                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
337                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
338                 
339                 interrupt-names = "Mali_GP_IRQ",
340                                   "Mali_GP_MMU_IRQ",
341                                   "Mali_PP0_IRQ",
342                                   "Mali_PP0_MMU_IRQ",
343                                   "Mali_PP1_IRQ",
344                                   "Mali_PP1_MMU_IRQ";
345           };
346
347         clocks-enable {
348                 compatible = "rockchip,clocks-enable";
349                 clocks =
350                                 /*PD_CORE*/
351                                 <&clk_gates0 6>,<&clk_gates0 0>,
352                                 <&clk_gates0 7>,
353
354                                 /*PD_CPU*/
355                                 <&clk_gates0 1>, <&clk_gates0 3>,
356                                 <&clk_gates0 4>, <&clk_gates0 5>,
357                                 <&clk_gates0 12>,
358
359                                 /*TIMER*/
360                                 <&clk_gates10 3>, <&clk_gates10 4>,
361                                 <&clk_gates10 5>, <&clk_gates10 6>,
362                                 <&clk_gates10 7>, <&clk_gates10 8>,
363
364                                 /*PD_PERI*/
365                                 <&clk_gates2 0>, <&hclk_peri_pre>,
366                                 <&pclk_peri_pre>, <&clk_gates2 1>,
367
368                                 /*aclk_cpu_pre*/
369                                 <&clk_gates4 12>,/*aclk_intmem*/
370                                 <&clk_gates4 10>,/*aclk_strc_sys*/
371
372                                 /*hclk_cpu_pre*/
373                                 //<&clk_gates5 6>,/*hclk_rom*/
374                                 <&clk_gates3 5>,/*hclk_crypto*/
375
376                                 /*pclk_cpu_pre*/
377                                 <&clk_gates5 4>,/*pclk_grf*/
378                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
379                                 //<&clk_gates5 14>,/*pclk_acodec*/
380                                 //<&clk_gates3 8>,/*pclk_hdmi*/
381
382                                 /*aclk_peri_pre*/
383                                 //<&clk_gates10 10>,/*aclk_gmac*/
384                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
385                                 //<&clk_gates5 1>,/*aclk_dmac2*/
386                                 <&clk_gates9 15>,/*aclk_peri_niu*/
387                                 <&clk_gates9 2>,/*g_pclk_pmu*/
388                                 <&clk_gates9 3>,/*g_pclk_pmu_noc*/
389                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
390
391                                 /*hclk_peri_pre*/
392                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
393                                 //<&clk_gates9 13>,/*hclk_usb_peri*/
394                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
395
396                                 /*pclk_peri_pre*/
397                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
398
399                                 /*hclk_vio_pre*/
400                                 //<&clk_gates6 12>,/*hclk_vio_niu*/
401                                 //<&clk_gates6 1>,/*hclk_lcdc*/
402
403                                 /*aclk_vio0_pre*/
404                                 //<&clk_gates6 13>,/*aclk_vio*/
405                                 //<&clk_gates6 0>,/*aclk_lcdc*/
406
407                                 /*aclk_vio1_pre*/
408                                 //<&clk_gates9 10>,/*aclk_vio1_niu*/
409
410                                 /*UART*/
411                                 <&clk_gates1 12>,
412                                 <&clk_gates1 13>,
413                                 <&clk_gates8 2>,/*pclk_uart2*/
414
415                                 //<&clk_gpu>,
416
417                                 /*jtag*/
418                                 //<&clk_gates1 3>,/*clk_jtag*/
419
420                                 /*pmu*/
421                                 <&clk_gates1 0>;/*pclk_pmu_pre*/
422         };
423
424         i2c0: i2c@20072000 {
425                 compatible = "rockchip,rk30-i2c";
426                 reg = <0x20072000 0x1000>;
427                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
428                 #address-cells = <1>;
429                 #size-cells = <0>;
430                 pinctrl-names = "default", "gpio";
431                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
432                 pinctrl-1 = <&i2c0_gpio>;
433                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
434                 clocks = <&clk_gates8 4>;
435                 rockchip,check-idle = <1>;
436                 status = "disabled";
437         };
438
439         i2c1: i2c@20056000 {
440                 compatible = "rockchip,rk30-i2c";
441                 reg = <0x20056000 0x1000>;
442                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
443                 #address-cells = <1>;
444                 #size-cells = <0>;
445                 pinctrl-names = "default", "gpio";
446                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
447                 pinctrl-1 = <&i2c1_gpio>;
448                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
449                 clocks = <&clk_gates8 5>;
450                 rockchip,check-idle = <1>;
451                 status = "disabled";
452         };
453
454         i2c2: i2c@2005a000 {
455                 compatible = "rockchip,rk30-i2c";
456                 reg = <0x2005a000 0x1000>;
457                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
458                 #address-cells = <1>;
459                 #size-cells = <0>;
460                 pinctrl-names = "default", "gpio";
461                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
462                 pinctrl-1 = <&i2c2_gpio>;
463                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
464                 clocks = <&clk_gates8 6>;
465                 rockchip,check-idle = <1>;
466                 status = "disabled";
467         };
468
469         i2c3: i2c@2005e000 {
470                 compatible = "rockchip,rk30-i2c";
471                 reg = <0x2005e000 0x1000>;
472                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
473                 #address-cells = <1>;
474                 #size-cells = <0>;
475                 pinctrl-names = "default", "gpio";
476                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
477                 pinctrl-1 = <&i2c3_gpio>;
478                 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
479                 clocks = <&clk_gates8 7>;
480                 rockchip,check-idle = <1>;
481                 status = "disabled";
482         };
483
484         i2s0: i2s0@10220000 {
485                 compatible = "rockchip-i2s";
486                 reg = <0x10220000 0x1000>;
487                 i2s-id = <0>;
488                 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
489                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
490                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
491                 dmas = <&pdma 0>, <&pdma 1>;
492                 //#dma-cells = <2>;
493                 dma-names = "tx", "rx";
494                 //pinctrl-names = "default", "sleep";
495                 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
496                 //pinctrl-1 = <&i2s0_gpio>;
497                 status = "disabled";
498         };
499
500         i2s1: i2s1@10200000 {
501                 compatible = "rockchip-i2s";
502                 reg = <0x10200000 0x1000>;
503                 i2s-id = <1>;
504                 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
505                 clock-names = "i2s_clk", "i2s_hclk";
506                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
507                 dmas = <&pdma 14>, <&pdma 15>;
508                 //#dma-cells = <2>;
509                 dma-names = "tx", "rx";
510         };
511
512         spdif: spdif@10204000 {
513                 compatible = "rockchip-spdif";
514                 reg = <0x10204000 0x1000>;
515                 clocks = <&clk_spdif>, <&clk_gates10 9>;
516                 clock-names = "spdif_mclk", "spdif_hclk";
517                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
518                 dmas = <&pdma 13>;
519                 //#dma-cells = <1>;
520                 dma-names = "tx";
521                 pinctrl-names = "default";
522                 pinctrl-0 = <&spdif_tx>;
523         };      
524
525         dsihost0: mipi@10110000{
526                 compatible = "rockchip,rk312x-dsi";
527                 rockchip,prop = <0>;
528                 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
529                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
530                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
531                 clocks = <&clk_gates2 15>, <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>, <&pd_mipidsi>;
532                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "hclk_vio_h2p", "pd_mipi_dsi";
533                 status = "okay";
534         };
535
536         emmc: rksdmmc@1021c000 {
537                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
538                 reg = <0x1021c000 0x4000>;
539                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
540                 #address-cells = <1>;
541                 #size-cells = <0>;
542                 //pinctrl-names = "default",,"suspend";
543                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
544                 clocks = <&clk_emmc>, <&clk_gates7 0>;
545                 clock-names = "clk_mmc", "hclk_mmc";
546                 dmas = <&pdma 12>;
547                 dma-names = "dw_mci";
548                 num-slots = <1>;
549                 fifo-depth = <0x100>;
550                 bus-width = <8>;
551                 cru_regsbase = <0x124>;
552                 cru_reset_offset = <3>;
553         };
554
555
556         sdmmc: rksdmmc@10214000 {
557                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
558                 reg = <0x10214000 0x4000>;
559                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
560                 #address-cells = <1>;
561                 #size-cells = <0>;
562                 pinctrl-names = "default", "idle", "udbg";
563                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd  &sdmmc0_dectn &sdmmc0_bus4>;
564                 pinctrl-1 = <&sdmmc0_gpio>;
565                 pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
566                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
567                 clock-names = "clk_mmc", "hclk_mmc";
568                 dmas = <&pdma 10>;
569                 dma-names = "dw_mci";
570                 num-slots = <1>;
571                 fifo-depth = <0x100>;
572                 bus-width = <4>;
573                 cru_regsbase = <0x124>;
574                 cru_reset_offset = <1>;
575         };
576
577         sdio: rksdmmc@10218000 {
578                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
579                 reg = <0x10218000 0x4000>;
580                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
581                 #address-cells = <1>;
582                 #size-cells = <0>;
583                 pinctrl-names = "default","idle";
584                 pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>;
585                 pinctrl-1 = <&sdio0_gpio>;
586                 clocks = <&clk_sdio>, <&clk_gates5 11>;
587                 clock-names = "clk_mmc", "hclk_mmc";
588                 dmas = <&pdma 11>;
589                 dma-names = "dw_mci";
590                 num-slots = <1>;
591                 fifo-depth = <0x100>;
592                 bus-width = <4>;
593                 cru_regsbase = <0x124>;
594                 cru_reset_offset = <2>;
595         };
596         
597         spi0: spi@20074000 {
598                 compatible = "rockchip,rockchip-spi";
599                 reg = <0x20074000 0x1000>;
600                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
601                 #address-cells = <1>;
602                 #size-cells = <0>;
603                 pinctrl-names = "default";
604                 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
605                 //pinctrl-0 = <&spi0_txd_mux1 &spi0_rxd_mux1 &spi0_clk_mux1 &spi0_cs0_mux1 &spi0_cs1_mux1>;
606                 //pinctrl-0 = <&spi0_txd_mux2 &spi0_rxd_mux2 &spi0_clk_mux2 &spi0_cs0_mux2>;
607                 rockchip,spi-src-clk = <0>;
608                 num-cs = <2>;
609                 clocks =<&clk_spi0>, <&clk_gates7 12>;
610                 clock-names = "spi","pclk_spi0";
611                 dmas = <&pdma 8>, <&pdma 9>;
612                 #dma-cells = <2>;
613                 dma-names = "tx", "rx";
614                 status = "disabled";
615         };
616
617         adc: adc@2006c000 {
618                 compatible = "rockchip,saradc";
619                 reg = <0x2006c000 0x100>;
620                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
621                 #io-channel-cells = <1>;
622                 io-channel-ranges;
623                 rockchip,adc-vref = <1800>;
624                 clock-frequency = <1000000>;
625                 clocks = <&clk_saradc>, <&clk_gates7 14>;
626                 clock-names = "saradc", "pclk_saradc";
627                 status = "disabled";
628         };
629
630         pwm0: pwm@20050000 {
631                 compatible = "rockchip,rk-pwm";
632                 reg = <0x20050000 0x10>;
633                 #pwm-cells = <2>;
634                 pinctrl-names = "default";
635                 pinctrl-0 = <&pwm0_pin>;
636                 clocks = <&clk_gates7 10>;
637                 clock-names = "pclk_pwm";
638                 status = "disabled";
639         };
640
641         pwm1: pwm@20050010 {
642                 compatible = "rockchip,rk-pwm";
643                 reg = <0x20050010 0x10>;
644                 #pwm-cells = <2>;
645                 pinctrl-names = "default";
646                 pinctrl-0 = <&pwm1_pin>;
647                 clocks = <&clk_gates7 10>;
648                 clock-names = "pclk_pwm";
649                 status = "disabled";
650         };
651
652         pwm2: pwm@20050020 {
653                 compatible = "rockchip,rk-pwm";
654                 reg = <0x20050020 0x10>;
655                 #pwm-cells = <2>;
656                 pinctrl-names = "default";
657                 pinctrl-0 = <&pwm2_pin>;
658                 clocks = <&clk_gates7 10>;
659                 clock-names = "pclk_pwm";
660                 status = "disabled";
661         };
662
663         pwm3: pwm@20050030 {
664                 compatible = "rockchip,rk-pwm";
665                 reg = <0x20050030 0x10>;
666                 #pwm-cells = <2>;
667                 pinctrl-names = "default";
668                 pinctrl-0 = <&pwm3_pin>;
669                 clocks = <&clk_gates7 10>;
670                 clock-names = "pclk_pwm";
671                 status = "disabled";
672         };
673
674         remotectl: pwm@20050030 {
675                 compatible = "rockchip,remotectl-pwm";
676                 reg = <0x20050030 0x10>;
677                 #pwm-cells = <2>;
678                 pinctrl-names = "default";
679                 pinctrl-0 = <&pwm3_pin>;
680                 clocks = <&clk_gates7 10>;
681                 clock-names = "pclk_pwm";
682                 remote_pwm_id = <3>;
683                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
684                 status = "okay";
685         };
686         dwc_control_usb: dwc-control-usb@20008000 {
687                 compatible = "rockchip,rk3126-dwc-control-usb";
688                 reg = <0x20008000 0x4>;
689                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
690                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
691                              <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
692                 interrupt-names = "otg_bvalid",
693                                   "otg0_linestate",
694                                   "otg1_linestate";
695                 clocks = <&clk_gates9 13>;
696                 clock-names = "hclk_usb_peri";
697                 rockchip,remote_wakeup;
698                 rockchip,usb_irq_wakeup;
699                 resets = <&reset RK3128_RST_USBPOR>;
700                 reset-names = "usbphy_por";
701                 usb_bc{
702                         compatible = "inno,phy";
703                         regbase = &dwc_control_usb;
704                         rk_usb,bvalid     = <0x14c  5 1>;
705                         rk_usb,iddig      = <0x14c  8 1>;
706                         rk_usb,vdmsrcen   = <0x184 12 1>;
707                         rk_usb,vdpsrcen   = <0x184 11 1>;
708                         rk_usb,rdmpden    = <0x184 10 1>;
709                         rk_usb,idpsrcen   = <0x184  9 1>;
710                         rk_usb,idmsinken  = <0x184  8 1>;
711                         rk_usb,idpsinken  = <0x184  7 1>;
712                         rk_usb,dpattach   = <0x2c0  7 1>;
713                         rk_usb,cpdet      = <0x2c0  6 1>;
714                         rk_usb,dcpattach  = <0x2c0  5 1>;
715                 };
716         };
717
718         usb0: usb@10180000 {
719                 compatible = "rockchip,rk3126_usb20_otg";
720                 reg = <0x10180000 0x40000>;
721                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
722                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
723                 clock-names = "clk_usbphy0", "hclk_usb0";
724                 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_UTMI0>,
725                                 <&reset RK3128_RST_OTGC0>;
726                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
727                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
728                 rockchip,usb-mode = <0>;
729         };
730
731         ehci: usb@101c0000 {
732                 compatible = "rockchip,rk3126_ehci";
733                 reg = <0x101c0000 0x20000>;
734                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
735                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
736                 clock-names = "clk_usbphy1", "hclk_host0";
737                 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
738                                 <&reset RK3128_RST_OTGC1>;
739                 reset-names = "host_ahb", "host_phy", "host_controller";
740         };
741
742         ohci: usb@101e0000 {
743                 compatible = "rockchip,rk3126_ohci";
744                 reg = <0x101e0000 0x20000>;
745                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
746         };
747
748         fb: fb{
749                 compatible = "rockchip,rk-fb";
750                 rockchip,disp-mode = <ONE_DUAL>;
751         };
752
753         rk_screen: rk_screen{
754                 compatible = "rockchip,screen";
755         };
756
757         lvds: lvds@20038000 {
758                 compatible = "rockchip,rk31xx-lvds";
759                 reg = <0x20038000 0x4000>, <0x101100b0 0x01>;
760                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
761                 clocks = <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>;
762                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "hclk_vio_h2p";
763                 status = "disabled";
764         };
765
766         lcdc: lcdc@1010e000 {
767                 compatible = "rockchip,rk312x-lcdc";
768                 rockchip,prop = <PRMRY>;
769                 reg = <0x1010e000 0x1000>;
770                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
771                 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>, <&pd_vop>, <&clk_cpll>;
772                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc", "pd_lcdc", "sclk_pll";
773                 rockchip,iommu-enabled = <1>;
774                 status = "disabled";
775         };
776
777         hdmi: hdmi@20034000 {
778                 compatible = "rockchip,rk312x-hdmi";
779                 reg = <0x20034000 0x4000>;
780                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
781                 rockchip,hdmi_lcdc_source = <0>;
782                 pinctrl-names = "default", "gpio";
783                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
784                 pinctrl-1 = <&hdmi_gpio>;
785                 clocks = <&clk_gates3 8>, <&pd_hdmi>;
786                 clock-names = "pclk_hdmi", "pd_hdmi";
787                 rockchip,hdcp_enable = <0>;
788                 rockchip,cec_enable = <0>;
789                 status = "disabled";
790         };
791
792         tve: tve{
793                 compatible = "rockchip,rk312x-tve";
794                 reg = <0x1010e200 0x100>;
795                 status = "disabled";
796         };
797
798         vpu: vpu_service {
799                 compatible = "rockchip,vpu_sub";
800                 iommu_enabled = <1>;
801                 reg = <0x10106000 0x800>;
802                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
803                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
804                 interrupt-names = "irq_enc", "irq_dec";
805                 dev_mode = <0>;
806                 name = "vpu_service";
807         };
808
809         hevc: hevc_service {
810                 compatible = "rockchip,hevc_sub";
811                 iommu_enabled = <1>;
812                 reg = <0x10104000 0x400>;
813                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
814                 interrupt-names = "irq_dec";
815                 dev_mode = <1>;
816                 name = "hevc_service";
817         };
818
819         vpu_combo: vpu_combo@ff9a0000 {
820                 compatible = "rockchip,vpu_combo";
821                 subcnt = <2>;
822                 rockchip,sub = <&vpu>, <&hevc>;
823                 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
824                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
825                 resets = <&reset RK3128_RST_VCODEC_H>, <&reset RK3128_RST_VCODEC_A>,
826                         <&reset RK3128_RST_HEVC>;
827                 reset-names = "video_h", "video_a", "video";
828                 mode_bit = <15>;
829                 mode_ctrl = <0x144>;
830                 name = "vpu_combo";
831                 status = "okay";
832         };
833
834         iep: iep@10108000 {
835                 compatible = "rockchip,iep";
836                 iommu_enabled = <1>;
837                 reg = <0x10108000 0x800>;
838                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
839                 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
840                 clock-names = "aclk_iep", "hclk_iep";
841                 version = <1>;
842                 status = "okay";
843         };
844         
845         rga: rga@1010c000 {
846                 compatible = "rockchip,rk312x-rga";
847                 reg = <0x1010c000 0x1000>;
848                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
849                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
850                 clock-names = "hclk_rga", "aclk_rga";
851                 status = "okay";
852         };
853
854   vop_mmu {
855                 dbgname = "vop";
856                 compatible = "rockchip,vop_mmu";
857                 reg = <0x1010e300 0x100>;
858                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
859                 interrupt-names = "vop_mmu";
860           };
861
862           hevc_mmu {
863                 dbgname = "hevc";
864                 compatible = "rockchip,hevc_mmu";
865                 reg = <0x10104440 0x40>,
866                       <0x10104480 0x40>;
867                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
868                 interrupt-names = "hevc_mmu";
869           };
870
871           vpu_mmu {
872                 dbgname = "vpu";
873                 compatible = "rockchip,vpu_mmu";
874                 reg = <0x10106800 0x100>;
875                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
876                 interrupt-names = "vpu_mmu";
877           };
878
879           iep_mmu {
880                 dbgname = "iep";
881                 compatible = "rockchip,iep_mmu";
882                 reg = <0x10108800 0x100>;
883                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
884                 interrupt-names = "iep_mmu";
885           };
886
887           dvfs {
888                 vd_arm: vd_arm {
889                         regulator_name = "vdd_arm";
890                         pd_core {
891                                 clk_core_dvfs_table: clk_core {
892                                         operating-points = <
893                                                 /* KHz    uV */
894                                                 312000 1100000
895                                                 504000 1100000
896                                                 816000 1100000
897                                                 1008000 1100000
898                                                 >;
899                                         temp-limit-enable = <0>;
900                                         target-temp = <80>;
901                                         temp-channel = <1>;
902                                         normal-temp-limit = <
903                                         /*delta-temp    delta-freq*/
904                                                 3       96000
905                                                 6       144000
906                                                 9       192000
907                                                 15      384000
908                                                 >;
909                                         performance-temp-limit = <
910                                                 /*temp    freq*/
911                                                 110     816000
912                                                 >;
913                                         status = "okay";
914                                         regu-mode-table = <
915                                                 /*freq     mode*/
916                                                 1008000    4
917                                                 0          3
918                                         >;
919                                         regu-mode-en = <0>;
920                                         lkg_adjust_volt_en = <1>;
921                                         channel = <0>;
922                                         def_table_lkg = <35>;
923                                         min_adjust_freq = <1200000>;
924                                         lkg_adjust_volt_table = <
925                                                 /*lkg(mA)  volt(uV)*/
926                                                 60         25000
927                                                 >;
928                                 };
929                         };
930                 };
931
932                 vd_logic: vd_logic {
933                         regulator_name = "vdd_logic";
934                         pd_ddr {
935                                 clk_ddr_dvfs_table: clk_ddr {
936                                         operating-points = <
937                                                 /* KHz    uV */
938                                                 200000 1200000
939                                                 300000 1200000
940                                                 400000 1200000
941                                                 >;
942                                         status = "disabled";
943                                 };
944                         };
945
946                         pd_gpu {
947                                 clk_gpu_dvfs_table: clk_gpu {
948                                         operating-points = <
949                                                 /* KHz    uV */
950                                                 200000 1200000
951                                                 300000 1200000
952                                                 400000 1200000
953                                                 >;
954                                         status = "okay";
955                                         regu-mode-table = <
956                                                 /*freq     mode*/
957                                                 200000     4
958                                                 0          3
959                                         >;
960                                         regu-mode-en = <0>;
961                                 };
962                         };
963                 };
964         };
965         ion {
966                 compatible = "rockchip,ion";
967                 #address-cells = <1>;
968                 #size-cells = <0>;
969
970                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
971                         compatible = "rockchip,ion-heap";
972                         rockchip,ion_heap = <4>;
973                         reg = <0x00000000 0x800000>; /* 8MB */
974                 };
975                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
976                         compatible = "rockchip,ion-heap";
977                         rockchip,ion_heap = <0>;
978                 };
979         };
980         cif: cif@1010a000 {
981              compatible = "rockchip,cif";
982              reg = <0x1010a000 0x2000>;
983              interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
984              clocks = <&pd_vip>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
985              clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
986              status = "okay";
987              };
988
989         codec_hdmi_spdif: codec-hdmi-spdif {
990                 compatible = "hdmi-spdif";
991         };
992
993         rockchip-hdmi-spdif {
994                 compatible = "rockchip-hdmi-spdif";
995                 dais {
996                         dai0 {
997                                 audio-codec = <&codec_hdmi_spdif>;
998                                 audio-controller = <&spdif>;
999                         };
1000                 };
1001         };
1002         codec: codec@20030000 {
1003                 compatible = "rk312x-codec";
1004                 reg = <0x20030000 0x4000>;
1005                 //pinctrl-names = "default";
1006                 //pinctrl-0 = <&i2s_gpio>;
1007                 boot_depop = <1>;
1008                 pa_enable_time = <1000>;
1009                 clocks = <&clk_gates5 14>;
1010                 clock-names = "g_pclk_acodec";
1011         };
1012         rockchip_audio: audio-rk312x {
1013                 compatible = "audio-rk312x";
1014                 dais {
1015                         dai0 {
1016                                 audio-codec = <&codec>;
1017                                 audio-controller = <&i2s1>;
1018                                 format = "i2s";
1019                                 //continuous-clock;
1020                                 //bitclock-inversion;
1021                                 //frame-inversion;
1022                                 //bitclock-master;
1023                                 //frame-master;
1024                         };
1025                         dai1 {
1026                                 audio-codec = <&codec>;
1027                                 audio-controller = <&i2s1>;
1028                                 format = "i2s";
1029                                 //continuous-clock;
1030                                 //bitclock-inversion;
1031                                 //frame-inversion;
1032                                 //bitclock-master;
1033                                 //frame-master;
1034                         };
1035                 };
1036         };
1037 };