arch/arm/boot/dts/rk3036-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3036.h>
  15
  16 /{
  17
  18         clocks {
  19                 compatible = "rockchip,rk-clocks";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0  0x20000000  0x1f0>;
  23
  24                 fixed_rate_cons {
  25                         compatible = "rockchip,rk-fixed-rate-cons";
  26
  27                         xin24m: xin24m {
  28                                 compatible = "rockchip,rk-fixed-clock";
  29                                 clock-output-names = "xin24m";
  30                                 clock-frequency = <24000000>;
  31                                 #clock-cells = <0>;
  32                         };
  33
  34                         xin12m: xin12m {
  35                                 compatible = "rockchip,rk-fixed-clock";
  36                                 clocks = <&xin24m>;
  37                                 clock-output-names = "xin12m";
  38                                 clock-frequency = <12000000>;
  39                                 #clock-cells = <0>;
  40                         };
  41
  42                         rmii_clkin: rmii_clkin {
  43                                 compatible = "rockchip,rk-fixed-clock";
  44                                 clock-output-names = "rmii_clkin";
  45                                 clock-frequency = <50000000>;
  46                                 #clock-cells = <0>;
  47                         };
  48
  49                         usb_480m: usb_480m {
  50                                 compatible = "rockchip,rk-fixed-clock";
  51                                 clock-output-names = "usb_480m";
  52                                 clock-frequency = <480000000>;
  53                                 #clock-cells = <0>;
  54                         };
  55
  56                         i2s_clkin: i2s_clkin {
  57                                 compatible = "rockchip,rk-fixed-clock";
  58                                 clock-output-names = "i2s_clkin";
  59                                 clock-frequency = <0>;
  60                                 #clock-cells = <0>;
  61                         };
  62
  63                         jtag_tck: jtag_tck {
  64                                 compatible = "rockchip,rk-fixed-clock";
  65                                 clock-output-names = "jtag_tck";
  66                                 clock-frequency = <0>;
  67                                 #clock-cells = <0>;
  68                         };
  69
  70                         dummy: dummy {
  71                                 compatible = "rockchip,rk-fixed-clock";
  72                                 clock-output-names = "dummy";
  73                                 clock-frequency = <0>;
  74                                 #clock-cells = <0>;
  75                         };
  76
  77                         dummy_cpll: dummy_cpll {
  78                                 compatible = "rockchip,rk-fixed-clock";
  79                                 clock-output-names = "dummy_cpll";
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                         };
  83
  84                 };
  85
  86                 fixed_factor_cons {
  87                         compatible = "rockchip,rk-fixed-factor-cons";
  88 /*
  89                         otgphy0_12m: otgphy0_12m {
  90                                 compatible = "rockchip,rk-fixed-factor-clock";
  91                                 clocks = <&clk_gates1 5>;
  92                                 clock-output-names = "otgphy0_12m";
  93                                 clock-div = <1>;
  94                                 clock-mult = <20>;
  95                                 #clock-cells = <0>;
  96                         };
  97 */
  98                         hclk_vcodec: hclk_vcodec {
  99                                 compatible = "rockchip,rk-fixed-factor-clock";
 100                                 clocks = <&aclk_vcodec_pre>;
 101                                 clock-output-names = "hclk_vcodec";
 102                                 clock-div = <4>;
 103                                 clock-mult = <1>;
 104                                 #clock-cells = <0>;
 105                         };
 106
 107                         io_mac_mdclkout: io_mac_mdclkout {
 108                                 compatible = "rockchip,rk-fixed-factor-clock";
 109                                 clocks = <&aclk_peri_pre>;
 110                                 clock-output-names = "io_mac_mdclkout";
 111                                 clock-div = <2>;
 112                                 clock-mult = <1>;
 113                                 #clock-cells = <0>;
 114                         };
 115                 };
 116
 117                 clock_regs {
 118                         compatible = "rockchip,rk-clock-regs";
 119                         #address-cells = <1>;
 120                         #size-cells = <1>;
 121                         reg = <0x0000 0x01f0>;
 122                         ranges;
 123
 124                         /* PLL control regs */
 125                         pll_cons {
 126                                 compatible = "rockchip,rk-pll-cons";
 127                                 #address-cells = <1>;
 128                                 #size-cells = <1>;
 129                                 ranges ;
 130
 131                                 clk_apll: pll-clk@0000 {
 132                                         compatible = "rockchip,rk3188-pll-clk";
 133                                         reg = <0x0000 0x10>;
 134                                         mode-reg = <0x0040 0>;
 135                                         status-reg = <0x0004 10>;
 136                                         clocks = <&xin24m>;
 137                                         clock-output-names = "clk_apll";
 138                                         rockchip,pll-type = <CLK_PLL_3036_APLL>;
 139                                         #clock-cells = <0>;
 140                                 };
 141
 142                                 clk_dpll: pll-clk@0010 {
 143                                         compatible = "rockchip,rk3188-pll-clk";
 144                                         reg = <0x0010 0x10>;
 145                                         mode-reg = <0x0040 4>;
 146                                         status-reg = <0x0014 10>;
 147                                         clocks = <&xin24m>;
 148                                         clock-output-names = "clk_dpll";
 149                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 150                                         #clock-cells = <0>;
 151                                 };
 152
 153                                 clk_gpll: pll-clk@0030 {
 154                                         compatible = "rockchip,rk3188-pll-clk";
 155                                         reg = <0x0030 0x10>;
 156                                         mode-reg = <0x0040 12>;
 157                                         status-reg = <0x0034 10>;
 158                                         clocks = <&xin24m>;
 159                                         clock-output-names = "clk_gpll";
 160                                         rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
 161                                         #clock-cells = <0>;
 162                                         #clock-init-cells = <1>;
 163                                 };
 164
 165                         };
 166
 167                         /* Select control regs */
 168                         clk_sel_cons {
 169                                 compatible = "rockchip,rk-sel-cons";
 170                                 #address-cells = <1>;
 171                                 #size-cells = <1>;
 172                                 ranges;
 173
 174                                 clk_sel_con0: sel-con@0044 {
 175                                         compatible = "rockchip,rk3188-selcon";
 176                                         reg = <0x0044 0x4>;
 177                                         #address-cells = <1>;
 178                                         #size-cells = <1>;
 179
 180                                         clk_core_div: clk_core_div {
 181                                                 compatible = "rockchip,rk3188-div-con";
 182                                                 rockchip,bits = <0 5>;
 183                                                 clocks = <&clk_core>;
 184                                                 clock-output-names = "clk_core";
 185                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 186                                                 #clock-cells = <0>;
 187                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 188                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 189                                                                         CLK_SET_RATE_NO_REPARENT)>;
 190                                         };
 191
 192                                         /* reg[6:5]: reserved */
 193
 194                                         clk_core: clk_core_mux {
 195                                                 compatible = "rockchip,rk3188-mux-con";
 196                                                 rockchip,bits = <7 1>;
 197                                                 clocks = <&clk_apll>, <&clk_gates0 6>;
 198                                                 clock-output-names = "clk_core";
 199                                                 #clock-cells = <0>;
 200                                                 #clock-init-cells = <1>;
 201                                         };
 202
 203                                         aclk_cpu_pre_div: aclk_cpu_pre_div {
 204                                                 compatible = "rockchip,rk3188-div-con";
 205                                                 rockchip,bits = <8 5>;
 206                                                 clocks = <&aclk_cpu_pre>;
 207                                                 clock-output-names = "aclk_cpu_pre";
 208                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 209                                                 #clock-cells = <0>;
 210                                                 rockchip,clkops-idx =
 211                                                         <CLKOPS_RATE_MUX_DIV>;
 212                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 213                                         };
 214
 215                                         /* reg[13]: reserved */
 216
 217                                         aclk_cpu_pre: aclk_cpu_pre_mux {
 218                                                 compatible = "rockchip,rk3188-mux-con";
 219                                                 rockchip,bits = <14 2>;
 220                                                 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
 221                                                 clock-output-names = "aclk_cpu_pre";
 222                                                 #clock-cells = <0>;
 223                                                 #clock-init-cells = <1>;
 224                                         };
 225
 226                                 };
 227
 228                                 clk_sel_con1: sel-con@0048 {
 229                                         compatible = "rockchip,rk3188-selcon";
 230                                         reg = <0x0048 0x4>;
 231                                         #address-cells = <1>;
 232                                         #size-cells = <1>;
 233
 234                                         pclk_dbg_div:  pclk_dbg_div {
 235                                                 compatible = "rockchip,rk3188-div-con";
 236                                                 rockchip,bits = <0 4>;
 237                                                 clocks = <&clk_core>;
 238                                                 clock-output-names = "pclk_dbg";
 239                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 240                                                 #clock-cells = <0>;
 241                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 242                                         };
 243
 244                                         aclk_core_pre: aclk_core_pre_div {
 245                                                 compatible = "rockchip,rk3188-div-con";
 246                                                 rockchip,bits = <4 3>;
 247                                                 clocks = <&clk_core>;
 248                                                 clock-output-names = "aclk_core_pre";
 249                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 250                                                 #clock-cells = <0>;
 251                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 252                                         };
 253
 254                                         /* reg[7]: reserved */
 255
 256                                         hclk_cpu_pre: hclk_cpu_pre_div {
 257                                                 compatible = "rockchip,rk3188-div-con";
 258                                                 rockchip,bits = <8 2>;
 259                                                 clocks = <&aclk_cpu_pre>;
 260                                                 clock-output-names = "hclk_cpu_pre";
 261                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 262                                                 #clock-cells = <0>;
 263                                                 #clock-init-cells = <1>;
 264                                         };
 265
 266                                         /* reg[11:10]: reserved */
 267
 268                                         pclk_cpu_pre: pclk_cpu_pre_div {
 269                                                 compatible = "rockchip,rk3188-div-con";
 270                                                 rockchip,bits = <12 3>;
 271                                                 clocks = <&aclk_cpu_pre>;
 272                                                 clock-output-names = "pclk_cpu_pre";
 273                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 274                                                 #clock-cells = <0>;
 275                                                 #clock-init-cells = <1>;
 276                                         };
 277
 278                                         /* reg[15]: reserved */
 279                                 };
 280
 281                                 clk_sel_con2: sel-con@004c {
 282                                         compatible = "rockchip,rk3188-selcon";
 283                                         reg = <0x004c 0x4>;
 284                                         #address-cells = <1>;
 285                                         #size-cells = <1>;
 286
 287                                         /* reg[3:0]: reserved */
 288
 289                                         clk_timer0: clk_timer0_mux {
 290                                                 compatible = "rockchip,rk3188-mux-con";
 291                                                 rockchip,bits = <4 1>;
 292                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 293                                                 clock-output-names = "clk_timer0";
 294                                                 #clock-cells = <0>;
 295                                                 #clock-init-cells = <1>;
 296                                         };
 297
 298                                         clk_timer1: clk_timer1_mux {
 299                                                 compatible = "rockchip,rk3188-mux-con";
 300                                                 rockchip,bits = <5 1>;
 301                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 302                                                 clock-output-names = "clk_timer1";
 303                                                 #clock-cells = <0>;
 304                                                 #clock-init-cells = <1>;
 305                                         };
 306
 307                                         clk_timer2: clk_timer2_mux {
 308                                                 compatible = "rockchip,rk3188-mux-con";
 309                                                 rockchip,bits = <6 1>;
 310                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 311                                                 clock-output-names = "clk_timer2";
 312                                                 #clock-cells = <0>;
 313                                                 #clock-init-cells = <1>;
 314                                         };
 315
 316                                         clk_timer3: clk_timer3_mux {
 317                                                 compatible = "rockchip,rk3188-mux-con";
 318                                                 rockchip,bits = <7 1>;
 319                                                 clocks = <&xin24m>, <&aclk_peri_pre>;
 320                                                 clock-output-names = "clk_timer3";
 321                                                 #clock-cells = <0>;
 322                                                 #clock-init-cells = <1>;
 323                                         };
 324
 325                                         /* reg[15:8]: reserved */
 326                                 };
 327
 328                                 clk_sel_con3: sel-con@0050 {
 329                                         compatible = "rockchip,rk3188-selcon";
 330                                         reg = <0x0050 0x4>;
 331                                         #address-cells = <1>;
 332                                         #size-cells = <1>;
 333
 334                                         clk_i2s_pll_div: clk_i2s_pll_div {
 335                                                 compatible = "rockchip,rk3188-div-con";
 336                                                 rockchip,bits = <0 7>;
 337                                                 clocks = <&clk_i2s_pll>;
 338                                                 clock-output-names = "clk_i2s_pll";
 339                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 340                                                 #clock-cells = <0>;
 341                                                 rockchip,clkops-idx =
 342                                                         <CLKOPS_RATE_MUX_DIV>;
 343                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 344                                         };
 345
 346                                         /* reg[7]: reserved */
 347
 348                                         clk_i2s: clk_i2s_mux {
 349                                                 compatible = "rockchip,rk3188-mux-con";
 350                                                 rockchip,bits = <8 2>;
 351                                                 clocks = <&clk_i2s_pll_div>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
 352                                                 clock-output-names = "clk_i2s";
 353                                                 #clock-cells = <0>;
 354                                                 rockchip,clkops-idx =
 355                                                         <CLKOPS_RATE_RK3288_I2S>;
 356                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 357                                         };
 358
 359                                         /* reg[11:10]: reserved */
 360
 361                                         clk_i2s_out: i2s_outclk_mux {
 362                                                 compatible = "rockchip,rk3188-mux-con";
 363                                                 rockchip,bits = <12 1>;
 364                                                 clocks = <&xin12m>, <&clk_i2s>;
 365                                                 clock-output-names = "i2s_clkout";
 366                                                 #clock-cells = <0>;
 367                                         };
 368
 369                                         /* reg[13]: reserved */
 370
 371                                         clk_i2s_pll: i2s_pll_mux {
 372                                                 compatible = "rockchip,rk3188-mux-con";
 373                                                 rockchip,bits = <14 2>;
 374                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 375                                                 clock-output-names = "clk_i2s_pll";
 376                                                 #clock-cells = <0>;
 377                                                 #clock-init-cells = <1>;
 378                                         };
 379
 380                                 };
 381
 382                                 clk_sel_con5: sel-con@0058 {
 383                                         compatible = "rockchip,rk3188-selcon";
 384                                         reg = <0x0058 0x4>;
 385                                         #address-cells = <1>;
 386                                         #size-cells = <1>;
 387
 388                                         spdif_div: spdif_div {
 389                                                 compatible = "rockchip,rk3188-div-con";
 390                                                 rockchip,bits = <0 7>;
 391                                                 clocks = <&clk_spdif_pll>;
 392                                                 clock-output-names = "clk_spdif_pll";
 393                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 394                                                 #clock-cells = <0>;
 395                                                 rockchip,clkops-idx =
 396                                                         <CLKOPS_RATE_MUX_DIV>;
 397                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 398                                         };
 399
 400                                         /* reg[7]: reserved */
 401
 402                                         clk_spdif: spdif_mux {
 403                                                 compatible = "rockchip,rk3188-mux-con";
 404                                                 rockchip,bits = <8 2>;
 405                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 406                                                 clock-output-names = "clk_spdif";
 407                                                 #clock-cells = <0>;
 408                                                 rockchip,clkops-idx =
 409                                                         <CLKOPS_RATE_RK3288_I2S>;
 410                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 411                                         };
 412
 413                                         clk_spdif_pll: spdif_pll_mux {
 414                                                 compatible = "rockchip,rk3188-mux-con";
 415                                                 rockchip,bits = <10 2>;
 416                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 417                                                 clock-output-names = "clk_spdif_pll";
 418                                                 #clock-cells = <0>;
 419                                                 #clock-init-cells = <1>;
 420                                         };
 421
 422                                         /* reg[15:12]: reserved */
 423                                 };
 424
 425                                 clk_sel_con7: sel-con@0060 {
 426                                         compatible = "rockchip,rk3188-selcon";
 427                                         reg = <0x0060 0x4>;
 428                                         #address-cells = <1>;
 429                                         #size-cells = <1>;
 430
 431                                         i2s_frac: i2s_frac {
 432                                                 compatible = "rockchip,rk3188-frac-con";
 433                                                 clocks = <&clk_i2s_pll>;
 434                                                 clock-output-names = "i2s_frac";
 435                                                 /* numerator    denominator */
 436                                                 rockchip,bits = <0 32>;
 437                                                 rockchip,clkops-idx =
 438                                                         <CLKOPS_RATE_FRAC>;
 439                                                 #clock-cells = <0>;
 440                                         };
 441                                 };
 442
 443                                 clk_sel_con9: sel-con@0068 {
 444                                         compatible = "rockchip,rk3188-selcon";
 445                                         reg = <0x0068 0x4>;
 446                                         #address-cells = <1>;
 447                                         #size-cells = <1>;
 448
 449                                         spdif_frac: spdif_frac {
 450                                                 compatible = "rockchip,rk3188-frac-con";
 451                                                 clocks = <&spdif_div>;
 452                                                 clock-output-names = "spdif_frac";
 453                                                 /* numerator    denominator */
 454                                                 rockchip,bits = <0 32>;
 455                                                 rockchip,clkops-idx =
 456                                                         <CLKOPS_RATE_FRAC>;
 457                                                 #clock-cells = <0>;
 458                                         };
 459                                 };
 460
 461                                 clk_sel_con10: sel-con@006c {
 462                                         compatible = "rockchip,rk3188-selcon";
 463                                         reg = <0x006c 0x4>;
 464                                         #address-cells = <1>;
 465                                         #size-cells = <1>;
 466
 467                                         aclk_peri_pre_div: aclk_peri_pre_div {
 468                                                 compatible = "rockchip,rk3188-div-con";
 469                                                 rockchip,bits = <0 5>;
 470                                                 clocks = <&aclk_peri_pre>;
 471                                                 clock-output-names = "aclk_peri_pre";
 472                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 473                                                 #clock-cells = <0>;
 474                                                 rockchip,clkops-idx =
 475                                                         <CLKOPS_RATE_MUX_DIV>;
 476                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 477                                         };
 478
 479                                         /* reg[7:5]: reserved */
 480
 481                                         hclk_peri_pre: hclk_peri_pre_div {
 482                                                 compatible = "rockchip,rk3188-div-con";
 483                                                 rockchip,bits = <8 2>;
 484                                                 clocks = <&aclk_peri_pre>;
 485                                                 clock-output-names = "hclk_peri_pre";
 486                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 487                                                 rockchip,div-relations =
 488                                                                 <0x0 1
 489                                                                  0x1 2
 490                                                                  0x2 4>;
 491                                                 #clock-cells = <0>;
 492                                                 #clock-init-cells = <1>;
 493                                         };
 494
 495                                         /* reg[11:10]: reserved */
 496
 497                                         pclk_peri_pre: pclk_peri_div {
 498                                                 compatible = "rockchip,rk3188-div-con";
 499                                                 rockchip,bits = <12 2>;
 500                                                 clocks = <&aclk_peri_pre>;
 501                                                 clock-output-names = "pclk_peri_pre";
 502                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 503                                                 rockchip,div-relations =
 504                                                                 <0x0 1
 505                                                                  0x1 2
 506                                                                  0x2 4
 507                                                                  0x3 8>;
 508                                                 #clock-cells = <0>;
 509                                                 #clock-init-cells = <1>;
 510                                         };
 511
 512                                         aclk_peri_pre: aclk_peri_pre_mux {
 513                                                 compatible = "rockchip,rk3188-mux-con";
 514                                                 rockchip,bits = <14 2>;
 515                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>;
 516                                                 clock-output-names = "aclk_peri_pre";
 517                                                 #clock-cells = <0>;
 518                                                 #clock-init-cells = <1>;
 519                                         };
 520                                 };
 521
 522                                 clk_sel_con11: sel-con@0070 {
 523                                         compatible = "rockchip,rk3188-selcon";
 524                                         reg = <0x0070 0x4>;
 525                                         #address-cells = <1>;
 526                                         #size-cells = <1>;
 527
 528                                         clk_sdmmc0_div: clk_sdmmc0_div {
 529                                                 compatible = "rockchip,rk3188-div-con";
 530                                                 rockchip,bits = <0 6>;
 531                                                 clocks = <&clk_sdmmc0>;
 532                                                 clock-output-names = "clk_sdmmc0";
 533                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 534                                                 #clock-cells = <0>;
 535                                                 rockchip,clkops-idx =
 536                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 537                                         };
 538
 539                                         /* reg[7]: reserved */
 540
 541                                         clk_sdio_div: clk_sdio_div {
 542                                                 compatible = "rockchip,rk3188-div-con";
 543                                                 rockchip,bits = <8 7>;
 544                                                 clocks = <&clk_sdio>;
 545                                                 clock-output-names = "clk_sdio";
 546                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 547                                                 #clock-cells = <0>;
 548                                                 rockchip,clkops-idx =
 549                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 550                                         };
 551
 552                                         /* reg[15]: reserved */
 553
 554                                 };
 555
 556                                 clk_sel_con12: sel-con@0074 {
 557                                         compatible = "rockchip,rk3188-selcon";
 558                                         reg = <0x0074 0x4>;
 559                                         #address-cells = <1>;
 560                                         #size-cells = <1>;
 561
 562                                         clk_emmc_div: clk_emmc_div {
 563                                                 compatible = "rockchip,rk3188-div-con";
 564                                                 rockchip,bits = <0 7>;
 565                                                 clocks = <&clk_emmc>;
 566                                                 clock-output-names = "clk_emmc";
 567                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 568                                                 #clock-cells = <0>;
 569                                                 rockchip,clkops-idx =
 570                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 571                                         };
 572
 573                                         /* reg[7]: reserved */
 574
 575                                         clk_sdmmc0: clk_sdmmc0_mux {
 576                                                 compatible = "rockchip,rk3188-mux-con";
 577                                                 rockchip,bits = <8 2>;
 578                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 579                                                 clock-output-names = "clk_sdmmc0";
 580                                                 #clock-cells = <0>;
 581                                         };
 582
 583                                         clk_sdio: clk_sdio_mux {
 584                                                 compatible = "rockchip,rk3188-mux-con";
 585                                                 rockchip,bits = <10 2>;
 586                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 587                                                 clock-output-names = "clk_sdio";
 588                                                 #clock-cells = <0>;
 589                                         };
 590
 591                                         clk_emmc: clk_emmc_mux {
 592                                                 compatible = "rockchip,rk3188-mux-con";
 593                                                 rockchip,bits = <12 2>;
 594                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&xin24m>;
 595                                                 clock-output-names = "clk_emmc";
 596                                                 #clock-cells = <0>;
 597                                         };
 598
 599                                         /* reg[15:14]: reserved */
 600                                 };
 601
 602                                 clk_sel_con13: sel-con@0078 {
 603                                         compatible = "rockchip,rk3188-selcon";
 604                                         reg = <0x0078 0x4>;
 605                                         #address-cells = <1>;
 606                                         #size-cells = <1>;
 607
 608                                         clk_uart0_div: clk_uart0_div {
 609                                                 compatible = "rockchip,rk3188-div-con";
 610                                                 rockchip,bits = <0 7>;
 611                                                 clocks = <&clk_uart_pll>;
 612                                                 clock-output-names = "clk_uart0_div";
 613                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 614                                                 #clock-cells = <0>;
 615                                         };
 616
 617                                         /* reg[7]: reserved */
 618
 619                                         clk_uart0: clk_uart0_mux {
 620                                                 compatible = "rockchip,rk3188-mux-con";
 621                                                 rockchip,bits = <8 2>;
 622                                                 clocks = <&clk_uart0_div>, <&uart0_frac>, <&xin24m>;
 623                                                 clock-output-names = "clk_uart0";
 624                                                 #clock-cells = <0>;
 625                                                 rockchip,clkops-idx =
 626                                                         <CLKOPS_RATE_RK3288_I2S>;
 627                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 628                                         };
 629
 630                                         clk_uart_pll: clk_uart_pll_mux {
 631                                                 compatible = "rockchip,rk3188-mux-con";
 632                                                 rockchip,bits = <10 2>;
 633                                                 clocks = <&clk_apll>,<&clk_dpll>, <&clk_gpll>, <&usb_480m>;
 634                                                 clock-output-names = "clk_uart_pll";
 635                                                 #clock-cells = <0>;
 636                                                 #clock-init-cells = <1>;
 637                                         };
 638
 639                                         /* reg[15:12]: reserved */
 640
 641                                 };
 642
 643                                 clk_sel_con14: sel-con@007c {
 644                                         compatible = "rockchip,rk3188-selcon";
 645                                         reg = <0x007c 0x4>;
 646                                         #address-cells = <1>;
 647                                         #size-cells = <1>;
 648
 649                                         clk_uart1_div: clk_uart1_div {
 650                                                 compatible = "rockchip,rk3188-div-con";
 651                                                 rockchip,bits = <0 7>;
 652                                                 clocks = <&clk_uart_pll>;
 653                                                 clock-output-names = "clk_uart1_div";
 654                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 655                                                 #clock-cells = <0>;
 656                                         };
 657
 658                                         /* reg[7]: reserved */
 659
 660                                         clk_uart1: clk_uart1_mux {
 661                                                 compatible = "rockchip,rk3188-mux-con";
 662                                                 rockchip,bits = <8 2>;
 663                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 664                                                 clock-output-names = "clk_uart1";
 665                                                 #clock-cells = <0>;
 666                                                 rockchip,clkops-idx =
 667                                                         <CLKOPS_RATE_RK3288_I2S>;
 668                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 669                                         };
 670
 671                                         /* reg[15:10]: reserved */
 672                                 };
 673
 674                                 clk_sel_con15: sel-con@0080 {
 675                                         compatible = "rockchip,rk3188-selcon";
 676                                         reg = <0x0080 0x4>;
 677                                         #address-cells = <1>;
 678                                         #size-cells = <1>;
 679
 680                                         clk_uart2_div: clk_uart2_div {
 681                                                 compatible = "rockchip,rk3188-div-con";
 682                                                 rockchip,bits = <0 7>;
 683                                                 clocks = <&clk_uart_pll>;
 684                                                 clock-output-names = "clk_uart2_div";
 685                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 686                                                 #clock-cells = <0>;
 687                                         };
 688
 689                                         /* reg[7]: reserved */
 690
 691                                         clk_uart2: clk_uart2_mux {
 692                                                 compatible = "rockchip,rk3188-mux-con";
 693                                                 rockchip,bits = <8 2>;
 694                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
 695                                                 clock-output-names = "clk_uart2";
 696                                                 #clock-cells = <0>;
 697                                                 rockchip,clkops-idx =
 698                                                         <CLKOPS_RATE_RK3288_I2S>;
 699                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 700                                         };
 701
 702                                         /* reg[15:10]: reserved */
 703                                 };
 704
 705                                 clk_sel_con16: sel-con@0084 {
 706                                         compatible = "rockchip,rk3188-selcon";
 707                                         reg = <0x0084 0x4>;
 708                                         #address-cells = <1>;
 709                                         #size-cells = <1>;
 710
 711                                         clk_sfc: clk_sfc_mux {
 712                                                 compatible = "rockchip,rk3188-mux-con";
 713                                                 rockchip,bits = <0 2>;
 714                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>, <&xin24m>;
 715                                                 clock-output-names = "clk_sfc";
 716                                                 #clock-cells = <0>;
 717                                         };
 718
 719                                         clk_sfc_div: clk_sfc_div {
 720                                                 compatible = "rockchip,rk3188-div-con";
 721                                                 rockchip,bits = <2 5>;
 722                                                 clocks = <&clk_sfc>;
 723                                                 clock-output-names = "clk_sfc";
 724                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 725                                                 #clock-cells = <0>;
 726                                                 rockchip,clkops-idx =
 727                                                         <CLKOPS_RATE_MUX_DIV>;
 728                                         };
 729
 730                                         /* reg[7]: reserved */
 731
 732                                         clk_nandc: clk_nandc_mux {
 733                                                 compatible = "rockchip,rk3188-mux-con";
 734                                                 rockchip,bits = <8 2>;
 735                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 736                                                 clock-output-names = "clk_nandc";
 737                                                 #clock-cells = <0>;
 738                                         };
 739
 740                                         clk_nandc_div: clk_nandc_div {
 741                                                 compatible = "rockchip,rk3188-div-con";
 742                                                 rockchip,bits = <10 5>;
 743                                                 clocks = <&clk_nandc>;
 744                                                 clock-output-names = "clk_nandc";
 745                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 746                                                 #clock-cells = <0>;
 747                                                 rockchip,clkops-idx =
 748                                                         <CLKOPS_RATE_MUX_DIV>;
 749                                         };
 750
 751                                         /* reg[31:15]: reserved */
 752                                 };
 753
 754                                 clk_sel_con17: sel-con@0088 {
 755                                         compatible = "rockchip,rk3188-selcon";
 756                                         reg = <0x0088 0x4>;
 757                                         #address-cells = <1>;
 758                                         #size-cells = <1>;
 759
 760                                         uart0_frac: uart0_frac {
 761                                                 compatible = "rockchip,rk3188-frac-con";
 762                                                 clocks = <&clk_uart0_div>;
 763                                                 clock-output-names = "uart0_frac";
 764                                                 /* numerator    denominator */
 765                                                 rockchip,bits = <0 32>;
 766                                                 rockchip,clkops-idx =
 767                                                         <CLKOPS_RATE_FRAC>;
 768                                                 #clock-cells = <0>;
 769                                         };
 770                                 };
 771
 772                                 clk_sel_con18: sel-con@008c {
 773                                         compatible = "rockchip,rk3188-selcon";
 774                                         reg = <0x008c 0x4>;
 775                                         #address-cells = <1>;
 776                                         #size-cells = <1>;
 777
 778                                         uart1_frac: uart1_frac {
 779                                                 compatible = "rockchip,rk3188-frac-con";
 780                                                 clocks = <&clk_uart1_div>;
 781                                                 clock-output-names = "uart1_frac";
 782                                                 /* numerator    denominator */
 783                                                 rockchip,bits = <0 32>;
 784                                                 rockchip,clkops-idx =
 785                                                         <CLKOPS_RATE_FRAC>;
 786                                                 #clock-cells = <0>;
 787                                         };
 788                                 };
 789
 790                                 clk_sel_con19: sel-con@0090 {
 791                                         compatible = "rockchip,rk3188-selcon";
 792                                         reg = <0x0090 0x4>;
 793                                         #address-cells = <1>;
 794                                         #size-cells = <1>;
 795
 796                                         uart2_frac: uart2_frac {
 797                                                 compatible = "rockchip,rk3188-frac-con";
 798                                                 clocks = <&clk_uart2_div>;
 799                                                 clock-output-names = "uart2_frac";
 800                                                 /* numerator    denominator */
 801                                                 rockchip,bits = <0 32>;
 802                                                 rockchip,clkops-idx =
 803                                                         <CLKOPS_RATE_FRAC>;
 804                                                 #clock-cells = <0>;
 805                                         };
 806
 807                                 };
 808
 809                                 clk_sel_con20: sel-con@0094 {
 810                                         compatible = "rockchip,rk3188-selcon";
 811                                         reg = <0x0094 0x4>;
 812                                         #address-cells = <1>;
 813                                         #size-cells = <1>;
 814
 815                                         clk_hevc_core: clk_hevc_core_mux {
 816                                                 compatible = "rockchip,rk3188-mux-con";
 817                                                 rockchip,bits = <0 2>;
 818                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 819                                                 clock-output-names = "clk_hevc_core";
 820                                                 #clock-cells = <0>;
 821                                                 #clock-init-cells = <1>;
 822                                         };
 823
 824                                         clk_hevc_core_div: clk_hevc_core_div {
 825                                                 compatible = "rockchip,rk3188-div-con";
 826                                                 rockchip,bits = <2 5>;
 827                                                 clocks = <&clk_hevc_core>;
 828                                                 clock-output-names = "clk_hevc_core";
 829                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 830                                                 #clock-cells = <0>;
 831                                                 rockchip,clkops-idx =
 832                                                         <CLKOPS_RATE_MUX_DIV>;
 833                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 834                                         };
 835
 836                                         /* reg[31:7]: reserved */
 837
 838                                 };
 839
 840                                 clk_sel_con21: sel-con@0098 {
 841                                         compatible = "rockchip,rk3188-selcon";
 842                                         reg = <0x0098 0x4>;
 843                                         #address-cells = <1>;
 844                                         #size-cells = <1>;
 845
 846                                         clk_mac_pll: clk_mac_pll_mux {
 847                                                 compatible = "rockchip,rk3188-mux-con";
 848                                                 rockchip,bits = <0 2>;
 849                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 850                                                 clock-output-names = "clk_mac_pll";
 851                                                 #clock-cells = <0>;
 852                                                 #clock-init-cells = <1>;
 853                                         };
 854
 855                                         /* reg[2]: reserved */
 856
 857                                         clk_mac_ref: clk_mac_ref_mux {
 858                                                 compatible = "rockchip,rk3188-mux-con";
 859                                                 rockchip,bits = <3 1>;
 860                                                 clocks = <&clk_mac_pll_div>, <&rmii_clkin>;
 861                                                 clock-output-names = "clk_mac_ref";
 862                                                 #clock-cells = <0>;
 863                                                 rockchip,clkops-idx =
 864                                                         <CLKOPS_RATE_MAC_REF>;
 865                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 866                                                 #clock-init-cells = <1>;
 867                                         };
 868
 869                                         clk_mac_ref_div: clk_mac_ref_div {
 870                                                 compatible = "rockchip,rk3188-div-con";
 871                                                 rockchip,bits = <4 5>;
 872                                                 clocks = <&clk_mac_ref>;
 873                                                 clock-output-names = "clk_mac";
 874                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 875                                                 #clock-cells = <0>;
 876                                                 #clock-init-cells = <1>;
 877                                         };
 878
 879                                         clk_mac_pll_div: clk_mac_pll_div {
 880                                                 compatible = "rockchip,rk3188-div-con";
 881                                                 rockchip,bits = <9 5>;
 882                                                 clocks = <&clk_mac_pll>;
 883                                                 clock-output-names = "clk_mac_pll";
 884                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 885                                                 #clock-cells = <0>;
 886                                                 rockchip,clkops-idx =
 887                                                         <CLKOPS_RATE_MUX_DIV>;
 888                                                 #clock-init-cells = <1>;
 889                                         };
 890
 891                                         /* reg[15:14]: reserved */
 892                                 };
 893
 894                                 clk_sel_con25: sel-con@00a8 {
 895                                         compatible = "rockchip,rk3188-selcon";
 896                                         reg = <0x00a8 0x4>;
 897                                         #address-cells = <1>;
 898                                         #size-cells = <1>;
 899
 900                                         clk_spi0_div: clk_spi0_div {
 901                                                 compatible = "rockchip,rk3188-div-con";
 902                                                 rockchip,bits = <0 7>;
 903                                                 clocks = <&clk_spi0>;
 904                                                 clock-output-names = "clk_spi0";
 905                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 906                                                 #clock-cells = <0>;
 907                                                 rockchip,clkops-idx =
 908                                                         <CLKOPS_RATE_MUX_DIV>;
 909                                         };
 910
 911                                         /* reg[7]: reserved */
 912
 913                                         clk_spi0: clk_spi0_mux {
 914                                                 compatible = "rockchip,rk3188-mux-con";
 915                                                 rockchip,bits = <8 2>;
 916                                                 clocks = <&clk_apll>, <&clk_dpll>,<&clk_gpll>;
 917                                                 clock-output-names = "clk_spi0";
 918                                                 #clock-cells = <0>;
 919                                         };
 920
 921                                         /* reg[15:10]: reserved */
 922
 923                                 };
 924
 925                                 clk_sel_con26: sel-con@00ac {
 926                                         compatible = "rockchip,rk3188-selcon";
 927                                         reg = <0x00ac 0x4>;
 928                                         #address-cells = <1>;
 929                                         #size-cells = <1>;
 930
 931                                         ddr_div: ddr_div {
 932                                                 compatible = "rockchip,rk3188-div-con";
 933                                                 rockchip,bits = <0 2>;
 934                                                 clocks = <&clk_ddr>;
 935                                                 clock-output-names = "clk_ddr";
 936                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 937                                                 rockchip,div-relations =
 938                                                                 <0x0 1
 939                                                                  0x1 2
 940                                                                  0x3 4>;
 941                                                 #clock-cells = <0>;
 942                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 943                                                                         CLK_SET_RATE_NO_REPARENT)>;
 944                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
 945                                         };
 946
 947                                         /* reg[7:1]: reserved */
 948
 949                                         clk_ddr: ddr_clk_pll_mux {
 950                                                 compatible = "rockchip,rk3188-mux-con";
 951                                                 rockchip,bits = <8 1>;
 952                                                 clocks = <&clk_dpll>, <&dummy>;
 953                                                 clock-output-names = "clk_ddr";
 954                                                 #clock-cells = <0>;
 955                                         };
 956
 957                                         /* reg[15:9]: reserved */
 958                                 };
 959
 960                                 clk_sel_con28: sel-con@00b4 {
 961                                         compatible = "rockchip,rk3188-selcon";
 962                                         reg = <0x00b4 0x4>;
 963                                         #address-cells = <1>;
 964                                         #size-cells = <1>;
 965
 966                                         dclk_lcdc1: dclk_lcdc1_mux {
 967                                                 compatible = "rockchip,rk3188-mux-con";
 968                                                 rockchip,bits = <0 2>;
 969                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
 970                                                 clock-output-names = "dclk_lcdc1";
 971                                                 #clock-cells = <0>;
 972                                                 #clock-init-cells = <1>;
 973                                         };
 974
 975                                         /* reg[7:2]: reserved */
 976
 977                                         dclk_lcdc1_div: dclk_lcdc1_div {
 978                                                 compatible = "rockchip,rk3188-div-con";
 979                                                 rockchip,bits = <8 8>;
 980                                                 clocks = <&dclk_lcdc1>;
 981                                                 clock-output-names = "dclk_lcdc1";
 982                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 983                                                 #clock-cells = <0>;
 984                                                 rockchip,clkops-idx =
 985                                                         <CLKOPS_RATE_MUX_DIV>;
 986                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 987                                         };
 988                                 };
 989
 990                                 clk_sel_con30: sel-con@00bc {
 991                                         compatible = "rockchip,rk3188-selcon";
 992                                         reg = <0x00bc 0x4>;
 993                                         #address-cells = <1>;
 994                                         #size-cells = <1>;
 995
 996                                         clk_testout_div: clk_testout_div {
 997                                                 compatible = "rockchip,rk3188-div-con";
 998                                                 rockchip,bits = <0 5>;
 999                                                 clocks = <&dummy>;
1000                                                 clock-output-names = "clk_testout";
1001                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1002                                                 #clock-cells = <0>;
1003                                                 #clock-init-cells = <1>;
1004                                         };
1005
1006                                         /* reg[7:5]: reserved */
1007
1008                                         hclk_vio_pre_div: hclk_vio_pre_div {
1009                                                 compatible = "rockchip,rk3188-div-con";
1010                                                 rockchip,bits = <8 5>;
1011                                                 clocks = <&hclk_vio_pre>;
1012                                                 clock-output-names = "hclk_vio_pre";
1013                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1014                                                 #clock-cells = <0>;
1015                                                 rockchip,clkops-idx =
1016                                                         <CLKOPS_RATE_MUX_DIV>;
1017                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1018                                         };
1019
1020                                         /* reg[13]: reserved */
1021
1022                                         hclk_vio_pre: hclk_vio_pre_mux {
1023                                                 compatible = "rockchip,rk3188-mux-con";
1024                                                 rockchip,bits = <14 2>;
1025                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1026                                                 clock-output-names = "hclk_vio_pre";
1027                                                 #clock-cells = <0>;
1028                                                 #clock-init-cells = <1>;
1029                                         };
1030
1031                                 };
1032
1033                                 clk_sel_con31: sel-con@00c0 {
1034                                         compatible = "rockchip,rk3188-selcon";
1035                                         reg = <0x00c0 0x4>;
1036                                         #address-cells = <1>;
1037                                         #size-cells = <1>;
1038
1039                                         clk_hdmi: clk_hdmi_mux {
1040                                                 compatible = "rockchip,rk3188-mux-con";
1041                                                 rockchip,bits = <0 1>;
1042                                                 clocks = <&dclk_lcdc1_div>, <&dummy>;
1043                                                 clock-output-names = "clk_hdmi";
1044                                                 #clock-cells = <0>;
1045                                         };
1046
1047                                         /* reg[7:1]: reserved */
1048
1049                                         aclk_vio_pre_div: aclk_vio_pre_div {
1050                                                 compatible = "rockchip,rk3188-div-con";
1051                                                 rockchip,bits = <8 5>;
1052                                                 clocks = <&aclk_vio_pre>;
1053                                                 clock-output-names = "aclk_vio_pre";
1054                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1055                                                 #clock-cells = <0>;
1056                                                 rockchip,clkops-idx =
1057                                                         <CLKOPS_RATE_MUX_DIV>;
1058                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1059                                         };
1060
1061                                         /* reg[13]: reserved */
1062
1063                                         aclk_vio_pre: aclk_vio_pre_mux {
1064                                                 compatible = "rockchip,rk3188-mux-con";
1065                                                 rockchip,bits = <14 2>;
1066                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1067                                                 clock-output-names = "aclk_vio_pre";
1068                                                 #clock-cells = <0>;
1069                                                 #clock-init-cells = <1>;
1070                                         };
1071
1072                                 };
1073
1074                                 clk_sel_con32: sel-con@00c4 {
1075                                         compatible = "rockchip,rk3188-selcon";
1076                                         reg = <0x00c4 0x4>;
1077                                         #address-cells = <1>;
1078                                         #size-cells = <1>;
1079
1080                                         /* reg[7:0]: reserved */
1081
1082                                         aclk_vcodec_pre_div: aclk_vcodec_pre_div {
1083                                                 compatible = "rockchip,rk3188-div-con";
1084                                                 rockchip,bits = <8 5>;
1085                                                 clocks = <&aclk_vcodec_pre>;
1086                                                 clock-output-names = "aclk_vcodec_pre";
1087                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1088                                                 #clock-cells = <0>;
1089                                                 rockchip,clkops-idx =
1090                                                         <CLKOPS_RATE_MUX_DIV>;
1091                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1092                                         };
1093
1094                                         /* reg[13]: reserved */
1095
1096                                         aclk_vcodec_pre: aclk_vcodec_pre_mux {
1097                                                 compatible = "rockchip,rk3188-mux-con";
1098                                                 rockchip,bits = <14 2>;
1099                                                 clocks = <&clk_apll>, <&clk_dpll>, <&clk_gpll>;
1100                                                 clock-output-names = "aclk_vcodec_pre";
1101                                                 #clock-cells = <0>;
1102                                                 #clock-init-cells = <1>;
1103                                         };
1104                                 };
1105
1106                                 clk_sel_con34: sel-con@00cc {
1107                                         compatible = "rockchip,rk3188-selcon";
1108                                         reg = <0x00cc 0x4>;
1109                                         #address-cells = <1>;
1110                                         #size-cells = <1>;
1111
1112                                         clk_gpu_div: clk_gpu_div {
1113                                                 compatible = "rockchip,rk3188-div-con";
1114                                                 rockchip,bits = <0 5>;
1115                                                 clocks = <&clk_gpu>;
1116                                                 clock-output-names = "clk_gpu";
1117                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1118                                                 #clock-cells = <0>;
1119                                                 rockchip,clkops-idx =
1120                                                         <CLKOPS_RATE_MUX_DIV>;
1121                                                 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1122                                         };
1123
1124                                         /* reg[7:5]: reserved */
1125
1126                                         clk_gpu: clk_gpu_mux {
1127                                                 compatible = "rockchip,rk3188-mux-con";
1128                                                 rockchip,bits = <8 2>;
1129                                                 clocks = <&dummy>, <&dummy>, <&clk_gpll>;
1130                                                 clock-output-names = "clk_gpu";
1131                                                 #clock-cells = <0>;
1132                                                 #clock-init-cells = <1>;
1133                                         };
1134
1135                                         /* reg[15:10]: reserved */
1136
1137                                 };
1138
1139                         };
1140
1141
1142                         /* Gate control regs */
1143                         clk_gate_cons {
1144                                 compatible = "rockchip,rk-gate-cons";
1145                                 #address-cells = <1>;
1146                                 #size-cells = <1>;
1147                                 ranges ;
1148
1149                                 clk_gates0: gate-clk@00d0{
1150                                         compatible = "rockchip,rk3188-gate-clk";
1151                                         reg = <0x00d0 0x4>;
1152                                         clocks =
1153                                                 <&clk_core>,            <&clk_gpll>,
1154                                                 <&clk_dpll>,    <&aclk_cpu_pre>,
1155
1156                                                 <&aclk_cpu_pre>,        <&aclk_cpu_pre>,
1157                                                 <&clk_gpll>,            <&clk_core>,
1158
1159                                                 <&clk_gpll>,    <&clk_i2s_pll>,
1160                                                 <&i2s_frac>,    <&hclk_vio_pre>,
1161
1162                                                 <&dummy>,               <&clk_i2s_out>,
1163                                                 <&clk_i2s>,             <&dummy>;
1164
1165                                         clock-output-names =
1166                                                 "pclk_dbg",                     "reserved",      /* do not use bit1 = "cpu_gpll" */
1167                                                 "reserved",             "aclk_cpu_pre",
1168
1169                                                 "hclk_cpu_pre",         "pclk_cpu_pre",
1170                                                 "reserved",             "aclk_core_pre",
1171
1172                                                 "reserved",             "clk_i2s_pll",
1173                                                 "i2s_frac",             "hclk_vio_pre",
1174
1175                                                 "clk_cryto",            "clk_i2s_out",
1176                                                 "clk_i2s",              "clk_testout";
1177                                         rockchip,suspend-clkgating-setting=<0x19ff 0x19ff>;
1178
1179                                         #clock-cells = <1>;
1180                                 };
1181
1182                                 clk_gates1: gate-clk@00d4{
1183                                         compatible = "rockchip,rk3188-gate-clk";
1184                                         reg = <0x00d4 0x4>;
1185                                         clocks =
1186                                                 <&clk_timer0>,          <&clk_timer1>,
1187                                                 <&dummy>,               <&jtag_tck>,
1188
1189                                                 <&aclk_vio_pre>,                <&xin12m>,
1190                                                 <&dummy>,               <&dummy>,
1191
1192                                                 <&clk_uart0_div>,               <&uart0_frac>,
1193                                                 <&clk_uart1_div>,               <&uart1_frac>,
1194
1195                                                 <&clk_uart2_div>,               <&uart2_frac>,
1196                                                 <&dummy>,               <&dummy>;
1197
1198                                         clock-output-names =
1199                                                 "clk_timer0",           "clk_timer1",
1200                                                 "reserved",             "clk_jatg",
1201
1202                                                 "aclk_vio_pre",         "clk_otgphy0",
1203                                                 "clk_otgphy1",                  "reserved",
1204
1205                                                 "clk_uart0_div",        "uart0_frac",
1206                                                 "clk_uart1_div",        "uart1_frac",
1207
1208                                                 "clk_uart2_div",        "uart2_frac",
1209                                                 "reserved",     "reserved";
1210
1211                                          rockchip,suspend-clkgating-setting=<0xc0af 0xc0af>;
1212                                         #clock-cells = <1>;
1213                                 };
1214
1215                                 clk_gates2: gate-clk@00d8 {
1216                                         compatible = "rockchip,rk3188-gate-clk";
1217                                         reg = <0x00d8 0x4>;
1218                                         clocks =
1219                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1220                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1221
1222                                                 <&clk_timer2>,          <&clk_timer3>,
1223                                                 <&clk_mac_ref>,         <&dummy>,
1224
1225                                                 <&dummy>,               <&clk_spi0>,
1226                                                 <&clk_spdif_pll>,               <&clk_sdmmc0>,
1227
1228                                                 <&spdif_frac>,          <&clk_sdio>,
1229                                                 <&clk_emmc>,            <&dummy>;
1230
1231                                         clock-output-names =
1232                                                 "aclk_peri",            "aclk_peri_pre",
1233                                                 "hclk_peri_pre",                "pclk_peri_pre",
1234
1235                                                 "clk_timer2",           "clk_timer3",
1236                                                 "clk_mac",              "reserved",
1237
1238                                                 "reserved",             "clk_spi0",
1239                                                 "clk_spdif_pll",                "clk_sdmmc0",
1240
1241                                                 "spdif_frac",           "clk_sdio",
1242                                                 "clk_emmc",             "reserved";
1243                                             rockchip,suspend-clkgating-setting=<0x81bf 0x81bf>;
1244
1245                                         #clock-cells = <1>;
1246                                 };
1247
1248                                 clk_gates3: gate-clk@00dc {
1249                                         compatible = "rockchip,rk3188-gate-clk";
1250                                         reg = <0x00dc 0x4>;
1251                                         clocks =
1252                                                 <&dummy>,               <&dummy>,
1253                                                 <&dclk_lcdc1>,          <&dummy>,
1254
1255                                                 <&dummy>,                       <&hclk_peri_pre>,
1256                                                 <&dummy>,               <&dummy>,
1257
1258                                                 <&pclk_cpu_pre>,                <&dummy>,
1259                                                 <&dummy>,               <&aclk_vcodec_pre>,
1260
1261                                                 <&aclk_vcodec_pre>,             <&clk_gpu>,
1262                                                 <&hclk_peri_pre>,               <&dummy>;
1263
1264                                         clock-output-names =
1265                                                 "reserved",             "reserved",
1266                                                 "dclk_lcdc1",           "reserved",
1267
1268                                                 "reserved",             "g_hclk_mac",
1269                                                 "reserved",             "reserved",
1270
1271                                                 "g_pclk_hdmi",          "reserved",
1272                                                 "reserved",             "aclk_vcodec_pre",
1273
1274                                                 "hclk_vcodec",          "clk_gpu",
1275                                                 "g_hclk_sfc",           "reserved";
1276                                                 rockchip,suspend-clkgating-setting=<0xa7fb 0xa7fb>;
1277
1278                                         #clock-cells = <1>;
1279                                 };
1280
1281                                 clk_gates4: gate-clk@00e0{
1282                                         compatible = "rockchip,rk3188-gate-clk";
1283                                         reg = <0x00e0 0x4>;
1284                                         clocks =
1285                                                 <&hclk_peri_pre>,               <&pclk_peri_pre>,
1286                                                 <&aclk_peri_pre>,               <&aclk_peri_pre>,
1287
1288                                                 <&dummy>,               <&dummy>,
1289                                                 <&dummy>,               <&dummy>,
1290
1291                                                 <&dummy>,               <&dummy>,
1292                                                 <&aclk_cpu_pre>,                <&dummy>,
1293
1294                                                 <&aclk_cpu_pre>,                <&dummy>,
1295                                                 <&dummy>,               <&dummy>;
1296
1297                                         clock-output-names =
1298                                                 "g_hp_axi_matrix",              "g_pp_axi_matrix",
1299                                                 "g_aclk_cpu_peri",              "g_ap_axi_matrix",
1300
1301                                                 "reserved",             "g_hclk_mac",
1302                                                 "reserved",             "reserved",
1303
1304                                                 "reserved",             "reserved",
1305                                                 "g_aclk_strc_sys",              "reserved",
1306
1307                                                 /* Not use these ddr gates */
1308                                                 "g_aclk_intmem",                "reserved",
1309                                                 "reserved",             "reserved";
1310
1311                                         rockchip,suspend-clkgating-setting = <0xffff 0xffff>;
1312                                         #clock-cells = <1>;
1313                                 };
1314
1315                                 clk_gates5: gate-clk@00e4 {
1316                                         compatible = "rockchip,rk3188-gate-clk";
1317                                         reg = <0x00e4 0x4>;
1318                                         clocks =
1319                                                 <&dummy>,               <&aclk_peri_pre>,
1320                                                 <&pclk_peri_pre>,               <&dummy>,
1321
1322                                                 <&pclk_cpu_pre>,                <&dummy>,
1323                                                 <&hclk_cpu_pre>,                <&pclk_cpu_pre>,
1324
1325                                                 <&dummy>,               <&hclk_peri_pre>,
1326                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1327
1328                                                 <&dummy>,               <&hclk_peri_pre>,
1329                                                 <&pclk_cpu_pre>,                <&dummy>;
1330
1331                                         clock-output-names =
1332                                                 "reserved",             "g_aclk_dmac2",
1333                                                 "g_pclk_efuse", "reserved",
1334
1335                                                 "g_pclk_grf",           "reserved",
1336                                                 "g_hclk_rom",           "g_pclk_ddrupctl",
1337
1338                                                 "reserved",             "g_hclk_nandc",
1339                                                 "g_hclk_sdmmc0",                "g_hclk_sdio",
1340
1341                                                 "reserved",             "g_hclk_otg0",
1342                                                 "g_pclk_acodec",                "reserved";
1343
1344                                         rockchip,suspend-clkgating-setting = <0x91fd 0x91fd>;
1345
1346                                         #clock-cells = <1>;
1347                                 };
1348
1349                                 clk_gates6: gate-clk@00e8 {
1350                                         compatible = "rockchip,rk3188-gate-clk";
1351                                         reg = <0x00e8 0x4>;
1352                                         clocks =
1353                                                 <&dummy>,               <&dummy>,
1354                                                 <&dummy>,               <&dummy>,
1355
1356                                                 <&dummy>,               <&dummy>,
1357                                                 <&dummy>,               <&dummy>,
1358
1359                                                 <&dummy>,               <&dummy>,
1360                                                 <&dummy>,                       <&dummy>,
1361
1362                                                 <&hclk_vio_pre>,                <&aclk_vio_pre>,
1363                                                 <&dummy>,               <&dummy>;
1364
1365                                         clock-output-names =
1366                                                 "reserved",             "reserved",
1367                                                 "reserved",             "reserved",
1368
1369                                                 "reserved",             "reserved",
1370                                                 "reserved",             "reserved",
1371
1372                                                 "reserved",             "reserved",
1373                                                 "reserved",             "reserved",
1374
1375                                                 "g_hclk_vio_bus",               "g_aclk_vio",
1376                                                 "reserved",             "reserved";
1377
1378                                         rockchip,suspend-clkgating-setting = <0xffff 0xffff>;
1379
1380                                         #clock-cells = <1>;
1381                                 };
1382
1383                                 clk_gates7: gate-clk@00ec {
1384                                         compatible = "rockchip,rk3188-gate-clk";
1385                                         reg = <0x00ec 0x4>;
1386                                         clocks =
1387                                                 <&hclk_peri_pre>,               <&dummy>,
1388                                                 <&hclk_peri_pre>,               <&hclk_peri_pre>,
1389
1390                                                 <&dummy>,               <&dummy>,
1391                                                 <&dummy>,               <&pclk_peri_pre>,
1392
1393                                                 <&dummy>,               <&dummy>,
1394                                                 <&pclk_peri_pre>,               <&dummy>,
1395
1396                                                 <&pclk_peri_pre>,               <&dummy>,
1397                                                 <&dummy>,               <&pclk_peri_pre>;
1398
1399                                         clock-output-names =
1400                                                 "g_hclk_emmc",          "reserved",
1401                                                 "g_hclk_i2s",           "g_hclk_otg1",
1402
1403                                                 "reserved",             "reserved",
1404                                                 "reserved",             "g_pclk_timer0",
1405
1406                                                 "reserved",             "reserved",
1407                                                 "g_pclk_pwm",           "reserved",
1408
1409                                                 "g_pclk_spi",           "reserved",
1410                                                 "reserved",             "g_pclk_wdt";
1411
1412                                         rockchip,suspend-clkgating-setting = <0x6ff2 0x6ff2>;
1413
1414                                         #clock-cells = <1>;
1415                                 };
1416
1417                                 clk_gates8: gate-clk@00f0 {
1418                                         compatible = "rockchip,rk3188-gate-clk";
1419                                         reg = <0x00f0 0x4>;
1420                                         clocks =
1421                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1422                                                 <&pclk_peri_pre>,               <&dummy>,
1423
1424                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1425                                                 <&pclk_peri_pre>,               <&dummy>,
1426
1427                                                 <&dummy>,               <&pclk_peri_pre>,
1428                                                 <&pclk_peri_pre>,               <&pclk_peri_pre>,
1429
1430                                                 <&dummy>,               <&dummy>,
1431                                                 <&dummy>,               <&dummy>;
1432
1433                                         clock-output-names =
1434                                                 "g_pclk_uart0",         "g_pclk_uart1",
1435                                                 "g_pclk_uart2",         "reserved",
1436
1437                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
1438                                                 "g_pclk_i2c2",          "reserved",
1439
1440                                                 "reserved",             "g_pclk_gpio0",
1441                                                 "g_pclk_gpio1",         "g_pclk_gpio2",
1442
1443                                                 "reserved",             "reserved",
1444                                                 "reserved",             "reserved";
1445
1446                                         rockchip,suspend-clkgating-setting=<0xf38c 0xf38c>;
1447                                         #clock-cells = <1>;
1448                                 };
1449
1450                                 clk_gates9: gate-clk@00f4 {
1451                                         compatible = "rockchip,rk3188-gate-clk";
1452                                         reg = <0x00f4 0x4>;
1453                                         clocks =
1454                                                 <&dummy>,               <&dummy>,
1455                                                 <&dummy>,               <&dummy>,
1456
1457                                                 <&dummy>,               <&hclk_vio_pre>,
1458                                                 <&aclk_vio_pre>,                <&dummy>,
1459
1460                                                 <&dummy>,               <&dummy>,
1461                                                 <&dummy>,               <&dummy>,
1462
1463                                                 <&dummy>,               <&hclk_peri_pre>,
1464                                                 <&hclk_peri_pre>,               <&aclk_peri_pre>;
1465
1466                                         clock-output-names =
1467                                                 "reserved",             "reserved",
1468                                                 "reserved",             "reserved",
1469
1470                                                 "reserved",             "g_hclk_lcdc",
1471                                                 "g_aclk_lcdc",          "reserved",
1472
1473                                                 "reserved",             "reserved",
1474                                                 "reserved",             "reserved",
1475
1476                                                 "reserved",             "g_hclk_usb_peri",
1477                                                 "g_hclk_pe_arbi",               "g_aclk_peri_niu";
1478
1479                                         rockchip,suspend-clkgating-setting=<0xdf9f 0xdf9f>;
1480
1481                                         #clock-cells = <1>;
1482                                 };
1483
1484                                 clk_gates10: gate-clk@00f8 {
1485                                         compatible = "rockchip,rk3188-gate-clk";
1486                                         reg = <0x00f8 0x4>;
1487                                         clocks =
1488                                                 <&xin24m>,              <&xin24m>,
1489                                                 <&xin24m>,              <&dummy>,
1490
1491                                                 <&clk_nandc>,           <&clk_sfc>,
1492                                                 <&clk_hevc_core>,               <&dummy>,
1493
1494                                                 <&clk_dpll>,            <&dummy>,
1495                                                 <&dummy>,               <&dummy>,
1496
1497                                                 <&dummy>,               <&dummy>,
1498                                                 <&dummy>,               <&dummy>;
1499
1500                                         clock-output-names =
1501                                                 "g_clk_pvtm_core",              "g_clk_pvtm_gpu",
1502                                                 "g_pvtm_video",         "reserved",
1503
1504                                                 "clk_nandc",            "clk_sfc",
1505                                                 "clk_hevc_core",                "reserved",
1506
1507                                                 "reserved",             "reserved",
1508                                                 "reserved",             "reserved",
1509
1510                                                 "reserved",             "reserved",
1511                                                 "reserved",             "reserved";
1512
1513                                         rockchip,suspend-clkgating-setting = <0x0077 0x0077>;   /* pwm logic vol */
1514
1515                                         #clock-cells = <1>;
1516                                 };
1517
1518                         };
1519                 };
1520         };
1521 };