1 Rockchip SoC USB controller
3 The USB devices interface with USB controllers on Rockchip SOCs.
4 The device node has following properties.
8 - compatible : Should be "rockchip,rk3188_usb20_otg" or
9 "rockchip,rk3288_usb20_otg" and so on, depending upon the SoC.
10 - reg : Physical base address of the controller and
11 length of memory mapped region.
12 - interrupts : interrupt number to the cpu.
13 - clocks : Clock IDs array as required by the controller.
14 - clock-names : Names of clock correseponding IDs clock
15 property as requested by the controller driver.
16 - rockchip,usb-mode : This signifies the otg controller mode.
17 "0" represents that otg supports both host and slave mode,
18 "1" represents that force otg to host only mode,
19 "2" represents that force otg to device only mode.
22 - rockchip,usb-pmic-vbus: If present, OTG VBUS 5V is supplied
29 compatible = "rockchip,rk3288_usb20_otg";
30 reg = <0xff580000 0x40000>;
31 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
33 clock-names = "clk_usbphy0", "hclk_usb0";
34 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
35 rockchip,usb-mode = <0>;
40 - compatible : Should be "rockchip,rk3188_usb20_host" or
41 "rockchip,rk3288_usb20_host" and so on, depending upon the SoC.
42 - reg : Physical base address of the controller and
43 length of memory mapped region.
44 - interrupts : Interrupt number to the cpu.
45 - clocks : Clock IDs array as required by the controller.
46 - clock-names : Names of clock correseponding IDs clock
47 property as requested by the controller driver.
53 compatible = "rockchip,rk3288_usb20_host";
54 reg = <0xff540000 0x40000>;
55 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
58 clock-names = "clk_usbphy1", "hclk_usb1",
64 - compatible : Should be "rockchip,rk3188_rk_ehci_host" or
65 "rockchip,rk3288_rk_ehci_host" and so on, for USB 2.0 EHCI
66 controller in host mode, depending upon the SoC.
67 - reg : Physical base address of the controller and
68 length of memory mapped region.
69 - interrupts : Interrupt number to the cpu.
70 - clocks : Clock IDs array as required by the controller.
71 - clock-names : Names of clock correseponding IDs clock
72 property as requested by the controller driver.
78 compatible = "rockchip,rk3288_rk_ehci_host";
79 reg = <0xff500000 0x20000>;
80 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
82 clock-names = "clk_usbphy2", "hclk_usb2";
87 - compatible : Should be "rockchip,rk3188_rk_ohci_host" or
88 "rockchip,rk3288_rk_ohci_host" and so on, for USB 2.0 OHCI
89 companion controller in host mode, depending upon the SoC.
90 - reg : Physical base address of the controller and
91 length of memory mapped region.
92 - interrupts : Interrupt number to the cpu.
93 - clocks : Clock IDs array as required by the controller.
94 - clock-names : Names of clock correseponding IDs clock
95 property as requested by the controller driver.
101 compatible = "rockchip,rk3288_rk_ohci_host";
102 reg = <0xff520000 0x20000>;
103 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
105 clock-names = "clk_usbphy3", "hclk_usb3";
111 - compatible : Should be "rockchip,rk3188_rk_ehci_host" or
112 "rockchip,rk3288_rk_ehci1_host" and so on, depending upon
114 - reg : Physical base address of the controller and
115 length of memory mapped region.
116 - interrupts : Interrupt number to the cpu.
117 - clocks : Clock IDs array as required by the controller.
118 - clock-names : Names of clock correseponding IDs clock
119 property as requested by the controller driver.
125 compatible = "rockchip,rk3288_rk_ehci1_host";
126 reg = <0xff5c0000 0x40000>;
127 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
129 <&ehci1phy_12m>, <&usbphy_480m>,
130 <&otgphy1_480m>, <&otgphy2_480m>;
131 clock-names = "ehci1phy_480m", "hclk_ehci1",
132 "ehci1phy_12m", "usbphy_480m",
133 "ehci1_usbphy1", "ehci1_usbphy2";
136 ROCKCHIP USB-PHY CONTROL
138 - compatible : Should be "rockchip,rk3188-dwc-control-usb"
139 or "rockchip,rk3288-dwc-control-usb" and so on, depending
141 - reg : Physical base address of USB-PHY GRF registers.
142 It contains the address of "GRF_SOC_STATUSX" and
143 "GRF_UOCX_BASE" depending upon the number of usb controllers
145 - reg-names : The names of the register addresses corresponding
146 to the registers filled in "reg".
147 - interrupts : Interrupt number to the cpu.
148 - interrupt-names : The names of the interrupts corresponding
149 to the registers filled in "interrupts".
150 - clocks : Clock IDs array as required by the controller.
151 - clock-names : Names of clock correseponding IDs clock
152 property as requested by the controller driver.
155 The child node 'usb_bc' to the node 'dwc_control_usb' is for
156 USB Battery Charging detect. It is used to differentiate the
157 Charging Port(i.e. CDP, DCP or SDP).
159 - compatible : Should be "synopsys,phy", "inno,phy" or
160 "rockchip,ctrl" depending upon the vendor of usb phy
164 The following properties represent the control and status
165 registers of usb otg battery charging. All these properties
166 are of type <u32>. Each property contains three tuples.
167 The layout of each tuple is:
169 offset, start bit, and bitmask.
185 The child node 'usb_uart' to the node 'dwc_control_usb' is for
186 the usb uart debug function.
188 - status : If be "ok" or "okay" will enable the usb-uart debug
189 function and bypass UART2 to USB OTG io port.
194 dwc_control_usb: dwc-control-usb@ff770284 {
195 compatible = "rockchip,rk3288-dwc-control-usb";
196 reg = <0xff770284 0x04>, <0xff770288 0x04>,
197 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
198 <0xff770320 0x14>, <0xff770334 0x14>,
199 <0xff770348 0x10>, <0xff770358 0x08>,
201 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
202 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
203 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
204 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
206 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-names = "otg_id",
216 clocks = <&clk_gates7 9>, <&usbphy_480m>,
217 <&otgphy1_480m>, <&otgphy2_480m>;
218 clock-names = "hclk_usb_peri", "usbphy_480m",
219 "usbphy1_480m", "usbphy2_480m";
222 compatible = "synopsys,phy";
223 /* offset bit mask */
224 rk_usb,bvalid = <0x288 14 1>;
225 rk_usb,dcdenb = <0x328 14 1>;
226 rk_usb,vdatsrcenb = <0x328 7 1>;
227 rk_usb,vdatdetenb = <0x328 6 1>;
228 rk_usb,chrgsel = <0x328 5 1>;
229 rk_usb,chgdet = <0x2cc 23 1>;
230 rk_usb,fsvminus = <0x2cc 25 1>;
231 rk_usb,fsvplus = <0x2cc 24 1>;
238 ROCKCHIP USB-COMMON CONTROL
240 - compatible : Should be "rockchip,rk3188-usb-control" or
241 "rockchip,rk3288-usb-control" and so on, depending upon
245 - host_drv_gpio : If present, specifies the GPIO that needs
246 to be pulled up for the host bus to be powered.
247 - otg_drv_gpio : If present, specifies the GPIO that needs
248 to be pulled up for the otg bus to be powered.
249 - rockchip,remote_wakeup : If present, host can be resumed
250 from suspend state by remote wakeup signal.
251 - rockchip,usb_irq_wakeup : If present, supports usb irqs to
252 wake up the system. The usb irqs are described in ROCKCHIP
253 USB-PHY CONTROL node, which include: "otg_id","otg_bvalid",
254 "linestate" and so on.
260 compatible = "rockchip,rk3288-usb-control";
262 host_drv_gpio = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>;
263 otg_drv_gpio = <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;
265 rockchip,remote_wakeup;
266 rockchip,usb_irq_wakeup;