Makefile: build dependencies in .*.o.d files

My previous attempts at fixing dependency generation actually cause
full recompilation every time a file is changed. Apparently, it'll work
best if each target object has its own dependency file. i.e., target
'model.o' has a corresponding '.model.o.d' which holds its dependency
information.

diff --git a/.gitignore b/.gitignore
index 78006ce2b7ae315957e475b507ba1a5e5693787c..d7ca89a59497416520a82aeecc1a99a0ce05a2a1 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -5,9 +5,9 @@
 *.so
 *~
 *.dot
+.*.d
 
 # files in this directory
 /tags
 /doc/docs
-/make.deps
 /benchmarks

diff --git a/Makefile b/Makefile
index 9b20f4c8a65632c7d0f1c25e18417b38724c9ff2..1cc4f4baa9cb1054f34b5ba2497bb32c175aa87f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -17,20 +17,8 @@ endif
 
 TESTS_DIR = test
 
-program_H_SRCS := $(wildcard *.h) $(wildcard include/*.h)
-program_C_SRCS := $(wildcard *.c) $(wildcard *.cc)
-DEPS = make.deps
-
 all: $(LIB_SO) tests
 
-$(DEPS): build_deps := 1
-$(DEPS): $(program_C_SRCS) $(program_H_SRCS)
-       $(CXX) -MM $(program_C_SRCS) $(CPPFLAGS) > $(DEPS)
-
-ifeq ($(build_deps),1)
-include $(DEPS)
-endif
-
 debug: CPPFLAGS += -DCONFIG_DEBUG
 debug: all
 
@@ -44,12 +32,14 @@ $(LIB_SO): $(OBJECTS)
 malloc.o: malloc.c
        $(CC) -fPIC -c malloc.c -DMSPACES -DONLY_MSPACES -DHAVE_MMAP=0 $(CPPFLAGS) -Wno-unused-variable
 
-%.o: %.cc $(DEPS)
-       $(CXX) -fPIC -c $< $(CPPFLAGS)
+%.o: %.cc
+       $(CXX) -MMD -MF .$@.d -fPIC -c $< $(CPPFLAGS)
+
+-include $(OBJECTS:%=.%.d)
 
 PHONY += clean
 clean:
-       rm -f *.o *.so
+       rm -f *.o *.so .*.d
        $(MAKE) -C $(TESTS_DIR) clean
 
 PHONY += mrclean