If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers...
[oota-llvm.git] / test / CodeGen /
drwxr-xr-x   ..
drwxr-xr-x - ARM
drwxr-xr-x - Alpha
drwxr-xr-x - CBackend
drwxr-xr-x - CPP
drwxr-xr-x - CellSPU
drwxr-xr-x - Generic
drwxr-xr-x - IA64
drwxr-xr-x - Mips
drwxr-xr-x - PowerPC
drwxr-xr-x - SPARC
drwxr-xr-x - X86