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drm/i915: Remove duplicated psr.active unset
2015-03-26 Rodrigo Vividrm/i915: Remove duplicated psr.active unset
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-03-26 Rodrigo Vividrm/i915: kill i915.powersave
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-03-20 Rodrigo Vividrm/i915: Fix sink crc connector iteration
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-03-17 Rodrigo Vividrm/i915: Make sure we invalidate frontbuffer on fbcon.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-02-25 Rodrigo Vividrm/i915: Fix frontbuffer false positve.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-02-23 Rodrigo Vividrm/i915/bdw: PCI IDs ending in 0xb are ULT.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-26 Rodrigo Vividrm/i915: BDW Fix Halo PCI IDs marked as ULT.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-26 Rodrigo Vividrm/i915: Fix and clean BDW PCH identification
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-15 Rodrigo Vividrm/i915: PSR link standby at debugfs
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-15 Rodrigo Vividrm/i915: group link_standby setup and let this info...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-15 Rodrigo Vividrm/i915: Add missing vbt check.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-15 Rodrigo Vividrm/i915: PSR HSW/BDW: Fix inverted logic at sink main_link_...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-15 Rodrigo Vividrm/i915: PSR VLV/CHV: Remove condition checks that...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-15 Rodrigo Vividrm/i915: VLV/CHV PSR needs to exit PSR on every flush.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-12 Rodrigo ViviRevert "drm/i915/chv: Use timeout mode for RC6 on chv"
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2015-01-07 Rodrigo ViviRevert "drm/i915: Parsing LFP brightness control from...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-17 Rodrigo Vividrm/i915: Organize bind_vma funcs
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-17 Rodrigo Vividrm/i915: Organize INSTDONE report for future.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-17 Rodrigo Vividrm/i915: Organize PDP regs report for future.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-17 Rodrigo Vividrm/i915: Organize PPGTT init
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-17 Rodrigo Vividrm/i915: Organize Fence registers for future enablement.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-10 Rodrigo Vividrm/i915: Introduce FBC DocBook.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-10 Rodrigo Vividrm/i915: Move FBC stuff to intel_fbc.c
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: Enable PSR for Baytrail and Braswell.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: VLV/CHV PSR debugfs.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: VLV/CHV PSR Software timer mode
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: PSR VLV/CHV: Introduce setup, enable and...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: Add PSR registers for PSR VLV/CHV.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: Remove intel_psr_is_enabled function.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: remove PSR BDW single frame update.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: PSR get full link off x standby from VBT
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: HSW/BDW PSR Set idle_frames = VBT + 1
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-12-03 Rodrigo Vividrm/i915: Parse VBT PSR block.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-11-17 Rodrigo Vividrm/i915: Add PSR docbook
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-11-17 Rodrigo Vividrm/i915: Introduce intel_psr.c
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-11-17 Rodrigo Vividrm/i915: Make dp aux pack/unpack public outside intel_dp.c
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-11-06 Rodrigo Vividrm/i915: Disable caches for Global GTT.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-10-24 Rodrigo Vividrm/i915/chv: Use 16 and 32 for low and high drain...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-10-24 Rodrigo Vividrm/i915/bdw: Remove BDW preproduction W/As until C...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-10-24 Rodrigo Vividrm/i915: Do not export RC6p and RC6pp if they don...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-10-02 Rodrigo Vividrm/i915: make sink_crc return -EIO on aux read/write...
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-30 Rodrigo Vividrm/i915: preserve other DP_TEST_SINK bits.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-30 Rodrigo Vividrm/i915/bdw: WaDisableFenceDestinationToSLM
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-30 Rodrigo Vividrm/i915: Add IS_BDW_GT3 macro.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-30 Rodrigo Vividrm/i915: Fix Sink CRC
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-29 Rodrigo Vividrm/i915: Broadwell DDI Buffer translation - more tuning
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-29 Rodrigo Vividrm/i915: Broadwell DDI Buffer translation changed...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-29 Rodrigo Vividrm/i915: Make sure PSR is ready for been re-enabled.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-29 Rodrigo Vividrm/i915: Minimize the huge amount of unecessary fbc...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-24 Rodrigo Vividrm/i915: Avoid re-configure panel on every PSR re...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-24 Rodrigo Vividrm/i915: PSR: Organize PSR enable function
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-24 Rodrigo Vividrm/i915: PSR: organize setup function.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-19 Rodrigo Vividrm/i915: Avoid reading fbc registers in vain when...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-19 Rodrigo Vividrm/i915: Only flush fbc on sw when fbc is enabled.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-19 Rodrigo Vividrm/i915: Use EIO instead of EAGAIN for sink CRC error.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-09-03 Rodrigo Vividrm/i915: FBC flush nuke for BDW
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-08-08 Rodrigo Vividrm/i915: Introduce FBC False Color for debug purposes.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-08-08 Rodrigo ViviRevert "drm/i915: Enable semaphores on BDW"
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-08-07 Rodrigo Vividrm/i915: Fix DEIER and GTIER collecting for BDW.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-08-07 Rodrigo Vividrm/i915: Collect gtier properly on HSW.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-08-07 Rodrigo Vividrm/i915: Fix error state collecting
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-07-23 Rodrigo Vividrm/i915: Fix possible overflow when recording semaphore...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-07-23 Rodrigo Vividrm/i915: Enable PSR by default.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-07-07 Rodrigo Vividrm/i915: Enable semaphores on BDW
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-07-07 Rodrigo Vividrm/i915: Implement MI decode for gen8
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-07-07 Rodrigo Vividrm/i915: Updating comments.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-07-07 Rodrigo Vividrm/i915: Fix VCS2's ring name.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-07-07 Rodrigo Vividrm/i915: Don't pretend ips is always enabled on BDW.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-24 Rodrigo Vividrm/i915: BDW: Adding Reserved PCI IDs.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: Improve PSR debugfs status.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: Force PSR exit by inactivating it.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: PSR HSW: update after enabling sprite.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: BDW PSR: Remove DDIA limitation for Broadwell.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: BDW PSR: Remove limitations that aren't valid...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: BDW PSR: Add single frame update support.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: Do not try to enable PSR when Panel doesn...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: Don't let update_psr function actually enable...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: Use HAS_PSR to avoid unecessary interactions.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-13 Rodrigo Vividrm/i915: Fix VLV CRC reading.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2014-06-11 Rodrigo Vividrm/i915: move psr_setup_done to psr struct
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2014-06-05 Rodrigo Vividrm/i915: BDW: Adding missing cursor offsets.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2014-01-27 Rodrigo Vividrm/i915: debugfs: Add support for probing DP sink...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2014-01-27 Rodrigo Vividrm: dp helper: Add DP test sink CRC definition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-10-03 Rodrigo Vividrm/i915: Simplify PSR debugfs
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-10-03 Rodrigo Vividrm/i915: Mask LPSP to get PSR working even with Power...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-09-04 Rodrigo Vividrm/i915: Report enabled slices on Haswell GT3
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-07-18 Rodrigo Vividrm/i915: Hook PSR functionality
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-07-18 Rodrigo Vividrm/i915: add update function to disable/enable-back PSR
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-07-18 Rodrigo Vividrm/intel: add enable_psr module option and disable...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-07-18 Rodrigo Vividrm/i915: Match all PSR mode entry conditions before...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-07-18 Rodrigo Vividrm/i915: Added debugfs support for PSR Status
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-07-18 Rodrigo Vividrm/i915: Enable/Disable PSR
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-07-18 Rodrigo Vividrm/i915: split aux_clock_divider logic in a separated...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-06-07 Rodrigo Vividrm/i915: WA: FBC Render Nuke.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-05-21 Rodrigo Vividrm/i915: Adding more reserved PCI IDs for Haswell.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-05-10 Rodrigo Vividrm/i915: HSW FBC WaFbcDisableDpfcClockGating
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-05-10 Rodrigo Vividrm/i915: HSW FBC WaFbcAsynchFlipDisableFbcQueue
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-05-10 Rodrigo Vividrm/i915: Enable FBC at Haswell.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-05-10 Rodrigo Vividrm/i915: IVB FBC WaFbcDisableDpfcClockGating
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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2013-05-10 Rodrigo Vividrm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
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