From ffc0b2663e4beaea1b584db607efd60660f5a74e Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 7 Sep 2006 20:33:45 +0000 Subject: [PATCH] Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns using test, which provides nice simplifications like: - movl %edi, %ecx - andl $2, %ecx - cmpl $0, %ecx + testl $2, %edi je LBB1_11 #cond_next90 There are a couple of dagiselemitter deficiencies that this exposes, they will be handled later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30156 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 14 ++++++--- lib/Target/X86/X86InstrInfo.td | 50 ++++++++++++++++-------------- 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 4f1feb1c615..1fc003d6447 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -2836,8 +2836,11 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt); } - SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag, - ShAmt, DAG.getConstant(32, MVT::i8)); + SDOperand InFlag = + DAG.getNode(X86ISD::CMP, MVT::Flag, + DAG.getNode(ISD::AND, MVT::i8, + ShAmt, DAG.getConstant(32, MVT::i8)), + DAG.getConstant(0, MVT::i8)); SDOperand Hi, Lo; SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); @@ -3134,7 +3137,8 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) { if (addTest) { CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); - Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0); + Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Op0, + DAG.getConstant(0, MVT::i8)); } std::vector Tys; @@ -3190,7 +3194,8 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) { if (addTest) { CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8); - Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond); + Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Cond, + DAG.getConstant(0, MVT::i8)); } return DAG.getNode(X86ISD::BRCOND, Op.getValueType(), Op.getOperand(0), Op.getOperand(2), CC, Cond); @@ -3774,7 +3779,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; case X86ISD::CMP: return "X86ISD::CMP"; - case X86ISD::TEST: return "X86ISD::TEST"; case X86ISD::COMI: return "X86ISD::COMI"; case X86ISD::UCOMI: return "X86ISD::UCOMI"; case X86ISD::SETCC: return "X86ISD::SETCC"; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 77944ba6d70..206faa129c0 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -52,8 +52,6 @@ def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, [SDNPOutFlag]>; -def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, - [SDNPOutFlag]>; def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, [SDNPInFlag, SDNPOutFlag]>; @@ -2073,60 +2071,54 @@ def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2), "test{b} {$src2, $src1|$src1, $src2}", - [(X86test GR8:$src1, GR8:$src2)]>; + [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>; def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2), "test{w} {$src2, $src1|$src1, $src2}", - [(X86test GR16:$src1, GR16:$src2)]>, OpSize; + [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize; def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2), "test{l} {$src2, $src1|$src1, $src2}", - [(X86test GR32:$src1, GR32:$src2)]>; + [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>; } -def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, GR8 :$src2), - "test{b} {$src2, $src1|$src1, $src2}", - [(X86test (loadi8 addr:$src1), GR8:$src2)]>; -def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, GR16:$src2), - "test{w} {$src2, $src1|$src1, $src2}", - [(X86test (loadi16 addr:$src1), GR16:$src2)]>, - OpSize; -def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, GR32:$src2), - "test{l} {$src2, $src1|$src1, $src2}", - [(X86test (loadi32 addr:$src1), GR32:$src2)]>; +// FIXME: These patterns are disabled until isel issue surrounding +//CodeGen/X86/test-load-fold.ll is fixed. def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2), "test{b} {$src2, $src1|$src1, $src2}", - [(X86test GR8:$src1, (loadi8 addr:$src2))]>; + [/*(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)*/]>; def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2), "test{w} {$src2, $src1|$src1, $src2}", - [(X86test GR16:$src1, (loadi16 addr:$src2))]>, + [/*(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)*/]>, OpSize; def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2), "test{l} {$src2, $src1|$src1, $src2}", - [(X86test GR32:$src1, (loadi32 addr:$src2))]>; + [/*(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)*/]>; def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8 (ops GR8:$src1, i8imm:$src2), "test{b} {$src2, $src1|$src1, $src2}", - [(X86test GR8:$src1, imm:$src2)]>; + [(X86cmp (and GR8:$src1, imm:$src2), 0)]>; def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16 (ops GR16:$src1, i16imm:$src2), "test{w} {$src2, $src1|$src1, $src2}", - [(X86test GR16:$src1, imm:$src2)]>, OpSize; + [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize; def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32 (ops GR32:$src1, i32imm:$src2), "test{l} {$src2, $src1|$src1, $src2}", - [(X86test GR32:$src1, imm:$src2)]>; + [(X86cmp (and GR32:$src1, imm:$src2), 0)]>; +// FIXME: These patterns are disabled until isel issue surrounding +//CodeGen/X86/test-load-fold.ll is fixed. def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 (ops i8mem:$src1, i8imm:$src2), "test{b} {$src2, $src1|$src1, $src2}", - [(X86test (loadi8 addr:$src1), imm:$src2)]>; + [/*(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)*/]>; def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 (ops i16mem:$src1, i16imm:$src2), "test{w} {$src2, $src1|$src1, $src2}", - [(X86test (loadi16 addr:$src1), imm:$src2)]>, + [/*(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)*/]>, OpSize; def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 (ops i32mem:$src1, i32imm:$src2), "test{l} {$src2, $src1|$src1, $src2}", - [(X86test (loadi32 addr:$src1), imm:$src2)]>; + [/*(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)*/]>; // Condition code ops, incl. set if equal/not equal/... @@ -2523,6 +2515,16 @@ def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1), def : Pat<(truncstore GR8:$src, addr:$dst, i1), (MOV8mr addr:$dst, GR8:$src)>; +// Comparisons. + +// TEST R,R is smaller than CMP R,0 +def : Pat<(X86cmp GR8:$src1, 0), + (TEST8rr GR8:$src1, GR8:$src1)>; +def : Pat<(X86cmp GR16:$src1, 0), + (TEST16rr GR16:$src1, GR16:$src1)>; +def : Pat<(X86cmp GR32:$src1, 0), + (TEST32rr GR32:$src1, GR32:$src1)>; + // {s|z}extload bool -> {s|z}extload byte def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>; def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>; -- 2.34.1