From fea997aac5773e936754de5436029c2a4fa1e930 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 1 Feb 2007 04:55:59 +0000 Subject: [PATCH] Fit in 80 columns git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33745 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 8 ++++---- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 12 +++++++----- lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp | 4 ++-- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 ++++-- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- 6 files changed, 19 insertions(+), 15 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index d9152573d3b..bb997609a7c 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1516,7 +1516,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp2 = LegalizeOp(Load.getValue(1)); break; } - assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!"); + assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); // Turn the unsupported load into an EXTLOAD followed by an explicit // zero/sign extend inreg. Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), @@ -1649,7 +1649,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // type should be returned by reference! SDOperand Lo, Hi; SplitVectorOp(Tmp2, Lo, Hi); - Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3); + Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); Result = LegalizeOp(Result); } } @@ -4689,7 +4689,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) { - Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset()); + Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset()); if (VT == MVT::f32 || VT == MVT::f64) { // f32->i32 or f64->i64 one to one expansion. // Remember that we legalized the chain. @@ -4705,7 +4705,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, getIntPtrConstant(IncrementSize)); // FIXME: This creates a bogus srcvalue! - Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset()); + Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset()); // Build a factor node to remember that this load is independent of the // other one. diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 7eabc84dcc2..2d1e6a3df92 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -696,7 +696,8 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number. /// Smaller number is the higher priority. template -unsigned BURegReductionPriorityQueue::CalcNodeSethiUllmanNumber(const SUnit *SU) { +unsigned BURegReductionPriorityQueue:: +CalcNodeSethiUllmanNumber(const SUnit *SU) { unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; if (SethiUllmanNumber != 0) return SethiUllmanNumber; @@ -805,7 +806,8 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number. /// Smaller number is the higher priority. template -unsigned TDRegReductionPriorityQueue::CalcNodeSethiUllmanNumber(const SUnit *SU) { +unsigned TDRegReductionPriorityQueue:: +CalcNodeSethiUllmanNumber(const SUnit *SU) { unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; if (SethiUllmanNumber != 0) return SethiUllmanNumber; @@ -816,8 +818,8 @@ unsigned TDRegReductionPriorityQueue::CalcNodeSethiUllmanNumber(const SUnit else if (SU->NumSuccsLeft == 0) // If SU does not have a use, i.e. it doesn't produce a value that would // be consumed (e.g. store), then it terminates a chain of computation. - // Give it a small SethiUllman number so it will be scheduled right before its - // predecessors that it doesn't lengthen their live ranges. + // Give it a small SethiUllman number so it will be scheduled right before + // its predecessors that it doesn't lengthen their live ranges. SethiUllmanNumber = 0; else if (SU->NumPredsLeft == 0 && (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU))) @@ -868,6 +870,6 @@ llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, MachineBasicBlock *BB) { return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, - new TDRegReductionPriorityQueue()); + new TDRegReductionPriorityQueue()); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp index d5b8d047739..442b8ef46a5 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp @@ -277,7 +277,7 @@ public: /// ResourceTally - Manages the use of resources over time intervals. Each /// item (slot) in the tally vector represents the resources used at a given /// moment. A bit set to 1 indicates that a resource is in use, otherwise -/// available. An assumption is made that the tally is large enough to schedule +/// available. An assumption is made that the tally is large enough to schedule /// all current instructions (asserts otherwise.) /// template @@ -377,7 +377,7 @@ private: // Try at cursor, if successful return position. if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor; // Locate a better position - Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units); + Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units); } } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 8bed6f7a26f..24b49b246cc 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1577,7 +1577,8 @@ SDOperand SelectionDAG::getLoad(MVT::ValueType VT, } SDOperand SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT, - SDOperand Chain, SDOperand Ptr, const Value *SV, + SDOperand Chain, SDOperand Ptr, + const Value *SV, int SVOffset, MVT::ValueType EVT, bool isVolatile) { // If they are asking for an extending load from/to the same thing, return a @@ -2228,7 +2229,8 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2).Val; } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, - SDOperand Op1, SDOperand Op2, SDOperand Op3) { + SDOperand Op1, SDOperand Op2, + SDOperand Op3) { return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Op1, Op2, Op3).Val; } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index af63d369919..8ce26281a3d 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3216,7 +3216,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, // Figure out if there is a Packed type corresponding to this Vector // type. If so, convert to the packed type. - MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems); + MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),NumElems); if (TVT != MVT::Other && isTypeLegal(TVT)) { // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a // "N x PTyElementVT" MVT::Vector type. diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index e0e2662ae52..2ebce86a036 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -715,7 +715,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, // If none of the top bits are demanded, convert this into an any_extend. if (NewBits == 0) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), + return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(), Op.getOperand(0))); // Since some of the sign extended bits are demanded, we know that the sign -- 2.34.1