From fc047278c160cf15d99502d8170d431cfcfe8a5b Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Thu, 18 Jul 2013 21:43:42 +0000 Subject: [PATCH] R600/SI: Add support for v2f32 stores git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186614 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUISelLowering.cpp | 3 +++ lib/Target/R600/SIInstructions.td | 3 +++ test/CodeGen/R600/store.ll | 18 ++++++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index e2fd369f869..666e1580918 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -57,6 +57,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::STORE, MVT::f32, Promote); AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); + setOperationAction(ISD::STORE, MVT::v2f32, Promote); + AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); + setOperationAction(ISD::STORE, MVT::v4f32, Promote); AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 95e86d794ca..76b73de9fb4 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1484,6 +1484,9 @@ def : BitConvert ; def : BitConvert ; +def : BitConvert ; +def : BitConvert ; + /********** =================== **********/ /********** Src & Dst modifiers **********/ /********** =================== **********/ diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index f8c6f8414c0..d233c73b805 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -15,6 +15,24 @@ define void @store_f32(float addrspace(1)* %out, float %in) { ret void } +; vec2 floating-point stores +; EG-CHECK: @store_v2f32 +; EG-CHECK: RAT_WRITE_CACHELESS_32_eg +; EG-CHECK-NEXT: RAT_WRITE_CACHELESS_32_eg +; CM-CHECK: @store_v2f32 +; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD +; CM-CHECK-NEXT: EXPORT_RAT_INST_STORE_DWORD +; SI-CHECK: @store_v2f32 +; SI-CHECK: BUFFER_STORE_DWORDX2 + +define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) { +entry: + %0 = insertelement <2 x float> , float %a, i32 0 + %1 = insertelement <2 x float> %0, float %b, i32 0 + store <2 x float> %1, <2 x float> addrspace(1)* %out + ret void +} + ; The stores in this function are combined by the optimizer to create a ; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer ; should not try to split the 64-bit store back into 2 32-bit stores. -- 2.34.1