From fa0cf99585b02b4f2491e195213d9d6d6704ca8f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 19 Feb 2014 08:25:02 +0000 Subject: [PATCH] Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 50 +++++----- .../X86/MCTargetDesc/X86MCCodeEmitter.cpp | 41 ++++++-- lib/Target/X86/X86CodeEmitter.cpp | 42 +++++++-- lib/Target/X86/X86InstrFPStack.td | 74 +++++++-------- lib/Target/X86/X86InstrFormats.td | 80 ++++++---------- test/MC/X86/padlock.s | 52 ----------- utils/TableGen/X86RecognizableInstr.cpp | 93 +++++++++---------- 7 files changed, 207 insertions(+), 225 deletions(-) diff --git a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h index 9b0fcbcb9cc..003bb04be56 100644 --- a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -306,10 +306,16 @@ namespace X86II { MRM_CB = 40, MRM_D0 = 41, MRM_D1 = 42, MRM_D4 = 43, MRM_D5 = 44, MRM_D6 = 45, MRM_D8 = 46, MRM_D9 = 47, MRM_DA = 48, MRM_DB = 49, MRM_DC = 50, MRM_DD = 51, - MRM_DE = 52, MRM_DF = 53, MRM_E0 = 54, MRM_E8 = 55, - MRM_F0 = 56, MRM_F8 = 57, MRM_F9 = 58, + MRM_DE = 52, MRM_DF = 53, MRM_E0 = 54, MRM_E1 = 55, + MRM_E2 = 56, MRM_E3 = 57, MRM_E4 = 58, MRM_E5 = 59, + MRM_E8 = 60, MRM_E9 = 61, MRM_EA = 62, MRM_EB = 63, + MRM_EC = 64, MRM_ED = 65, MRM_EE = 66, MRM_F0 = 67, + MRM_F1 = 68, MRM_F2 = 69, MRM_F3 = 70, MRM_F4 = 71, + MRM_F5 = 72, MRM_F6 = 73, MRM_F7 = 74, MRM_F8 = 75, + MRM_F9 = 76, MRM_FA = 77, MRM_FB = 78, MRM_FC = 79, + MRM_FD = 80, MRM_FE = 81, MRM_FF = 82, - FormMask = 63, + FormMask = 127, //===------------------------------------------------------------------===// // Actual flags... @@ -318,7 +324,7 @@ namespace X86II { // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 // prefix in 16-bit mode. - OpSizeShift = 6, + OpSizeShift = 7, OpSizeMask = 0x3 << OpSizeShift, OpSize16 = 1, @@ -327,14 +333,15 @@ namespace X86II { // AsSize - Set if this instruction requires an operand size prefix (0x67), // which most often indicates that the instruction address 16 bit address // instead of 32 bit address (or 32 bit address in 64 bit mode). - AdSize = 1 << 8, + AdSizeShift = OpSizeShift + 2, + AdSize = 1 << AdSizeShift, //===------------------------------------------------------------------===// // OpPrefix - There are several prefix bytes that are used as opcode // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is // no prefix. // - OpPrefixShift = 9, + OpPrefixShift = AdSizeShift + 1, OpPrefixMask = 0x7 << OpPrefixShift, // PS, PD - Prefix code for packed single and double precision vector @@ -350,7 +357,7 @@ namespace X86II { // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. // OpMapShift = OpPrefixShift + 3, - OpMapMask = 0xf << OpMapShift, + OpMapMask = 0x7 << OpMapShift, // OB - OneByte - Set if this instruction has a one byte opcode. OB = 0 << OpMapShift, @@ -371,20 +378,13 @@ namespace X86II { // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. XOPA = 6 << OpMapShift, - // D8-DF - These escape opcodes are used by the floating point unit. These - // values must remain sequential. - D8 = 7 << OpMapShift, D9 = 8 << OpMapShift, - DA = 9 << OpMapShift, DB = 10 << OpMapShift, - DC = 11 << OpMapShift, DD = 12 << OpMapShift, - DE = 13 << OpMapShift, DF = 14 << OpMapShift, - //===------------------------------------------------------------------===// // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. // They are used to specify GPRs and SSE registers, 64-bit operand size, // etc. We only cares about REX.W and REX.R bits and only the former is // statically determined. // - REXShift = OpMapShift + 4, + REXShift = OpMapShift + 3, REX_W = 1 << REXShift, //===------------------------------------------------------------------===// @@ -695,12 +695,20 @@ namespace X86II { case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: - case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8: - case X86II::MRM_F9: case X86II::MRM_D0: case X86II::MRM_D1: - case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6: - case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: - case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: - case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: + case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4: + case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8: + case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB: + case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE: + case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1: + case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4: + case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9: + case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: + case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0: + case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3: + case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6: + case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9: + case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC: + case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF: return -1; } } diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 88345fbf052..a10cb8ddd58 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -1152,11 +1152,6 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, case X86II::TA: // 0F 3A EmitByte(0x0F, CurByte, OS); break; - case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: - case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: - EmitByte(0xD8+(((TSFlags & X86II::OpMapMask) - X86II::D8) >> - X86II::OpMapShift), CurByte, OS); - break; } switch (TSFlags & X86II::OpMapMask) { @@ -1455,8 +1450,16 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE: - case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E8: - case X86II::MRM_F0: case X86II::MRM_F8: case X86II::MRM_F9: + case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1: + case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4: + case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9: + case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: + case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0: + case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3: + case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6: + case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9: + case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC: + case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF: EmitByte(BaseOpcode, CurByte, OS); unsigned char MRM; @@ -1485,10 +1488,34 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, case X86II::MRM_DE: MRM = 0xDE; break; case X86II::MRM_DF: MRM = 0xDF; break; case X86II::MRM_E0: MRM = 0xE0; break; + case X86II::MRM_E1: MRM = 0xE1; break; + case X86II::MRM_E2: MRM = 0xE2; break; + case X86II::MRM_E3: MRM = 0xE3; break; + case X86II::MRM_E4: MRM = 0xE4; break; + case X86II::MRM_E5: MRM = 0xE5; break; case X86II::MRM_E8: MRM = 0xE8; break; + case X86II::MRM_E9: MRM = 0xE9; break; + case X86II::MRM_EA: MRM = 0xEA; break; + case X86II::MRM_EB: MRM = 0xEB; break; + case X86II::MRM_EC: MRM = 0xEC; break; + case X86II::MRM_ED: MRM = 0xED; break; + case X86II::MRM_EE: MRM = 0xEE; break; case X86II::MRM_F0: MRM = 0xF0; break; + case X86II::MRM_F1: MRM = 0xF1; break; + case X86II::MRM_F2: MRM = 0xF2; break; + case X86II::MRM_F3: MRM = 0xF3; break; + case X86II::MRM_F4: MRM = 0xF4; break; + case X86II::MRM_F5: MRM = 0xF5; break; + case X86II::MRM_F6: MRM = 0xF6; break; + case X86II::MRM_F7: MRM = 0xF7; break; case X86II::MRM_F8: MRM = 0xF8; break; case X86II::MRM_F9: MRM = 0xF9; break; + case X86II::MRM_FA: MRM = 0xFA; break; + case X86II::MRM_FB: MRM = 0xFB; break; + case X86II::MRM_FC: MRM = 0xFC; break; + case X86II::MRM_FD: MRM = 0xFD; break; + case X86II::MRM_FE: MRM = 0xFE; break; + case X86II::MRM_FF: MRM = 0xFF; break; } EmitByte(MRM, CurByte, OS); break; diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 64f984066b5..82ba5998791 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -684,12 +684,6 @@ void Emitter::emitOpcodePrefix(uint64_t TSFlags, case X86II::TA: // 0F 3A MCE.emitByte(0x0F); break; - case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: - case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: - MCE.emitByte(0xD8+ - (((Desc->TSFlags & X86II::OpMapMask)-X86II::D8) - >> X86II::OpMapShift)); - break; } switch (Desc->TSFlags & X86II::OpMapMask) { @@ -1378,8 +1372,16 @@ void Emitter::emitInstruction(MachineInstr &MI, case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE: - case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E8: - case X86II::MRM_F0: case X86II::MRM_F8: + case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1: + case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4: + case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9: + case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: + case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0: + case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3: + case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6: + case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9: + case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC: + case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF: MCE.emitByte(BaseOpcode); unsigned char MRM; @@ -1408,10 +1410,34 @@ void Emitter::emitInstruction(MachineInstr &MI, case X86II::MRM_DE: MRM = 0xDE; break; case X86II::MRM_DF: MRM = 0xDF; break; case X86II::MRM_E0: MRM = 0xE0; break; + case X86II::MRM_E1: MRM = 0xE1; break; + case X86II::MRM_E2: MRM = 0xE2; break; + case X86II::MRM_E3: MRM = 0xE3; break; + case X86II::MRM_E4: MRM = 0xE4; break; + case X86II::MRM_E5: MRM = 0xE5; break; case X86II::MRM_E8: MRM = 0xE8; break; + case X86II::MRM_E9: MRM = 0xE9; break; + case X86II::MRM_EA: MRM = 0xEA; break; + case X86II::MRM_EB: MRM = 0xEB; break; + case X86II::MRM_EC: MRM = 0xEC; break; + case X86II::MRM_ED: MRM = 0xED; break; + case X86II::MRM_EE: MRM = 0xEE; break; case X86II::MRM_F0: MRM = 0xF0; break; + case X86II::MRM_F1: MRM = 0xF1; break; + case X86II::MRM_F2: MRM = 0xF2; break; + case X86II::MRM_F3: MRM = 0xF3; break; + case X86II::MRM_F4: MRM = 0xF4; break; + case X86II::MRM_F5: MRM = 0xF5; break; + case X86II::MRM_F6: MRM = 0xF6; break; + case X86II::MRM_F7: MRM = 0xF7; break; case X86II::MRM_F8: MRM = 0xF8; break; case X86II::MRM_F9: MRM = 0xF9; break; + case X86II::MRM_FA: MRM = 0xFA; break; + case X86II::MRM_FB: MRM = 0xFB; break; + case X86II::MRM_FC: MRM = 0xFC; break; + case X86II::MRM_FD: MRM = 0xFD; break; + case X86II::MRM_FE: MRM = 0xFE; break; + case X86II::MRM_FF: MRM = 0xFF; break; } MCE.emitByte(MRM); break; diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 8e64daf4773..1ff818c5c38 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -251,29 +251,29 @@ def COM_FST0r : FPST0rInst ; def COMP_FST0r : FPST0rInst ; // Unary operations. -multiclass FPUnary opcode, string asmstring> { +multiclass FPUnary { def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, [(set RFP32:$dst, (OpNode RFP32:$src))]>; def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, [(set RFP64:$dst, (OpNode RFP64:$src))]>; def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, [(set RFP80:$dst, (OpNode RFP80:$src))]>; -def _F : FPI, D9; +def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; } let Defs = [FPSW] in { -defm CHS : FPUnary; -defm ABS : FPUnary; -defm SQRT: FPUnary; -defm SIN : FPUnary; -defm COS : FPUnary; +defm CHS : FPUnary; +defm ABS : FPUnary; +defm SQRT: FPUnary; +defm SIN : FPUnary; +defm COS : FPUnary; let neverHasSideEffects = 1 in { def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; } -def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9; +def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; } // Defs = [FPSW] // Versions of FP instructions that take a single memory operand. Added for the @@ -515,8 +515,8 @@ def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, } let SchedRW = [WriteZero] in { -def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz", IIC_FLDZ>, D9; -def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1", IIC_FIST>, D9; +def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz", IIC_FLDZ>; +def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1", IIC_FIST>; } // Floating point compares. @@ -546,8 +546,8 @@ def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) (outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>; def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop (outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>; -def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop - (outs), (ins), "fucompp", IIC_FUCOM>, DA; +def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop + (outs), (ins), "fucompp", IIC_FUCOM>; } let Defs = [EFLAGS, FPSW], Uses = [ST0] in { @@ -568,9 +568,9 @@ def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), // Floating point flag ops. let SchedRW = [WriteALU] in { let Defs = [AX], Uses = [FPSW] in -def FNSTSW16r : I<0xE0, RawFrm, // AX = fp flags +def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags (outs), (ins), "fnstsw\t{%ax|ax}", - [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>, DF; + [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>; def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world (outs), (ins i16mem:$dst), "fnstcw\t$dst", @@ -584,40 +584,40 @@ def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] // FPU control instructions let SchedRW = [WriteMicrocoded] in { let Defs = [FPSW] in -def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", [], IIC_FNINIT>, DB; +def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>; def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), "ffree\t$reg", IIC_FFREE>; // Clear exceptions let Defs = [FPSW] in -def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", [], IIC_FNCLEX>, DB; +def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; } // SchedRW // Operandless floating-point instructions for the disassembler. let SchedRW = [WriteMicrocoded] in { def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>; -def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", [], IIC_FNOP>, D9; -def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", [], IIC_FXAM>, D9; -def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", [], IIC_FLDL>, D9; -def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", [], IIC_FLDL>, D9; -def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", [], IIC_FLDL>, D9; -def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", [], IIC_FLDL>, D9; -def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", [], IIC_FLDL>, D9; -def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", [], IIC_F2XM1>, D9; -def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", [], IIC_FYL2X>, D9; -def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", [], IIC_FPTAN>, D9; -def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", [], IIC_FPATAN>, D9; -def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", [], IIC_FXTRACT>, D9; -def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", [], IIC_FPREM1>, D9; -def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", [], IIC_FPSTP>, D9; -def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", [], IIC_FPSTP>, D9; -def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", [], IIC_FPREM>, D9; -def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>, D9; -def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", [], IIC_FSINCOS>, D9; -def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", [], IIC_FRNDINT>, D9; -def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", [], IIC_FSCALE>, D9; -def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", [], IIC_FCOMPP>, DE; +def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>; +def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>; +def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>; +def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>; +def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>; +def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>; +def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>; +def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>; +def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>; +def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>; +def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>; +def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>; +def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>; +def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>; +def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>; +def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>; +def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>; +def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>; +def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>; +def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>; +def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>; def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), "fxsave\t$dst", [], IIC_FXSAVE>, TB; diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index bd210040f40..0f6533dcea5 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -14,8 +14,8 @@ // Format specifies the encoding used by the instruction. This is part of the // ad-hoc solution used to emit machine instruction encodings by our machine // code emitter. -class Format val> { - bits<6> Value = val; +class Format val> { + bits<7> Value = val; } def Pseudo : Format<0>; def RawFrm : Format<1>; @@ -33,33 +33,23 @@ def MRM6r : Format<22>; def MRM7r : Format<23>; def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; def MRM6m : Format<30>; def MRM7m : Format<31>; -def MRM_C0 : Format<32>; -def MRM_C1 : Format<33>; -def MRM_C2 : Format<34>; -def MRM_C3 : Format<35>; -def MRM_C4 : Format<36>; -def MRM_C8 : Format<37>; -def MRM_C9 : Format<38>; -def MRM_CA : Format<39>; -def MRM_CB : Format<40>; -def MRM_D0 : Format<41>; -def MRM_D1 : Format<42>; -def MRM_D4 : Format<43>; -def MRM_D5 : Format<44>; -def MRM_D6 : Format<45>; -def MRM_D8 : Format<46>; -def MRM_D9 : Format<47>; -def MRM_DA : Format<48>; -def MRM_DB : Format<49>; -def MRM_DC : Format<50>; -def MRM_DD : Format<51>; -def MRM_DE : Format<52>; -def MRM_DF : Format<53>; -def MRM_E0 : Format<54>; -def MRM_E8 : Format<55>; -def MRM_F0 : Format<56>; -def MRM_F8 : Format<57>; -def MRM_F9 : Format<58>; +def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>; +def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>; +def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>; +def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>; +def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>; +def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>; +def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>; +def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>; +def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>; +def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>; +def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>; +def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>; +def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>; +def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>; +def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>; +def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>; +def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>; // ImmType - This specifies the immediate type used by an instruction. This is // part of the ad-hoc solution used to emit machine instruction encodings by our @@ -126,8 +116,8 @@ def XS : Prefix<3>; def XD : Prefix<4>; // Class specifying the opcode map. -class Map val> { - bits<4> Value = val; +class Map val> { + bits<3> Value = val; } def OB : Map<0>; def TB : Map<1>; @@ -136,14 +126,6 @@ def TA : Map<3>; def XOP8 : Map<4>; def XOP9 : Map<5>; def XOPA : Map<6>; -def D8 : Map<7>; -def D9 : Map<8>; -def DA : Map<9>; -def DB : Map<10>; -def DC : Map<11>; -def DD : Map<12>; -def DE : Map<13>; -def DF : Map<14>; // Class specifying the encoding class Encoding val> { @@ -171,14 +153,6 @@ class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class REP { bit hasREPPrefix = 1; } class TB { Map OpMap = TB; } -class D8 { Map OpMap = D8; } -class D9 { Map OpMap = D9; } -class DA { Map OpMap = DA; } -class DB { Map OpMap = DB; } -class DC { Map OpMap = DC; } -class DD { Map OpMap = DD; } -class DE { Map OpMap = DE; } -class DF { Map OpMap = DF; } class T8 { Map OpMap = T8; } class TA { Map OpMap = TA; } class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } @@ -231,7 +205,7 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, bits<8> Opcode = opcod; Format Form = f; - bits<6> FormBits = Form.Value; + bits<7> FormBits = Form.Value; ImmType ImmT = i; dag OutOperandList = outs; @@ -281,11 +255,11 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. // TSFlags layout should be kept in sync with X86InstrInfo.h. - let TSFlags{5-0} = FormBits; - let TSFlags{7-6} = OpSize.Value; - let TSFlags{8} = hasAdSizePrefix; - let TSFlags{11-9} = OpPrefix.Value; - let TSFlags{15-12} = OpMap.Value; + let TSFlags{6-0} = FormBits; + let TSFlags{8-7} = OpSize.Value; + let TSFlags{9} = hasAdSizePrefix; + let TSFlags{12-10} = OpPrefix.Value; + let TSFlags{15-13} = OpMap.Value; let TSFlags{16} = hasREX_WPrefix; let TSFlags{20-17} = ImmT.Value; let TSFlags{23-21} = FPForm.Value; diff --git a/test/MC/X86/padlock.s b/test/MC/X86/padlock.s index 5c523e7f68c..698581759f5 100644 --- a/test/MC/X86/padlock.s +++ b/test/MC/X86/padlock.s @@ -3,55 +3,3 @@ xstore // CHECK: xstore // CHECK: encoding: [0x0f,0xa7,0xc0] - - xstorerng -// CHECK: xstore -// CHECK: encoding: [0x0f,0xa7,0xc0] - - rep xcryptecb -// CHECK: rep -// CHECK: encoding: [0xf3] -// CHECK: xcryptecb -// CHECK: encoding: [0x0f,0xa7,0xc8] - - rep xcryptcbc -// CHECK: rep -// CHECK: encoding: [0xf3] -// CHECK: xcryptcbc -// CHECK: encoding: [0x0f,0xa7,0xd0] - - rep xcryptctr -// CHECK: rep -// CHECK: encoding: [0xf3] -// CHECK: xcryptctr -// CHECK: encoding: [0x0f,0xa7,0xd8] - - rep xcryptcfb -// CHECK: rep -// CHECK: encoding: [0xf3] -// CHECK: xcryptcfb -// CHECK: encoding: [0x0f,0xa7,0xe0] - - rep xcryptofb -// CHECK: rep -// CHECK: encoding: [0xf3] -// CHECK: xcryptofb -// CHECK: encoding: [0x0f,0xa7,0xe8] - - rep xsha1 -// CHECK: rep -// CHECK: encoding: [0xf3] -// CHECK: xsha1 -// CHECK: encoding: [0x0f,0xa6,0xc8] - - rep xsha256 -// CHECK: rep -// CHECK: encoding: [0xf3] -// CHECK: xsha256 -// CHECK: encoding: [0x0f,0xa6,0xd0] - - rep montmul -// CHECK: rep -// CHECK: encoding: [0xf3] -// CHECK: montmul -// CHECK: encoding: [0x0f,0xa6,0xc0] diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 1a6af715f62..0ebdd592b13 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -46,10 +46,34 @@ using namespace llvm; MAP(DE, 52) \ MAP(DF, 53) \ MAP(E0, 54) \ - MAP(E8, 55) \ - MAP(F0, 56) \ - MAP(F8, 57) \ - MAP(F9, 58) + MAP(E1, 55) \ + MAP(E2, 56) \ + MAP(E3, 57) \ + MAP(E4, 58) \ + MAP(E5, 59) \ + MAP(E8, 60) \ + MAP(E9, 61) \ + MAP(EA, 62) \ + MAP(EB, 63) \ + MAP(EC, 64) \ + MAP(ED, 65) \ + MAP(EE, 66) \ + MAP(F0, 67) \ + MAP(F1, 68) \ + MAP(F2, 69) \ + MAP(F3, 70) \ + MAP(F4, 71) \ + MAP(F5, 72) \ + MAP(F6, 73) \ + MAP(F7, 74) \ + MAP(F8, 75) \ + MAP(F9, 76) \ + MAP(FA, 77) \ + MAP(FB, 78) \ + MAP(FC, 79) \ + MAP(FD, 80) \ + MAP(FE, 81) \ + MAP(FF, 82) // A clone of X86 since we can't depend on something that is generated. namespace X86Local { @@ -79,9 +103,7 @@ namespace X86Local { }; enum { - OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, - D8 = 7, D9 = 8, DA = 9, DB = 10, - DC = 11, DD = 12, DE = 13, DF = 14 + OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6 }; enum { @@ -732,32 +754,23 @@ void RecognizableInstr::emitInstructionSpecifier() { HANDLE_OPERAND(relocation) } break; - case X86Local::MRM_C0: - case X86Local::MRM_C1: - case X86Local::MRM_C2: - case X86Local::MRM_C3: - case X86Local::MRM_C4: - case X86Local::MRM_C8: - case X86Local::MRM_C9: - case X86Local::MRM_CA: - case X86Local::MRM_CB: - case X86Local::MRM_E8: - case X86Local::MRM_F0: - case X86Local::MRM_F9: - case X86Local::MRM_D0: - case X86Local::MRM_D1: - case X86Local::MRM_D4: - case X86Local::MRM_D5: - case X86Local::MRM_D6: - case X86Local::MRM_D8: - case X86Local::MRM_D9: - case X86Local::MRM_DA: - case X86Local::MRM_DB: - case X86Local::MRM_DC: - case X86Local::MRM_DD: - case X86Local::MRM_DE: - case X86Local::MRM_DF: - case X86Local::MRM_E0: + case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2: + case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8: + case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB: + case X86Local::MRM_D0: case X86Local::MRM_D1: case X86Local::MRM_D4: + case X86Local::MRM_D5: case X86Local::MRM_D6: case X86Local::MRM_D8: + case X86Local::MRM_D9: case X86Local::MRM_DA: case X86Local::MRM_DB: + case X86Local::MRM_DC: case X86Local::MRM_DD: case X86Local::MRM_DE: + case X86Local::MRM_DF: case X86Local::MRM_E0: case X86Local::MRM_E1: + case X86Local::MRM_E2: case X86Local::MRM_E3: case X86Local::MRM_E4: + case X86Local::MRM_E5: case X86Local::MRM_E8: case X86Local::MRM_E9: + case X86Local::MRM_EA: case X86Local::MRM_EB: case X86Local::MRM_EC: + case X86Local::MRM_ED: case X86Local::MRM_EE: case X86Local::MRM_F0: + case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3: + case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6: + case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA: + case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD: + case X86Local::MRM_FE: case X86Local::MRM_FF: // Ignored. break; } @@ -825,20 +838,6 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { opcodeToSet = Opcode; break; - case X86Local::D8: - case X86Local::D9: - case X86Local::DA: - case X86Local::DB: - case X86Local::DC: - case X86Local::DD: - case X86Local::DE: - case X86Local::DF: - assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode"); - assert(Form == X86Local::RawFrm); - opcodeType = ONEBYTE; - filter = new ExactFilter(Opcode); - opcodeToSet = 0xd8 + (OpMap - X86Local::D8); - break; } // switch (OpMap) assert(opcodeType != (OpcodeType)-1 && -- 2.34.1