From f9516208e57364ab1e7d8748af1f59a2ea5fb572 Mon Sep 17 00:00:00 2001 From: Duncan Sands Date: Mon, 30 Jun 2008 10:19:09 +0000 Subject: [PATCH] Revert the SelectionDAG optimization that makes it impossible to create a MERGE_VALUES node with only one result: sometimes it is useful to be able to create a node with only one result out of one of the results of a node with more than one result, for example because the new node will eventually be used to replace a one-result node using ReplaceAllUsesWith, cf X86TargetLowering::ExpandFP_TO_SINT. On the other hand, most users of MERGE_VALUES don't need this and for them the optimization was valuable. So add a new utility method getMergeValues for creating MERGE_VALUES nodes which by default performs the optimization. Change almost everywhere to use getMergeValues (and tidy some stuff up at the same time). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52893 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAG.h | 9 +++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 15 ++-- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 +- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 49 +++++------- lib/Target/ARM/ARMISelLowering.cpp | 9 +-- lib/Target/Alpha/AlphaISelLowering.cpp | 5 +- lib/Target/CellSPU/SPUISelLowering.cpp | 9 +-- lib/Target/Mips/MipsISelLowering.cpp | 8 +- lib/Target/PIC16/PIC16ISelLowering.cpp | 4 +- lib/Target/PowerPC/PPCISelLowering.cpp | 27 +++---- lib/Target/Sparc/SparcISelLowering.cpp | 12 +-- lib/Target/X86/X86ISelLowering.cpp | 79 +++++++------------ 12 files changed, 93 insertions(+), 136 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 8b3dad223a0..dee6bc746e7 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -379,6 +379,15 @@ public: SDOperand Val, const Value* PtrVal, unsigned Alignment = 0); + /// getMergeValues - Create a MERGE_VALUES node from the given types and ops. + /// Allowed to return something different (and simpler) if Simplify is true. + SDOperand getMergeValues(SDVTList VTs, SDOperandPtr Ops, unsigned NumOps, + bool Simplify = true) { + if (Simplify && NumOps == 1) + return Ops[0]; + return getNode(ISD::MERGE_VALUES, VTs, Ops, NumOps); + } + /// getLoad - Loads are not normal binary operators: their result type is not /// determined by their operands, and they produce a value AND a token chain. /// diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index c40a783da07..3d01bb2fa05 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -652,8 +652,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); SDOperand Ops[] = { Result, Chain }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), - Ops, 2); + return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); } assert(LoadedVT.isInteger() && !LoadedVT.isVector() && "Unaligned load of unsupported type."); @@ -702,7 +701,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, Hi.getValue(1)); SDOperand Ops[] = { Result, TF }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); + return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); } /// UnrollVectorOp - We know that the given vector has a legal type, however @@ -933,8 +932,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Fall Thru case TargetLowering::Legal: { SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; - Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), - Ops, 2); + Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); break; } } @@ -968,8 +966,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Fall Thru case TargetLowering::Legal: { SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; - Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), - Ops, 2); + Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); break; } } @@ -4737,10 +4734,10 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, default: assert(0 && "Unsupported FP setcc!"); } } - + SDOperand Dummy; Tmp1 = ExpandLibCall(LC1, - DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, + DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, false /*sign irrelevant*/, Dummy); Tmp2 = DAG.getConstant(0, MVT::i32); CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 023be5c6954..6456fa30e3f 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1983,8 +1983,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) { unsigned OpOpcode = Operand.Val->getOpcode(); switch (Opcode) { case ISD::TokenFactor: - case ISD::MERGE_VALUES: - return Operand; // Factor or merge of one node? No need. + return Operand; // Factor of one node? No need. case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node"); case ISD::FP_EXTEND: assert(VT.isFloatingPoint() && diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 0ab5b6237ca..e8537d2011d 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1165,9 +1165,8 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { ValueVTs.push_back(Val->getValueType(i)); } } - return DAG.getNode(ISD::MERGE_VALUES, - DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), + &Constants[0], Constants.size()); } if (const ArrayType *ATy = dyn_cast(C->getType())) { @@ -1187,9 +1186,8 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { else Constants[i] = DAG.getConstant(0, EltVT); } - return DAG.getNode(ISD::MERGE_VALUES, - DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), + &Constants[0], Constants.size()); } if (const StructType *STy = dyn_cast(C->getType())) { @@ -1210,9 +1208,8 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { else Constants[i] = DAG.getConstant(0, EltVT); } - return DAG.getNode(ISD::MERGE_VALUES, - DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), + &Constants[0], Constants.size()); } const VectorType *VecTy = cast(V->getType()); @@ -2722,9 +2719,8 @@ void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : SDOperand(Agg.Val, Agg.ResNo + i); - setValue(&I, DAG.getNode(ISD::MERGE_VALUES, - DAG.getVTList(&AggValueVTs[0], NumAggValues), - &Values[0], NumAggValues)); + setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues), + &Values[0], NumAggValues)); } void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { @@ -2749,9 +2745,8 @@ void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { OutOfUndef ? DAG.getNode(ISD::UNDEF, Agg.Val->getValueType(Agg.ResNo + i)) : SDOperand(Agg.Val, Agg.ResNo + i); - setValue(&I, DAG.getNode(ISD::MERGE_VALUES, - DAG.getVTList(&ValValueVTs[0], NumValValues), - &Values[0], NumValValues)); + setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues), + &Values[0], NumValValues)); } @@ -2906,9 +2901,8 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) { else PendingLoads.push_back(Chain); - setValue(&I, DAG.getNode(ISD::MERGE_VALUES, - DAG.getVTList(&ValueVTs[0], NumValues), - &Values[0], NumValues)); + setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues), + &Values[0], NumValues)); } @@ -3796,9 +3790,8 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, if (ValueVTs.size() == 1) return Values[0]; - return DAG.getNode(ISD::MERGE_VALUES, - DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Values[0], ValueVTs.size()); + return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), + &Values[0], ValueVTs.size()); } /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the @@ -4867,10 +4860,8 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, AssertOp); ReturnValues.push_back(ReturnValue); } - Res = ReturnValues.size() == 1 ? ReturnValues.front() : - DAG.getNode(ISD::MERGE_VALUES, - DAG.getVTList(&RetTys[0], RetTys.size()), - &ReturnValues[0], ReturnValues.size()); + Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()), + &ReturnValues[0], ReturnValues.size()); } return std::make_pair(Res, Chain); @@ -4972,10 +4963,10 @@ LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) { SmallVector LegalValueVTs(NumValues); for (unsigned VI = 0; VI != NumValues; ++VI) LegalValueVTs[VI] = Args[a + VI].getValueType(); - SDL.setValue(AI, SDL.DAG.getNode(ISD::MERGE_VALUES, - SDL.DAG.getVTList(&LegalValueVTs[0], - NumValues), - &Args[a], NumValues)); + SDL.setValue(AI, + SDL.DAG.getMergeValues(SDL.DAG.getVTList(&LegalValueVTs[0], + NumValues), + &Args[a], NumValues)); // If this argument is live outside of the entry block, insert a copy from // whereever we got it to the vreg that other BB's will reference it as. DenseMap::iterator VMI=FuncInfo.ValueMap.find(AI); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index cfb98cb21cc..2c11919b482 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -654,8 +654,8 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { return Chain; ResultVals.push_back(Chain); - SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], - ResultVals.size()); + SDOperand Res = DAG.getMergeValues(DAG.getVTList(&NodeTys[0], NodeTys.size()), + &ResultVals[0], ResultVals.size()); return Res.getValue(Op.ResNo); } @@ -1025,9 +1025,8 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { ArgValues.push_back(Root); // Return the new list of results. - std::vector RetVT(Op.Val->value_begin(), - Op.Val->value_end()); - return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); + return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], + ArgValues.size()); } /// isFloatingPointZero - Return true if this is +0.0. diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index dd001b4f168..ad50816d9c2 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -280,9 +280,8 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, ArgValues.push_back(Root); // Return the new list of results. - std::vector RetVT(Op.Val->value_begin(), - Op.Val->value_end()); - return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); + return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], + ArgValues.size()); } static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 41555c0753d..e99a8bdae70 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1060,9 +1060,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) ArgValues.push_back(Root); // Return the new list of results. - std::vector RetVT(Op.Val->value_begin(), - Op.Val->value_end()); - return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); + return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], + ArgValues.size()); } /// isLSAAddress - Return the immediate to use if the specified @@ -1301,8 +1300,8 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals[NumResults++] = Chain; - SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, - ResultVals, NumResults); + SDOperand Res = DAG.getMergeValues(DAG.getVTList(&NodeTys[0], NodeTys.size()), + ResultVals, NumResults); return Res.getValue(Op.ResNo); } diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 16464d1f706..3dfd33401e8 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -517,8 +517,8 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), - &ResultVals[0], ResultVals.size()).Val; + return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], + ResultVals.size()).Val; } //===----------------------------------------------------------------------===// @@ -649,8 +649,8 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) ArgValues.push_back(Root); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), - &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); + return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], + ArgValues.size()).getValue(Op.ResNo); } //===----------------------------------------------------------------------===// diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index deab5d56754..fa1698f37e7 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -542,8 +542,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) // FIXME: Just copy right now. ArgValues.push_back(Root); - return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), &ArgValues[0], - ArgValues.size()).getValue(Op.ResNo); + return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], + ArgValues.size()).getValue(Op.ResNo); } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 9432a749b81..918db9d5d2d 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1775,9 +1775,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, ArgValues.push_back(Root); // Return the new list of results. - std::vector RetVT(Op.Val->value_begin(), - Op.Val->value_end()); - return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); + return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], + ArgValues.size()); } /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus @@ -2557,8 +2556,8 @@ SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); - SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), - &ResultVals[0], ResultVals.size()); + SDOperand Res = DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0], + ResultVals.size()); return Res.getValue(Op.ResNo); } @@ -2753,8 +2752,7 @@ SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG }; SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); SDOperand OutOps[] = { Load, Store }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), - OutOps, 2); + return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); } SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2796,8 +2794,7 @@ SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG }; SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops3, 4); SDOperand OutOps[] = { Load, Store }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), - OutOps, 2); + return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); } SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2829,8 +2826,7 @@ SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) { }; SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); SDOperand OutOps[] = { Load, Store }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), - OutOps, 2); + return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); } /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when @@ -3134,8 +3130,7 @@ SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); SDOperand OutOps[] = { OutLo, OutHi }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), - OutOps, 2); + return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2); } SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { @@ -3163,8 +3158,7 @@ SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); SDOperand OutOps[] = { OutLo, OutHi }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), - OutOps, 2); + return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2); } SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { @@ -3192,8 +3186,7 @@ SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), Tmp4, Tmp6, ISD::SETLE); SDOperand OutOps[] = { OutLo, OutHi }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT), - OutOps, 2); + return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2); } //===----------------------------------------------------------------------===// diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 5c0617438c4..48b4fecbf79 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -450,8 +450,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { ResultVals.push_back(Chain); // Merge everything together with a MERGE_VALUES node. - return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), - &ResultVals[0], ResultVals.size()); + return DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0], + ResultVals.size()); } @@ -829,8 +829,7 @@ static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), V.getValue(1) }; - return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::f64, MVT::Other), - Ops, 2); + return DAG.getMergeValues(DAG.getVTList(MVT::f64, MVT::Other), Ops, 2); } static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) { @@ -846,11 +845,8 @@ static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) { // to provide a register spill area. SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, DAG.getConstant(96, MVT::i32)); - std::vector Tys; - Tys.push_back(MVT::i32); - Tys.push_back(MVT::Other); SDOperand Ops[2] = { NewVal, Chain }; - return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); + return DAG.getMergeValues(DAG.getVTList(MVT::i32, MVT::Other), Ops, 2); } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index bc7a4aec2ba..7173df69694 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -979,8 +979,8 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, // Merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); - return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), - &ResultVals[0], ResultVals.size()).Val; + return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], + ResultVals.size()).Val; } @@ -1377,8 +1377,8 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn); // Return the new list of results. - return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), - &ArgValues[0], ArgValues.size()).getValue(Op.ResNo); + return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0], + ArgValues.size()).getValue(Op.ResNo); } SDOperand @@ -4361,7 +4361,6 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt); } - const MVT *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag); SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt, DAG.getConstant(VTBits, MVT::i8)); SDOperand Cond = DAG.getNode(X86ISD::CMP, VT, @@ -4369,41 +4368,19 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { SDOperand Hi, Lo; SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8); - VTs = DAG.getNodeValueTypes(VT, MVT::Flag); - SmallVector Ops; - if (Op.getOpcode() == ISD::SHL_PARTS) { - Ops.push_back(Tmp2); - Ops.push_back(Tmp3); - Ops.push_back(CC); - Ops.push_back(Cond); - Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); + SDOperand Ops0[4] = { Tmp2, Tmp3, CC, Cond }; + SDOperand Ops1[4] = { Tmp3, Tmp1, CC, Cond }; - Ops.clear(); - Ops.push_back(Tmp3); - Ops.push_back(Tmp1); - Ops.push_back(CC); - Ops.push_back(Cond); - Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); + if (Op.getOpcode() == ISD::SHL_PARTS) { + Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); + Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); } else { - Ops.push_back(Tmp2); - Ops.push_back(Tmp3); - Ops.push_back(CC); - Ops.push_back(Cond); - Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); - - Ops.clear(); - Ops.push_back(Tmp3); - Ops.push_back(Tmp1); - Ops.push_back(CC); - Ops.push_back(Cond); - Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size()); + Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4); + Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4); } - VTs = DAG.getNodeValueTypes(VT, VT); - Ops.clear(); - Ops.push_back(Lo); - Ops.push_back(Hi); - return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size()); + SDOperand Ops[2] = { Lo, Hi }; + return DAG.getMergeValues(DAG.getVTList(VT, VT), Ops, 2); } SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { @@ -4531,13 +4508,15 @@ SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) { std::pair Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG); SDOperand FIST = Vals.first, StackSlot = Vals.second; if (FIST.Val == 0) return 0; - - // Return an i64 load from the stack slot. - SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0); + + MVT VT = N->getValueType(0); + + // Return a load from the stack slot. + SDOperand Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0); // Use a MERGE_VALUES node to drop the chain result value. - return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val; -} + return DAG.getMergeValues(DAG.getVTList(VT), &Res, 1, false).Val; +} SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { MVT VT = Op.getValueType(); @@ -4833,11 +4812,8 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); - std::vector Tys; - Tys.push_back(SPTy); - Tys.push_back(MVT::Other); SDOperand Ops1[2] = { Chain.getValue(0), Chain }; - return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2); + return DAG.getMergeValues(DAG.getVTList(SPTy, MVT::Other), Ops1, 2); } SDOperand @@ -5069,7 +5045,7 @@ SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ }; Tys = DAG.getVTList(MVT::i64, MVT::Other); - return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val; + return DAG.getMergeValues(Tys, Ops, 2).Val; } SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); @@ -5081,8 +5057,7 @@ SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ // Use a MERGE_VALUES to return the value and chain. Ops[1] = edx.getValue(1); - Tys = DAG.getVTList(MVT::i64, MVT::Other); - return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val; + return DAG.getMergeValues(DAG.getVTList(MVT::i64, MVT::Other), Ops, 2).Val; } SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { @@ -5463,7 +5438,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, SDOperand Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; - return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2); + return DAG.getMergeValues(Op.Val->getVTList(), Ops, 2); } else { const Function *Func = cast(cast(Op.getOperand(5))->getValue()); @@ -5531,7 +5506,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, SDOperand Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; - return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2); + return DAG.getMergeValues(Op.Val->getVTList(), Ops, 2); } } @@ -5718,8 +5693,8 @@ SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) cpOutL.getValue(2)); SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); - Tys = DAG.getVTList(MVT::i64, MVT::Other); - return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val; + SDOperand Vals[2] = { ResultVal, cpOutH.getValue(1) }; + return DAG.getMergeValues(DAG.getVTList(MVT::i64, MVT::Other), Vals, 2).Val; } SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) { -- 2.34.1