From f86c29ea2c0321aa4dcad42c83ff7f09bab1b7d8 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Thu, 23 Apr 2015 20:31:26 +0000 Subject: [PATCH] ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets. This makes it more likely that we can use the 16-bit push and pop instructions on Thumb-2, saving around 4 bytes per function. Differential Revision: http://reviews.llvm.org/D9165 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235637 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFrameLowering.cpp | 4 +-- .../CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll | 2 +- ...013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll | 2 +- ...13-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll | 2 +- test/CodeGen/ARM/debug-frame.ll | 32 +++++++++---------- test/CodeGen/ARM/fold-stack-adjust.ll | 16 +++++----- test/CodeGen/ARM/interrupt-attr.ll | 4 +-- test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll | 4 +-- test/CodeGen/Thumb2/large-stack.ll | 2 +- test/CodeGen/Thumb2/tpsoft.ll | 12 +++---- test/MC/ARM/elf-thumbfunc-reloc.ll | 4 +-- 11 files changed, 42 insertions(+), 42 deletions(-) diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp index 9d2b09b4067..92fe8fe5fbc 100644 --- a/lib/Target/ARM/ARMFrameLowering.cpp +++ b/lib/Target/ARM/ARMFrameLowering.cpp @@ -1688,8 +1688,8 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, if (CS1Spilled && !UnspilledCS1GPRs.empty()) { for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { unsigned Reg = UnspilledCS1GPRs[i]; - // Don't spill high register if the function is thumb1 - if (!AFI->isThumb1OnlyFunction() || + // Don't spill high register if the function is thumb + if (!AFI->isThumbFunction() || isARMLowRegister(Reg) || Reg == ARM::LR) { MRI.setPhysRegUsed(Reg); if (!MRI.isReserved(Reg)) diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll index 446403d79ca..5e82b0925b2 100644 --- a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll +++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll @@ -33,7 +33,7 @@ define void @foo2(double %p0, ; --> D0 %struct_t* byval %p10) ; --> Stack+8 { entry: -;CHECK: push.w {r11, lr} +;CHECK: push {r7, lr} ;CHECK-NOT: stm ;CHECK: add r0, sp, #16 ;CHECK: bl fooUseStruct diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll index 68b918d2d7d..c93d2a2d34f 100644 --- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll @@ -22,7 +22,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP i32 %p3) #0 { ; --> SP+4, NSAA=SP+12 entry: ;CHECK: sub sp, #12 - ;CHECK: push.w {r11, lr} + ;CHECK: push {r7, lr} ;CHECK: sub sp, #4 ;CHECK: add r0, sp, #12 ;CHECK: str r2, [sp, #16] diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll index 212bbc2ee9c..944a60c0610 100644 --- a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll @@ -19,7 +19,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP i32 %p2) #0 { ; --> SP+24, NSAA=SP+24 entry: - ;CHECK: push.w {r11, lr} + ;CHECK: push {r7, lr} ;CHECK: ldr r0, [sp, #32] ;CHECK: bl fooUseI32 call void @fooUseI32(i32 %p2) diff --git a/test/CodeGen/ARM/debug-frame.ll b/test/CodeGen/ARM/debug-frame.ll index 9b115edc74d..1205585b412 100644 --- a/test/CodeGen/ARM/debug-frame.ll +++ b/test/CodeGen/ARM/debug-frame.ll @@ -264,14 +264,14 @@ declare void @_ZSt9terminatev() ; CHECK-THUMB-V7-FP-LABEL: _Z4testiiiiiddddd: ; CHECK-THUMB-V7-FP: .cfi_startproc -; CHECK-THUMB-V7-FP: push.w {r4, r7, r11, lr} +; CHECK-THUMB-V7-FP: push {r4, r6, r7, lr} ; CHECK-THUMB-V7-FP: .cfi_def_cfa_offset 16 ; CHECK-THUMB-V7-FP: .cfi_offset lr, -4 -; CHECK-THUMB-V7-FP: .cfi_offset r11, -8 -; CHECK-THUMB-V7-FP: .cfi_offset r7, -12 +; CHECK-THUMB-V7-FP: .cfi_offset r7, -8 +; CHECK-THUMB-V7-FP: .cfi_offset r6, -12 ; CHECK-THUMB-V7-FP: .cfi_offset r4, -16 -; CHECK-THUMB-V7-FP: add r7, sp, #4 -; CHECK-THUMB-V7-FP: .cfi_def_cfa r7, 12 +; CHECK-THUMB-V7-FP: add r7, sp, #8 +; CHECK-THUMB-V7-FP: .cfi_def_cfa r7, 8 ; CHECK-THUMB-V7-FP: vpush {d8, d9, d10, d11, d12} ; CHECK-THUMB-V7-FP: .cfi_offset d12, -24 ; CHECK-THUMB-V7-FP: .cfi_offset d11, -32 @@ -300,14 +300,14 @@ declare void @_ZSt9terminatev() ; CHECK-THUMB-V7-FP-NOIAS-LABEL: _Z4testiiiiiddddd: ; CHECK-THUMB-V7-FP-NOIAS: .cfi_startproc -; CHECK-THUMB-V7-FP-NOIAS: push.w {r4, r7, r11, lr} +; CHECK-THUMB-V7-FP-NOIAS: push {r4, r6, r7, lr} ; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa_offset 16 ; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 14, -4 -; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 11, -8 -; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 7, -12 +; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 7, -8 +; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 6, -12 ; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 4, -16 -; CHECK-THUMB-V7-FP-NOIAS: add r7, sp, #4 -; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa 7, 12 +; CHECK-THUMB-V7-FP-NOIAS: add r7, sp, #8 +; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa 7, 8 ; CHECK-THUMB-V7-FP-NOIAS: vpush {d8, d9, d10, d11, d12} ; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 268, -24 ; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 267, -32 @@ -404,11 +404,11 @@ entry: ; CHECK-THUMB-V7-FP-ELIM-LABEL: test2: ; CHECK-THUMB-V7-FP-ELIM: .cfi_startproc -; CHECK-THUMB-V7-FP-ELIM: push.w {r11, lr} +; CHECK-THUMB-V7-FP-ELIM: push {r7, lr} ; CHECK-THUMB-V7-FP-ELIM: .cfi_def_cfa_offset 8 ; CHECK-THUMB-V7-FP-ELIM: .cfi_offset lr, -4 -; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r11, -8 -; CHECK-THUMB-V7-FP-ELIM: pop.w {r11, pc} +; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r7, -8 +; CHECK-THUMB-V7-FP-ELIM: pop {r7, pc} ; CHECK-THUMB-V7-FP-ELIM: .cfi_endproc @@ -522,13 +522,13 @@ entry: ; CHECK-THUMB-V7-FP-ELIM-LABEL: test3: ; CHECK-THUMB-V7-FP-ELIM: .cfi_startproc -; CHECK-THUMB-V7-FP-ELIM: push.w {r4, r5, r11, lr} +; CHECK-THUMB-V7-FP-ELIM: push {r4, r5, r7, lr} ; CHECK-THUMB-V7-FP-ELIM: .cfi_def_cfa_offset 16 ; CHECK-THUMB-V7-FP-ELIM: .cfi_offset lr, -4 -; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r11, -8 +; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r7, -8 ; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r5, -12 ; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r4, -16 -; CHECK-THUMB-V7-FP-ELIM: pop.w {r4, r5, r11, pc} +; CHECK-THUMB-V7-FP-ELIM: pop {r4, r5, r7, pc} ; CHECK-THUMB-V7-FP-ELIM: .cfi_endproc diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll index aff79a1c113..1fd9bd9e47a 100644 --- a/test/CodeGen/ARM/fold-stack-adjust.ll +++ b/test/CodeGen/ARM/fold-stack-adjust.ll @@ -12,11 +12,11 @@ declare void @bar(i8*) define void @check_simple() minsize { ; CHECK-LABEL: check_simple: -; CHECK: push.w {r7, r8, r9, r10, r11, lr} +; CHECK: push {r3, r4, r5, r6, r7, lr} ; CHECK-NOT: sub sp, sp, ; ... ; CHECK-NOT: add sp, sp, -; CHECK: pop.w {r0, r1, r2, r3, r11, pc} +; CHECK: pop {r0, r1, r2, r3, r7, pc} ; CHECK-T1-LABEL: check_simple: ; CHECK-T1: push {r3, r4, r5, r6, r7, lr} @@ -44,11 +44,11 @@ define void @check_simple() minsize { define void @check_simple_too_big() minsize { ; CHECK-LABEL: check_simple_too_big: -; CHECK: push.w {r11, lr} +; CHECK: push {r7, lr} ; CHECK: sub sp, ; ... ; CHECK: add sp, -; CHECK: pop.w {r11, pc} +; CHECK: pop {r7, pc} %var = alloca i8, i32 64 call void @bar(i8* %var) ret void @@ -93,11 +93,11 @@ define void @check_vfp_fold() minsize { ; folded in except that doing so would clobber the value being returned. define i64 @check_no_return_clobber() minsize { ; CHECK-LABEL: check_no_return_clobber: -; CHECK: push.w {r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr} ; CHECK-NOT: sub sp, ; ... ; CHECK: add sp, #24 -; CHECK: pop.w {r11, pc} +; CHECK: pop {r7, pc} ; Just to keep iOS FileCheck within previous function: ; CHECK-IOS-LABEL: check_no_return_clobber: @@ -176,9 +176,9 @@ define void @test_varsize(...) minsize { ; CHECK-LABEL: test_varsize: ; CHECK: sub sp, #16 -; CHECK: push.w {r9, r10, r11, lr} +; CHECK: push {r5, r6, r7, lr} ; ... -; CHECK: pop.w {r2, r3, r11, lr} +; CHECK: pop.w {r2, r3, r7, lr} ; CHECK: add sp, #16 ; CHECK: bx lr diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll index 95ada085b0d..43bd5815a55 100644 --- a/test/CodeGen/ARM/interrupt-attr.ll +++ b/test/CodeGen/ARM/interrupt-attr.ll @@ -35,7 +35,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to ; appropriate sentinel so no special return needed). ; CHECK-M-LABEL: irq_fn: -; CHECK-M: push.w {r4, r10, r11, lr} +; CHECK-M: push.w {r4, r7, r11, lr} ; CHECK-M: add.w r11, sp, #8 ; CHECK-M: mov r4, sp ; CHECK-M: bfc r4, #0, #3 @@ -43,7 +43,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-M: bl _bar ; CHECK-M: sub.w r4, r11, #8 ; CHECK-M: mov sp, r4 -; CHECK-M: pop.w {r4, r10, r11, pc} +; CHECK-M: pop.w {r4, r7, r11, pc} call arm_aapcscc void @bar() ret void diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll index 59c23673211..a451321838e 100644 --- a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll +++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll @@ -7,8 +7,8 @@ entry: ; CHECK-LABEL: __gcov_execlp: ; CHECK: sub sp, #8 ; CHECK: push -; CHECK: add r7, sp, #4 -; CHECK: sub.w r4, r7, #4 +; CHECK: add r7, sp, #8 +; CHECK: sub.w r4, r7, #8 ; CHECK: mov sp, r4 ; CHECK-NOT: mov sp, r7 ; CHECK: add sp, #8 diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll index ff9e0501970..4fe49825fa3 100644 --- a/test/CodeGen/Thumb2/large-stack.ll +++ b/test/CodeGen/Thumb2/large-stack.ll @@ -29,7 +29,7 @@ define i32 @test3() { ; DARWIN: sub.w sp, sp, #805306368 ; DARWIN: sub sp, #20 ; LINUX-LABEL: test3: -; LINUX: push.w {r4, r7, r11, lr} +; LINUX: push {r4, r6, r7, lr} ; LINUX: sub.w sp, sp, #805306368 ; LINUX: sub sp, #16 %retval = alloca i32, align 4 diff --git a/test/CodeGen/Thumb2/tpsoft.ll b/test/CodeGen/Thumb2/tpsoft.ll index 89757cad563..de358d98d49 100644 --- a/test/CodeGen/Thumb2/tpsoft.ll +++ b/test/CodeGen/Thumb2/tpsoft.ll @@ -32,13 +32,13 @@ bb: ; preds = %entry ; ELFOBJ: Section { ; ELFOBJ: Name: .text ; ELFOBJ-LE: SectionData ( -;;; BL __aeabi_read_tp is ---------+ -;;; V -; ELFOBJ-LE-NEXT: 0000: 2DE90048 0E487844 0168FFF7 FEFF4058 +;;; BL __aeabi_read_tp is ---+ +;;; V +; ELFOBJ-LE-NEXT: 0000: 80B50E48 78440168 FFF7FEFF 40580D28 ; ELFOBJ-BE: SectionData ( -;;; BL __aeabi_read_tp is ---------+ -;;; V -; ELFOBJ-BE-NEXT: 0000: E92D4800 480E4478 6801F7FF FFFE5840 +;;; BL __aeabi_read_tp is ---+ +;;; V +; ELFOBJ-BE-NEXT: 0000: B580480E 44786801 F7FFFFFE 5840280D bb1: ; preds = %entry diff --git a/test/MC/ARM/elf-thumbfunc-reloc.ll b/test/MC/ARM/elf-thumbfunc-reloc.ll index 2ac0b117062..52579581875 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.ll +++ b/test/MC/ARM/elf-thumbfunc-reloc.ll @@ -24,13 +24,13 @@ entry: ; make sure that bl 0 (fff7feff) is correctly encoded ; CHECK: Sections [ ; CHECK: SectionData ( -; CHECK: 0000: 70472DE9 0048FFF7 FEFFBDE8 0088 +; CHECK: 0000: 704780B5 FFF7FEFF 80BD ; CHECK: ) ; CHECK: ] ; CHECK: Relocations [ ; CHECK-NEXT: Section {{.*}} .rel.text { -; CHECK-NEXT: 0x6 R_ARM_THM_CALL foo 0x0 +; CHECK-NEXT: 0x4 R_ARM_THM_CALL foo 0x0 ; CHECK-NEXT: } ; CHECK-NEXT: Section {{.*}} .rel.ARM.exidx { ; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0 -- 2.34.1