From f8396b83c686aa2db02866716660714491efd4ba Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Mon, 15 Dec 2014 20:10:28 +0000 Subject: [PATCH] [Hexagon] Adding accumulating half word multiplies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224266 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfo.td | 105 +++++++++++++++++++++ test/MC/Disassembler/Hexagon/xtype_mpy.txt | 48 ++++++++++ 2 files changed, 153 insertions(+) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 98a210f04b6..fbf4e54310f 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -1829,6 +1829,111 @@ let Defs = [USR_OVF], isCodeGenOnly = 0 in { def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>; } +//===----------------------------------------------------------------------===// +// Template Class +// MPYS / Multipy signed/unsigned halfwords and add/subtract the +// result from the accumulator. +//Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] +//===----------------------------------------------------------------------===// + +let hasNewValue = 1, opNewValue = 0 in +class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac, + bit hasShift, bit isUnsigned > + : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), + "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") + #"($Rs."#!if(LHbits{1},"h","l") + #", $Rt."#!if(LHbits{0},"h)","l)") + #!if(hasShift,":<<1","") + #!if(isSat,":sat",""), + [], "$dst2 = $Rx", M_tc_3x_SLOT23 > { + bits<5> Rx; + bits<5> Rs; + bits<5> Rt; + + let IClass = 0b1110; + let Inst{27-24} = 0b1110; + let Inst{23} = hasShift; + let Inst{22} = isUnsigned; + let Inst{21} = isNac; + let Inst{7} = isSat; + let Inst{6-5} = LHbits; + let Inst{4-0} = Rx; + let Inst{20-16} = Rs; + let Inst{12-8} = Rt; + } + +//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1] +let isCodeGenOnly = 0 in { +def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>; +def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>; +def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>; +def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>; +def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>; +def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>; +def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>; +def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>; +} + +//Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1] +let isCodeGenOnly = 0 in { +def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>; +def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>; +def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>; +def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>; +def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>; +def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>; +def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>; +def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>; +} + +//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1] +let isCodeGenOnly = 0 in { +def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>; +def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>; +def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>; +def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>; +def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>; +def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>; +def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>; +def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>; +} + +//Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1] +let isCodeGenOnly = 0 in { +def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>; +def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>; +def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>; +def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>; +def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>; +def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>; +def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>; +def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>; +} + +//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat +let isCodeGenOnly = 0 in { +def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>; +def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>; +def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>; +def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>; +def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>; +def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>; +def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>; +def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>; +} + +//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat +let isCodeGenOnly = 0 in { +def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>; +def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>; +def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>; +def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>; +def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>; +def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>; +def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>; +def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>; +} + // Multiply and use lower result. // Rd=+mpyi(Rs,#u8) let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 8 in diff --git a/test/MC/Disassembler/Hexagon/xtype_mpy.txt b/test/MC/Disassembler/Hexagon/xtype_mpy.txt index a410b533894..9e5a170fa9c 100644 --- a/test/MC/Disassembler/Hexagon/xtype_mpy.txt +++ b/test/MC/Disassembler/Hexagon/xtype_mpy.txt @@ -32,6 +32,38 @@ # CHECK: r17 = mpy(r21.h, r31.l):<<1:rnd:sat 0xf1 0xdf 0xb5 0xec # CHECK: r17 = mpy(r21.h, r31.h):<<1:rnd:sat +0x11 0xdf 0x95 0xee +# CHECK: r17 += mpy(r21.l, r31.l):<<1 +0x31 0xdf 0x95 0xee +# CHECK: r17 += mpy(r21.l, r31.h):<<1 +0x51 0xdf 0x95 0xee +# CHECK: r17 += mpy(r21.h, r31.l):<<1 +0x71 0xdf 0x95 0xee +# CHECK: r17 += mpy(r21.h, r31.h):<<1 +0x91 0xdf 0x95 0xee +# CHECK: r17 += mpy(r21.l, r31.l):<<1:sat +0xb1 0xdf 0x95 0xee +# CHECK: r17 += mpy(r21.l, r31.h):<<1:sat +0xd1 0xdf 0x95 0xee +# CHECK: r17 += mpy(r21.h, r31.l):<<1:sat +0xf1 0xdf 0x95 0xee +# CHECK: r17 += mpy(r21.h, r31.h):<<1:sat +0x11 0xdf 0xb5 0xee +# CHECK: r17 -= mpy(r21.l, r31.l):<<1 +0x31 0xdf 0xb5 0xee +# CHECK: r17 -= mpy(r21.l, r31.h):<<1 +0x51 0xdf 0xb5 0xee +# CHECK: r17 -= mpy(r21.h, r31.l):<<1 +0x71 0xdf 0xb5 0xee +# CHECK: r17 -= mpy(r21.h, r31.h):<<1 +0x91 0xdf 0xb5 0xee +# CHECK: r17 -= mpy(r21.l, r31.l):<<1:sat +0xb1 0xdf 0xb5 0xee +# CHECK: r17 -= mpy(r21.l, r31.h):<<1:sat +0xd1 0xdf 0xb5 0xee +# CHECK: r17 -= mpy(r21.h, r31.l):<<1:sat +0xf1 0xdf 0xb5 0xee +# CHECK: r17 -= mpy(r21.h, r31.h):<<1:sat 0x11 0xdf 0xd5 0xec # CHECK: r17 = mpyu(r21.l, r31.l):<<1 0x31 0xdf 0xd5 0xec @@ -40,3 +72,19 @@ # CHECK: r17 = mpyu(r21.h, r31.l):<<1 0x71 0xdf 0xd5 0xec # CHECK: r17 = mpyu(r21.h, r31.h):<<1 +0x11 0xdf 0xd5 0xee +# CHECK: r17 += mpyu(r21.l, r31.l):<<1 +0x31 0xdf 0xd5 0xee +# CHECK: r17 += mpyu(r21.l, r31.h):<<1 +0x51 0xdf 0xd5 0xee +# CHECK: r17 += mpyu(r21.h, r31.l):<<1 +0x71 0xdf 0xd5 0xee +# CHECK: r17 += mpyu(r21.h, r31.h):<<1 +0x11 0xdf 0xf5 0xee +# CHECK: r17 -= mpyu(r21.l, r31.l):<<1 +0x31 0xdf 0xf5 0xee +# CHECK: r17 -= mpyu(r21.l, r31.h):<<1 +0x51 0xdf 0xf5 0xee +# CHECK: r17 -= mpyu(r21.h, r31.l):<<1 +0x71 0xdf 0xf5 0xee +# CHECK: r17 -= mpyu(r21.h, r31.h):<<1 -- 2.34.1