From f2eb1e4286bf397d60a37e6f288ac81e644a3258 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 11 Sep 2013 11:58:30 +0000 Subject: [PATCH] [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190518 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsMSAInstrInfo.td | 48 ++--- lib/Target/Mips/MipsSEISelLowering.cpp | 36 ++++ test/CodeGen/Mips/msa/3r-m.ll | 64 ++++++ test/CodeGen/Mips/msa/3r-s.ll | 259 +++++++++++++++++++++++++ 4 files changed, 383 insertions(+), 24 deletions(-) diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 83f20ad16e9..d4dcbd1f5e1 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -1700,20 +1700,20 @@ class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, MSA128W>; -class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", int_mips_mulv_b, MSA128B>; -class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", int_mips_mulv_h, MSA128H>; -class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", int_mips_mulv_w, MSA128W>; -class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", int_mips_mulv_d, MSA128D>; +class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128B>; +class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128H>; +class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128W>; +class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128D>; class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128B>; class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128H>; class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128W>; class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128D>; -class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", int_mips_nlzc_b, MSA128B>; -class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", int_mips_nlzc_h, MSA128H>; -class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", int_mips_nlzc_w, MSA128W>; -class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", int_mips_nlzc_d, MSA128D>; +class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128B>; +class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128H>; +class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128W>; +class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128D>; class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", int_mips_nor_v, MSA128B>; @@ -1762,10 +1762,10 @@ class SLDI_H_DESC : MSA_BIT_H_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128H>; class SLDI_W_DESC : MSA_BIT_W_DESC_BASE<"sldi.w", int_mips_sldi_w, MSA128W>; class SLDI_D_DESC : MSA_BIT_D_DESC_BASE<"sldi.d", int_mips_sldi_d, MSA128D>; -class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", int_mips_sll_b, MSA128B>; -class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", int_mips_sll_h, MSA128H>; -class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", int_mips_sll_w, MSA128W>; -class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", int_mips_sll_d, MSA128D>; +class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128B>; +class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128H>; +class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128W>; +class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128D>; class SLLI_B_DESC : MSA_BIT_B_DESC_BASE<"slli.b", int_mips_slli_b, MSA128B>; class SLLI_H_DESC : MSA_BIT_H_DESC_BASE<"slli.h", int_mips_slli_h, MSA128H>; @@ -1790,10 +1790,10 @@ class SPLATI_W_DESC : MSA_BIT_W_DESC_BASE<"splati.w", int_mips_splati_w, class SPLATI_D_DESC : MSA_BIT_D_DESC_BASE<"splati.d", int_mips_splati_d, MSA128D>; -class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", int_mips_sra_b, MSA128B>; -class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", int_mips_sra_h, MSA128H>; -class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", int_mips_sra_w, MSA128W>; -class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", int_mips_sra_d, MSA128D>; +class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128B>; +class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128H>; +class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128W>; +class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128D>; class SRAI_B_DESC : MSA_BIT_B_DESC_BASE<"srai.b", int_mips_srai_b, MSA128B>; class SRAI_H_DESC : MSA_BIT_H_DESC_BASE<"srai.h", int_mips_srai_h, MSA128H>; @@ -1810,10 +1810,10 @@ class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h, MSA128H>; class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w, MSA128W>; class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d, MSA128D>; -class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", int_mips_srl_b, MSA128B>; -class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", int_mips_srl_h, MSA128H>; -class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", int_mips_srl_w, MSA128W>; -class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", int_mips_srl_d, MSA128D>; +class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128B>; +class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128H>; +class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128W>; +class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128D>; class SRLI_B_DESC : MSA_BIT_B_DESC_BASE<"srli.b", int_mips_srli_b, MSA128B>; class SRLI_H_DESC : MSA_BIT_H_DESC_BASE<"srli.h", int_mips_srli_h, MSA128H>; @@ -1890,10 +1890,10 @@ class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, MSA128D>; -class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", int_mips_subv_b, MSA128B>; -class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", int_mips_subv_h, MSA128H>; -class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", int_mips_subv_w, MSA128W>; -class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", int_mips_subv_d, MSA128D>; +class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128B>; +class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128H>; +class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128W>; +class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128D>; class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", int_mips_subvi_b, MSA128B>; class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", int_mips_subvi_h, MSA128H>; diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index c307aa76d81..879df6d1299 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -160,7 +160,13 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::STORE, Ty, Legal); setOperationAction(ISD::ADD, Ty, Legal); + setOperationAction(ISD::CTLZ, Ty, Legal); + setOperationAction(ISD::MUL, Ty, Legal); setOperationAction(ISD::SDIV, Ty, Legal); + setOperationAction(ISD::SHL, Ty, Legal); + setOperationAction(ISD::SRA, Ty, Legal); + setOperationAction(ISD::SRL, Ty, Legal); + setOperationAction(ISD::SUB, Ty, Legal); setOperationAction(ISD::UDIV, Ty, Legal); } @@ -930,6 +936,36 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_fsub_w: case Intrinsic::mips_fsub_d: return lowerMSABinaryIntr(Op, DAG, ISD::FSUB); + case Intrinsic::mips_mulv_b: + case Intrinsic::mips_mulv_h: + case Intrinsic::mips_mulv_w: + case Intrinsic::mips_mulv_d: + return lowerMSABinaryIntr(Op, DAG, ISD::MUL); + case Intrinsic::mips_nlzc_b: + case Intrinsic::mips_nlzc_h: + case Intrinsic::mips_nlzc_w: + case Intrinsic::mips_nlzc_d: + return lowerMSAUnaryIntr(Op, DAG, ISD::CTLZ); + case Intrinsic::mips_sll_b: + case Intrinsic::mips_sll_h: + case Intrinsic::mips_sll_w: + case Intrinsic::mips_sll_d: + return lowerMSABinaryIntr(Op, DAG, ISD::SHL); + case Intrinsic::mips_sra_b: + case Intrinsic::mips_sra_h: + case Intrinsic::mips_sra_w: + case Intrinsic::mips_sra_d: + return lowerMSABinaryIntr(Op, DAG, ISD::SRA); + case Intrinsic::mips_srl_b: + case Intrinsic::mips_srl_h: + case Intrinsic::mips_srl_w: + case Intrinsic::mips_srl_d: + return lowerMSABinaryIntr(Op, DAG, ISD::SRL); + case Intrinsic::mips_subv_b: + case Intrinsic::mips_subv_h: + case Intrinsic::mips_subv_w: + case Intrinsic::mips_subv_d: + return lowerMSABinaryIntr(Op, DAG, ISD::SUB); } } diff --git a/test/CodeGen/Mips/msa/3r-m.ll b/test/CodeGen/Mips/msa/3r-m.ll index 041d603dd4d..1612cfd267c 100644 --- a/test/CodeGen/Mips/msa/3r-m.ll +++ b/test/CodeGen/Mips/msa/3r-m.ll @@ -794,4 +794,68 @@ declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: mulv.d ; CHECK: st.d ; CHECK: .size llvm_mips_mulv_d_test + +define void @mulv_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_mulv_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_mulv_b_ARG2 + %2 = mul <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_mulv_b_RES + ret void +} + +; CHECK: mulv_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: mulv.b +; CHECK: st.b +; CHECK: .size mulv_b_test + +define void @mulv_h_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_mulv_h_ARG1 + %1 = load <8 x i16>* @llvm_mips_mulv_h_ARG2 + %2 = mul <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_mulv_h_RES + ret void +} + +; CHECK: mulv_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: mulv.h +; CHECK: st.h +; CHECK: .size mulv_h_test + +define void @mulv_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_mulv_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_mulv_w_ARG2 + %2 = mul <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_mulv_w_RES + ret void +} + +; CHECK: mulv_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: mulv.w +; CHECK: st.w +; CHECK: .size mulv_w_test + +define void @mulv_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_mulv_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_mulv_d_ARG2 + %2 = mul <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_mulv_d_RES + ret void +} + +; CHECK: mulv_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: mulv.d +; CHECK: st.d +; CHECK: .size mulv_d_test ; diff --git a/test/CodeGen/Mips/msa/3r-s.ll b/test/CodeGen/Mips/msa/3r-s.ll index 9031fd80470..735b2d5aaac 100644 --- a/test/CodeGen/Mips/msa/3r-s.ll +++ b/test/CodeGen/Mips/msa/3r-s.ll @@ -178,6 +178,70 @@ declare <2 x i64> @llvm.mips.sll.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: sll.d ; CHECK: st.d ; CHECK: .size llvm_mips_sll_d_test + +define void @sll_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_sll_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_sll_b_ARG2 + %2 = shl <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_sll_b_RES + ret void +} + +; CHECK: sll_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: sll.b +; CHECK: st.b +; CHECK: .size sll_b_test + +define void @sll_h_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_sll_h_ARG1 + %1 = load <8 x i16>* @llvm_mips_sll_h_ARG2 + %2 = shl <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_sll_h_RES + ret void +} + +; CHECK: sll_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: sll.h +; CHECK: st.h +; CHECK: .size sll_h_test + +define void @sll_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_sll_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_sll_w_ARG2 + %2 = shl <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_sll_w_RES + ret void +} + +; CHECK: sll_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: sll.w +; CHECK: st.w +; CHECK: .size sll_w_test + +define void @sll_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_sll_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_sll_d_ARG2 + %2 = shl <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_sll_d_RES + ret void +} + +; CHECK: sll_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: sll.d +; CHECK: st.d +; CHECK: .size sll_d_test ; @llvm_mips_sra_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sra_b_ARG2 = global <16 x i8> , align 16 @@ -267,6 +331,71 @@ declare <2 x i64> @llvm.mips.sra.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_sra_d_test ; + +define void @sra_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_sra_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_sra_b_ARG2 + %2 = ashr <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_sra_b_RES + ret void +} + +; CHECK: sra_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: sra.b +; CHECK: st.b +; CHECK: .size sra_b_test + +define void @sra_h_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_sra_h_ARG1 + %1 = load <8 x i16>* @llvm_mips_sra_h_ARG2 + %2 = ashr <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_sra_h_RES + ret void +} + +; CHECK: sra_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: sra.h +; CHECK: st.h +; CHECK: .size sra_h_test + +define void @sra_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_sra_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_sra_w_ARG2 + %2 = ashr <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_sra_w_RES + ret void +} + +; CHECK: sra_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: sra.w +; CHECK: st.w +; CHECK: .size sra_w_test + +define void @sra_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_sra_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_sra_d_ARG2 + %2 = ashr <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_sra_d_RES + ret void +} + +; CHECK: sra_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: sra.d +; CHECK: st.d +; CHECK: .size sra_d_test + @llvm_mips_srar_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_srar_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_srar_b_RES = global <16 x i8> , align 16 @@ -531,6 +660,71 @@ declare <2 x i64> @llvm.mips.srlr.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_srlr_d_test ; + +define void @srl_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_srl_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_srl_b_ARG2 + %2 = lshr <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_srl_b_RES + ret void +} + +; CHECK: srl_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: srl.b +; CHECK: st.b +; CHECK: .size srl_b_test + +define void @srl_h_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_srl_h_ARG1 + %1 = load <8 x i16>* @llvm_mips_srl_h_ARG2 + %2 = lshr <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_srl_h_RES + ret void +} + +; CHECK: srl_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: srl.h +; CHECK: st.h +; CHECK: .size srl_h_test + +define void @srl_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_srl_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_srl_w_ARG2 + %2 = lshr <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_srl_w_RES + ret void +} + +; CHECK: srl_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: srl.w +; CHECK: st.w +; CHECK: .size srl_w_test + +define void @srl_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_srl_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_srl_d_ARG2 + %2 = lshr <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_srl_d_RES + ret void +} + +; CHECK: srl_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: srl.d +; CHECK: st.d +; CHECK: .size srl_d_test + @llvm_mips_subs_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_subs_s_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_subs_s_b_RES = global <16 x i8> , align 16 @@ -971,3 +1165,68 @@ declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_subv_d_test ; + +define void @subv_b_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_subv_b_ARG1 + %1 = load <16 x i8>* @llvm_mips_subv_b_ARG2 + %2 = sub <16 x i8> %0, %1 + store <16 x i8> %2, <16 x i8>* @llvm_mips_subv_b_RES + ret void +} + +; CHECK: subv_b_test: +; CHECK: ld.b +; CHECK: ld.b +; CHECK: subv.b +; CHECK: st.b +; CHECK: .size subv_b_test + +define void @subv_h_test() nounwind { +entry: + %0 = load <8 x i16>* @llvm_mips_subv_h_ARG1 + %1 = load <8 x i16>* @llvm_mips_subv_h_ARG2 + %2 = sub <8 x i16> %0, %1 + store <8 x i16> %2, <8 x i16>* @llvm_mips_subv_h_RES + ret void +} + +; CHECK: subv_h_test: +; CHECK: ld.h +; CHECK: ld.h +; CHECK: subv.h +; CHECK: st.h +; CHECK: .size subv_h_test + +define void @subv_w_test() nounwind { +entry: + %0 = load <4 x i32>* @llvm_mips_subv_w_ARG1 + %1 = load <4 x i32>* @llvm_mips_subv_w_ARG2 + %2 = sub <4 x i32> %0, %1 + store <4 x i32> %2, <4 x i32>* @llvm_mips_subv_w_RES + ret void +} + +; CHECK: subv_w_test: +; CHECK: ld.w +; CHECK: ld.w +; CHECK: subv.w +; CHECK: st.w +; CHECK: .size subv_w_test + +define void @subv_d_test() nounwind { +entry: + %0 = load <2 x i64>* @llvm_mips_subv_d_ARG1 + %1 = load <2 x i64>* @llvm_mips_subv_d_ARG2 + %2 = sub <2 x i64> %0, %1 + store <2 x i64> %2, <2 x i64>* @llvm_mips_subv_d_RES + ret void +} + +; CHECK: subv_d_test: +; CHECK: ld.d +; CHECK: ld.d +; CHECK: subv.d +; CHECK: st.d +; CHECK: .size subv_d_test +; -- 2.34.1