From f23cbf56e9e48f116d56567f1c6ec4393f1d881a Mon Sep 17 00:00:00 2001 From: Zheng Yang Date: Fri, 28 Nov 2014 14:13:16 +0800 Subject: [PATCH] rk3036/rk3128 hdmi: According to HDMI CTS 7-19, GCP SB1~SB6 value must be zero if color mode is 24bit. So we enable reg04 bit4 which will set CD[0:3] of SB1 to zero. --- .../video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c | 4 ++-- .../video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h | 9 ++++++++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c b/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c index 7c7b2770468b..3228b52d7eed 100755 --- a/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c +++ b/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.c @@ -314,7 +314,7 @@ static int rk3036_hdmi_video_csc(struct hdmi *hdmi_drv, if ((vpara->input_color >= VIDEO_INPUT_COLOR_YCBCR444) || ((vpara->input_color == VIDEO_INPUT_COLOR_RGB) && (vpara->color_limit_range == COLOR_LIMIT_RANGE_0_255))) { - value = v_SOF_DISABLE; + value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1); hdmi_writel(hdmi_dev, VIDEO_CONTRL3, value); hdmi_msk_reg(hdmi_dev, VIDEO_CONTRL, m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_EXCHANGE, @@ -389,7 +389,7 @@ static int rk3036_hdmi_video_csc(struct hdmi *hdmi_drv, hdmi_writel(hdmi_dev, VIDEO_CSC_COEF+i, coeff[i]); } - value = v_SOF_DISABLE | csc_enable; + value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1); hdmi_writel(hdmi_dev, VIDEO_CONTRL3, value); hdmi_msk_reg(hdmi_dev, VIDEO_CONTRL, m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_EXCHANGE, diff --git a/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h b/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h index 20b326653e6c..6032b96cf317 100755 --- a/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h +++ b/drivers/video/rockchip/hdmi/chips/rk3036/rk3036_hdmi_hw.h @@ -112,10 +112,17 @@ enum { #define VIDEO_CONTRL3 0x04 +#define m_COLOR_DEPTH_NOT_INDICATED (1 << 4) #define m_SOF (1 << 3) +#define m_COLOR_RANGE (1 << 2) #define m_CSC (1 << 0) +#define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4) /*1: Force GCP CD[3:0] zero + 0: GCP CD[3:0] according + color depth*/ #define v_SOF_ENABLE (0 << 3) #define v_SOF_DISABLE (1 << 3) +#define v_COLOR_RANGE_FULL (1 << 2) +#define v_COLOR_RANGE_LIMITED (0 << 2) #define v_CSC_ENABLE 1 #define v_CSC_DISABLE 0 @@ -399,7 +406,7 @@ static inline int hdmi_msk_reg(struct rk_hdmi_device *hdmi_dev, u16 offset, } static inline void rk3036_hdmi_reset_pclk(void) { - writel_relaxed(0x00010001, RK_CRU_VIRT+ 0x128); + writel_relaxed(0x00010001, RK_CRU_VIRT + 0x128); msleep(100); writel_relaxed(0x00010000, RK_CRU_VIRT + 0x128); } -- 2.34.1