From ee1c8707789ac540ca2d0037d397f39fa91e7571 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 24 Jun 2010 15:24:03 +0000 Subject: [PATCH] Eliminate the other half of the BRCOND optimization, and update as many tests as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106749 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 7 - test/CodeGen/ARM/reg_sequence.ll | 4 +- test/CodeGen/PowerPC/2010-02-26-FoldFloats.ll | 433 ------------------ test/CodeGen/X86/2008-03-18-CoalescerBug.ll | 2 +- test/CodeGen/X86/2008-04-09-BranchFolding.ll | 2 +- test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll | 8 +- test/CodeGen/X86/2009-01-12-CoalescerBug.ll | 84 ---- test/CodeGen/X86/2009-09-07-CoalescerBug.ll | 47 -- .../X86/2009-09-19-SchedCustomLoweringBug.ll | 29 -- test/CodeGen/X86/2009-12-12-CoalescerBug.ll | 40 -- test/CodeGen/X86/loop-strength-reduce6.ll | 18 +- 11 files changed, 17 insertions(+), 657 deletions(-) delete mode 100644 test/CodeGen/PowerPC/2010-02-26-FoldFloats.ll delete mode 100644 test/CodeGen/X86/2009-01-12-CoalescerBug.ll delete mode 100644 test/CodeGen/X86/2009-09-07-CoalescerBug.ll delete mode 100644 test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll delete mode 100644 test/CodeGen/X86/2009-12-12-CoalescerBug.ll diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 5719cefb42e..cd86f8fc32e 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3015,7 +3015,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) { // Perform various simplifications. ConstantSDNode *N1C = dyn_cast(N1.getNode()); - ConstantSDNode *N2C = dyn_cast(N2.getNode()); switch (Opcode) { case ISD::CONCAT_VECTORS: // A CONCAT_VECTOR with all operands BUILD_VECTOR can be simplified to @@ -3045,12 +3044,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, if (N2 == N3) return N2; // select C, X, X -> X break; - case ISD::BRCOND: - if (N2C) { - if (!N2C->getZExtValue()) // Unconditional branch - return N1; // Never-taken branch - } - break; case ISD::VECTOR_SHUFFLE: llvm_unreachable("should use getVectorShuffle constructor!"); break; diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 79ed84f0dff..b00020c3950 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -250,13 +250,13 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { br label %8 ;