From eb7876083dcfb3a69264d14c130177ecf4fc4930 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 17 Mar 2014 17:03:51 +0000 Subject: [PATCH] R600/SI: Use correct dest register class for V_READFIRSTLANE_B32 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This instructions writes to an 32-bit SGPR. This change required adding the 32-bit VCC_LO and VCC_HI registers, because the full VCC register is 64 bits. This fixes verifier errors on several of the indirect addressing piglit tests. Tested-by: Michel Dänzer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204055 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUAsmPrinter.cpp | 3 ++- lib/Target/R600/SIInstructions.td | 13 ++++++++++++- lib/Target/R600/SILowerControlFlow.cpp | 5 +++-- lib/Target/R600/SIRegisterInfo.td | 13 +++++++++++-- test/CodeGen/R600/private-memory.ll | 4 ++-- 5 files changed, 30 insertions(+), 8 deletions(-) diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp index ccc3d135876..b166c4556fd 100644 --- a/lib/Target/R600/AMDGPUAsmPrinter.cpp +++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp @@ -210,7 +210,8 @@ void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF, continue; } unsigned reg = MO.getReg(); - if (reg == AMDGPU::VCC) { + if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO || + reg == AMDGPU::VCC_HI) { VCCUsed = true; continue; } diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 03e954f4aaf..9a18f7bc350 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -631,7 +631,18 @@ let neverHasSideEffects = 1, isMoveImm = 1 in { defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; } // End neverHasSideEffects = 1, isMoveImm = 1 -defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; +let Uses = [EXEC] in { + +def V_READFIRSTLANE_B32 : VOP1 < + 0x00000002, + (outs SReg_32:$vdst), + (ins VReg_32:$src0), + "V_READFIRSTLANE_B32 $vdst, $src0", + [] +>; + +} + defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", [(set i32:$dst, (fp_to_sint f64:$src0))] >; diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp index 5ec49308668..182f28ba774 100644 --- a/lib/Target/R600/SILowerControlFlow.cpp +++ b/lib/Target/R600/SILowerControlFlow.cpp @@ -345,12 +345,13 @@ void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) { .addReg(AMDGPU::EXEC); // Read the next variant into VCC (lower 32 bits) <- also loop target - BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC) + BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), + AMDGPU::VCC_LO) .addReg(Idx); // Move index from VCC into M0 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) - .addReg(AMDGPU::VCC); + .addReg(AMDGPU::VCC_LO); // Compare the just read M0 value to all possible Idx values BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC) diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index 49bdbc9fdbf..65cf311dd96 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -17,7 +17,16 @@ class SIReg encoding = 0> : Register { } // Special Registers -def VCC : SIReg<"VCC", 106>; +def VCC_LO : SIReg<"vcc_lo", 106>; +def VCC_HI : SIReg<"vcc_hi", 107>; + +// VCC for 64-bit instructions +def VCC : RegisterWithSubRegs<"VCC", [VCC_LO, VCC_HI]> { + let Namespace = "AMDGPU"; + let SubRegIndices = [sub0, sub1]; + let HWEncoding = 106; +} + def EXEC : SIReg<"EXEC", 126>; def SCC : SIReg<"SCC", 253>; def M0 : SIReg <"M0", 124>; @@ -150,7 +159,7 @@ def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>; // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, - (add SGPR_32, M0Reg) + (add SGPR_32, M0Reg, VCC_LO) >; def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>; diff --git a/test/CodeGen/R600/private-memory.ll b/test/CodeGen/R600/private-memory.ll index e22c718f310..4920320a537 100644 --- a/test/CodeGen/R600/private-memory.ll +++ b/test/CodeGen/R600/private-memory.ll @@ -13,10 +13,10 @@ ; R600-CHECK-NOT: ALU clause ; R600-CHECK: 0 + AR.x -; SI-CHECK: V_READFIRSTLANE +; SI-CHECK: V_READFIRSTLANE_B32 vcc_lo ; SI-CHECK: V_MOVRELD ; SI-CHECK: S_CBRANCH -; SI-CHECK: V_READFIRSTLANE +; SI-CHECK: V_READFIRSTLANE_B32 vcc_lo ; SI-CHECK: V_MOVRELD ; SI-CHECK: S_CBRANCH define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { -- 2.34.1