From e7d845b7093c4b2b3924730a3b7fda288aa90191 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Mon, 5 Jan 2015 21:22:42 +0000 Subject: [PATCH] [PowerPC] Add another test for load/store with update We now produce the desired code as noted in the README.txt file. Remove the README entry and add a regression test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225205 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/README.txt | 34 ------------------------------- test/CodeGen/PowerPC/ld-st-upd.ll | 19 +++++++++++++++++ 2 files changed, 19 insertions(+), 34 deletions(-) create mode 100644 test/CodeGen/PowerPC/ld-st-upd.ll diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt index 9c424eb483a..f705139e680 100644 --- a/lib/Target/PowerPC/README.txt +++ b/lib/Target/PowerPC/README.txt @@ -31,40 +31,6 @@ Ick. ===-------------------------------------------------------------------------=== -Support 'update' load/store instructions. These are cracked on the G5, but are -still a codesize win. - -With preinc enabled, this: - -long *%test4(long *%X, long *%dest) { - %Y = getelementptr long* %X, int 4 - %A = load long* %Y - store long %A, long* %dest - ret long* %Y -} - -compiles to: - -_test4: - mr r2, r3 - lwzu r5, 32(r2) - lwz r3, 36(r3) - stw r5, 0(r4) - stw r3, 4(r4) - mr r3, r2 - blr - -with -sched=list-burr, I get: - -_test4: - lwz r2, 36(r3) - lwzu r5, 32(r3) - stw r2, 4(r4) - stw r5, 0(r4) - blr - -===-------------------------------------------------------------------------=== - We compile the hottest inner loop of viterbi to: li r6, 0 diff --git a/test/CodeGen/PowerPC/ld-st-upd.ll b/test/CodeGen/PowerPC/ld-st-upd.ll new file mode 100644 index 00000000000..24f31aca05a --- /dev/null +++ b/test/CodeGen/PowerPC/ld-st-upd.ll @@ -0,0 +1,19 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc-unknown-linux-gnu" + +; Function Attrs: nounwind +define i32* @test4(i32* readonly %X, i32* nocapture %dest) #0 { + %Y = getelementptr i32* %X, i64 4 + %A = load i32* %Y, align 4 + store i32 %A, i32* %dest, align 4 + ret i32* %Y + +; CHECK-LABEL: @test4 +; CHECK: lwzu [[REG1:[0-9]+]], 16(3) +; CHECK: stw [[REG1]], 0(4) +; CHECK: blr +} + +attributes #0 = { nounwind } + -- 2.34.1