From e6220fb2305bdc993dc9039fffafd82c609c1c50 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Thu, 16 Jul 2009 13:32:49 +0000
Subject: [PATCH] Add reg-reg and pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75917 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/SystemZ/SystemZInstrInfo.td | 8 ++++++++
 test/CodeGen/SystemZ/02-RetAnd.ll      | 7 +++++++
 test/CodeGen/SystemZ/02-RetAndImm.ll   | 9 +++++++++
 3 files changed, 24 insertions(+)
 create mode 100644 test/CodeGen/SystemZ/02-RetAnd.ll
 create mode 100644 test/CodeGen/SystemZ/02-RetAndImm.ll

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 0b8ab46da4a..99e6c1b77af 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -69,6 +69,14 @@ def ADD64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
                      [(set GR64:$dst, (add GR64:$src1, imm:$src2)),
                       (implicit PSW)]>;
 
+let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
+// FIXME: Provide proper encoding!
+def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+                     "ngr\t{$dst, $src2}",
+                     [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
+}
+// FIXME: provide patterns for masked and-with-imm
+
 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 // FIXME: Provide proper encoding!
 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
diff --git a/test/CodeGen/SystemZ/02-RetAnd.ll b/test/CodeGen/SystemZ/02-RetAnd.ll
new file mode 100644
index 00000000000..e174d077281
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetAnd.ll
@@ -0,0 +1,7 @@
+; RUN: llvm-as < %s | llc
+
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    %c = and i64 %a, %b
+    ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetAndImm.ll b/test/CodeGen/SystemZ/02-RetAndImm.ll
new file mode 100644
index 00000000000..5753723cb1b
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetAndImm.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    %c = and i64 %a, 1
+    ret i64 %c
+}
+
+; FIXME: SystemZ has 4 and reg-imm instructions depending on imm,
+; we need to support them someday.
\ No newline at end of file
-- 
2.34.1