From e4dfc196e4add93dabd006dd110d88fe3069dd85 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Fri, 16 May 2014 10:27:10 +0000 Subject: [PATCH] [mips][mips64r6] Add LWPC and LWUPC instructions Differential Revision: http://reviews.llvm.org/D3788 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208971 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips32r6InstrFormats.td | 2 ++ lib/Target/Mips/Mips32r6InstrInfo.td | 13 +++++++++---- test/MC/Mips/mips32r6/valid.s | 2 ++ test/MC/Mips/mips64r6/valid.s | 2 ++ 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/lib/Target/Mips/Mips32r6InstrFormats.td b/lib/Target/Mips/Mips32r6InstrFormats.td index 3fe8f918c56..4d49ca1812e 100644 --- a/lib/Target/Mips/Mips32r6InstrFormats.td +++ b/lib/Target/Mips/Mips32r6InstrFormats.td @@ -35,6 +35,8 @@ class OPCODE2 Val> { bits<2> Value = Val; } def OPCODE2_ADDIUPC : OPCODE2<0b00>; +def OPCODE2_LWPC : OPCODE2<0b01>; +def OPCODE2_LWUPC : OPCODE2<0b10>; class OPCODE5 Val> { bits<5> Value = Val; diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 6f2548c6080..9c57ed6c7ab 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -81,6 +81,9 @@ class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>; class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>; class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>; +class LWPC_ENC : PCREL19_FM; +class LWUPC_ENC : PCREL19_FM; + class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>; class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>; class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>; @@ -172,14 +175,16 @@ multiclass CMP_CC_M { +class PCREL19_DESC_BASE { dag OutOperandList = (outs GPROpnd:$rs); dag InOperandList = (ins simm19_lsl2:$imm); string AsmString = !strconcat(instr_asm, "\t$rs, $imm"); list Pattern = []; } -class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>; +class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>; +class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>; +class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>; class ALIGN_DESC_BASE { @@ -347,8 +352,8 @@ def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; def JIALC; def JIC; // def LSA; // See MSA -def LWPC; -def LWUPC; +def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; +def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6; def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6; def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6; diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 933513a35f7..b83cbe1a4d7 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -44,6 +44,8 @@ cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] + lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] # mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 1cb2f86aae1..1551e5f3422 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -55,6 +55,8 @@ ddivu $2,$3,$4 # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f] dmod $2,$3,$4 # CHECK: dmod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xde] dmodu $2,$3,$4 # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf] + lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] + lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] # mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] -- 2.34.1