From e4b2165648e81542e654006ab753152ab48d63fa Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Sun, 20 Jul 2014 22:26:40 +0000 Subject: [PATCH] [PowerPC] Fix FrameIndex handling in SelectAddressRegImm The PPCTargetLowering::SelectAddressRegImm routine needs to handle FrameIndex nodes in a special manner, by tranlating them into a TargetFrameIndex node. This was done in most cases, but seems to have been neglected in one path: when the input tree has an OR of the FrameIndex with an immediate. This can happen if the FrameIndex can be proven to be sufficiently aligned that an OR of that immediate is equivalent to an ADD. The missing handling of FrameIndex in that case caused the SelectionDAG instruction selection to miss opportunities to merge the OR back into the FrameIndex node, leading to superfluous addi/ori instructions in the final assembler output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213482 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 8 +++++++- test/CodeGen/PowerPC/anon_aggr.ll | 26 +++++++++----------------- test/CodeGen/PowerPC/complex-return.ll | 2 +- test/CodeGen/PowerPC/vsx.ll | 2 +- 4 files changed, 18 insertions(+), 20 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index e2826f726dd..251c2362a52 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1331,7 +1331,13 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { // If all of the bits are known zero on the LHS or RHS, the add won't // carry. - Base = N.getOperand(0); + if (FrameIndexSDNode *FI = + dyn_cast(N.getOperand(0))) { + Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); + fixupFuncForFI(DAG, FI->getIndex(), N.getValueType()); + } else { + Base = N.getOperand(0); + } Disp = DAG.getTargetConstant(imm, N.getValueType()); return true; } diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll index 3bae5c6516c..6c4f140de12 100644 --- a/test/CodeGen/PowerPC/anon_aggr.ll +++ b/test/CodeGen/PowerPC/anon_aggr.ll @@ -62,8 +62,7 @@ unequal: } ; CHECK-LABEL: func2: -; CHECK: addi [[REG1:[0-9]+]], 1, 64 -; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]]) +; CHECK: ld [[REG2:[0-9]+]], 72(1) ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]] ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]] ; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]] @@ -82,8 +81,7 @@ unequal: ; DARWIN32: lwz r3, -[[OFFSET2]] ; DARWIN64: _func2: -; DARWIN64: addi r[[REG1:[0-9]+]], r1, 64 -; DARWIN64: ld r[[REG2:[0-9]+]], 8(r[[REG1]]) +; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1) ; DARWIN64: mr ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]] ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REG2]] @@ -108,10 +106,8 @@ unequal: } ; CHECK-LABEL: func3: -; CHECK: addi [[REG1:[0-9]+]], 1, 64 -; CHECK: addi [[REG2:[0-9]+]], 1, 48 -; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]]) -; CHECK: ld [[REG4:[0-9]+]], 8([[REG2]]) +; CHECK: ld [[REG3:[0-9]+]], 72(1) +; CHECK: ld [[REG4:[0-9]+]], 56(1) ; CHECK: cmpld {{[0-9]+}}, [[REG4]], [[REG3]] ; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1) ; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1) @@ -130,10 +126,8 @@ unequal: ; DARWIN32: lwz r3, -[[OFFSET1]] ; DARWIN64: _func3: -; DARWIN64: addi r[[REG1:[0-9]+]], r1, 64 -; DARWIN64: addi r[[REG2:[0-9]+]], r1, 48 -; DARWIN64: ld r[[REG3:[0-9]+]], 8(r[[REG1]]) -; DARWIN64: ld r[[REG4:[0-9]+]], 8(r[[REG2]]) +; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1) +; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1) ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG4]], r[[REG3]] ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]] ; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]] @@ -157,12 +151,11 @@ unequal: } ; CHECK-LABEL: func4: -; CHECK: addi [[REG1:[0-9]+]], 1, 128 +; CHECK: ld [[REG3:[0-9]+]], 136(1) ; CHECK: ld [[REG2:[0-9]+]], 120(1) -; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]]) ; CHECK: cmpld {{[0-9]+}}, [[REG2]], [[REG3]] -; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1) ; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1) +; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1) ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) @@ -178,9 +171,8 @@ unequal: ; DARWIN32: lwz r[[REG1]], -[[OFFSET2]] ; DARWIN64: _func4: -; DARWIN64: addi r[[REG1:[0-9]+]], r1, 128 ; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1) -; DARWIN64: ld r[[REG3:[0-9]+]], 8(r[[REG1]]) +; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1) ; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]] ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG2]], r[[REG3]] ; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]] diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll index 5ac7524ff5c..8a6adaee555 100644 --- a/test/CodeGen/PowerPC/complex-return.ll +++ b/test/CodeGen/PowerPC/complex-return.ll @@ -26,8 +26,8 @@ entry: ; CHECK-LABEL: foo: ; CHECK: lfd 3 ; CHECK: lfd 4 -; CHECK: lfd 2 ; CHECK: lfd 1 +; CHECK: lfd 2 define { float, float } @oof() nounwind { entry: diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index f5ac577a75d..2f226e1f614 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -634,7 +634,7 @@ define <2 x i32> @test80(i32 %v) { ; CHECK-DAG: addi [[R1:[0-9]+]], 3, 3 ; CHECK-DAG: addi [[R2:[0-9]+]], 1, -16 ; CHECK-DAG: addi [[R3:[0-9]+]], 3, 2 -; CHECK: std [[R1]], 8([[R2]]) +; CHECK: std [[R1]], -8(1) ; CHECK: std [[R3]], -16(1) ; CHECK: lxvd2x 34, 0, [[R2]] ; CHECK-NOT: stxvd2x -- 2.34.1