From e2a48fbd9d1ec8bebb5b10cf8770d716f8bdda28 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 22 Aug 2013 00:14:24 +0000 Subject: [PATCH] ARM: R9 is not safe to use for tcGPR. Indirect tail-calls shouldn't use R9 for the branch destination, as it's not reliably a call-clobbered register. rdar://14793425 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188967 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMRegisterInfo.td | 2 +- test/CodeGen/Thumb2/tail-call-r9.ll | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/Thumb2/tail-call-r9.ll diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index bb7d358ff18..90c6a965acf 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -251,7 +251,7 @@ def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>; // to the saved value before the tail call, which would clobber a call address. // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of // this class and the preceding one(!) This is what we want. -def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> { +def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> { let AltOrders = [(and tcGPR, tGPR)]; let AltOrderSelect = [{ return MF.getTarget().getSubtarget().isThumb1Only(); diff --git a/test/CodeGen/Thumb2/tail-call-r9.ll b/test/CodeGen/Thumb2/tail-call-r9.ll new file mode 100644 index 00000000000..24c76c98c03 --- /dev/null +++ b/test/CodeGen/Thumb2/tail-call-r9.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 | FileCheck %s + +@foo = common global void ()* null, align 4 + +; Make sure in the presence of a tail call, r9 doesn't get used to hold +; the destination address. It's callee-saved in AAPCS. +define arm_aapcscc void @test(i32 %a) nounwind { +; CHECK-LABEL: test: +; CHECK-NOT bx r9 + %tmp = load void ()** @foo, align 4 + tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r12}"() nounwind + tail call arm_aapcscc void %tmp() nounwind + ret void +} -- 2.34.1