From dbef0175c327c9b0987587402f12ba5845da381a Mon Sep 17 00:00:00 2001 From: Jozef Kolek Date: Mon, 20 Apr 2015 13:04:14 +0000 Subject: [PATCH] [mips][microMIPSr6] Implement BALC and BC instructions This patch implements BALC and BC instructions using mapping. Differential Revision: http://reviews.llvm.org/D8388 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235302 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrInfo.td | 50 +++++++++++++++++++++++ lib/Target/Mips/Mips32r6InstrInfo.td | 7 ++-- lib/Target/Mips/MipsInstrInfo.td | 4 ++ test/MC/Mips/micromips32r6/valid.s | 5 +++ 4 files changed, 63 insertions(+), 3 deletions(-) create mode 100644 lib/Target/Mips/MicroMips32r6InstrInfo.td create mode 100644 test/MC/Mips/micromips32r6/valid.s diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td new file mode 100644 index 00000000000..ed97aae014f --- /dev/null +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -0,0 +1,50 @@ +//=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes microMIPSr6 instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// Instruction Encodings +// +//===----------------------------------------------------------------------===// + +class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; +class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; + +//===----------------------------------------------------------------------===// +// +// Instruction Descriptions +// +//===----------------------------------------------------------------------===// + +class BC_MMR6_DESC_BASE + : BRANCH_DESC_BASE, MMR6Arch { + dag InOperandList = (ins opnd:$offset); + dag OutOperandList = (outs); + string AsmString = !strconcat(instr_asm, "\t$offset"); + bit isBarrier = 1; +} + +class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> { + bit isCall = 1; + list Defs = [RA]; +} +class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>; + +//===----------------------------------------------------------------------===// +// +// Instruction Definitions +// +//===----------------------------------------------------------------------===// + +def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6; +def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 49c63226dc0..5f61349e091 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -289,7 +289,8 @@ class BRANCH_DESC_BASE { bit hasDelaySlot = 0; } -class BC_DESC_BASE : BRANCH_DESC_BASE { +class BC_DESC_BASE : BRANCH_DESC_BASE, + MipsR6Arch { dag InOperandList = (ins opnd:$offset); dag OutOperandList = (outs); string AsmString = !strconcat(instr_asm, "\t$offset"); @@ -648,12 +649,12 @@ def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6; def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; -def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6; +def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6; def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6; def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6; def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; -def BC : BC_ENC, BC_DESC, ISA_MIPS32R6; +def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6; def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 2fed7dc6e15..db890382548 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1913,3 +1913,7 @@ include "MipsMSAInstrInfo.td" include "MicroMipsInstrFormats.td" include "MicroMipsInstrInfo.td" include "MicroMipsInstrFPU.td" + +// Micromips r6 +include "MicroMips32r6InstrFormats.td" +include "MicroMips32r6InstrInfo.td" diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s new file mode 100644 index 00000000000..e0e854450b9 --- /dev/null +++ b/test/MC/Mips/micromips32r6/valid.s @@ -0,0 +1,5 @@ +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s + + .set noat + balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8] + bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] -- 2.34.1