From dadc0f7c20f12ecf15ce9db7faeac269b717a8c7 Mon Sep 17 00:00:00 2001
From: Peizhao Ou <peizhaoo@uci.edu>
Date: Tue, 3 Apr 2018 01:03:23 -0700
Subject: [PATCH] Adds only one "dmb ld" for a sequence of adajcent stores

---
 .../AArch64/AArch64LoadStoreOptimizer.cpp     | 83 ++++++++++++++++++-
 1 file changed, 81 insertions(+), 2 deletions(-)

diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 988bc24ee6e..202b19525e1 100644
--- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1524,13 +1524,87 @@ bool AArch64LoadStoreOpt::tryToMergeLdStInst(
   return false;
 }
 
+static bool isLoad(MachineInstr* MI) {
+  switch (MI->getOpcode()) {
+    default: { return false; }
+    case AArch64::LDRBBpost:
+    case AArch64::LDRBBpre:
+    case AArch64::LDRBBui:
+    case AArch64::LDRBpost:
+    case AArch64::LDRBpre:
+    case AArch64::LDRBui:
+    case AArch64::LDRDpost:
+    case AArch64::LDRDpre:
+    case AArch64::LDRDui:
+    case AArch64::LDRHHpost:
+    case AArch64::LDRHHpre:
+    case AArch64::LDRHHui:
+    case AArch64::LDRHpost:
+    case AArch64::LDRHpre:
+    case AArch64::LDRHui:
+    case AArch64::LDRQpost:
+    case AArch64::LDRQpre:
+    case AArch64::LDRQui:
+    case AArch64::LDRSBWpost:
+    case AArch64::LDRSBWpre:
+    case AArch64::LDRSBWui:
+    case AArch64::LDRSBXpost:
+    case AArch64::LDRSBXpre:
+    case AArch64::LDRSBXui:
+    case AArch64::LDRSHWpost:
+    case AArch64::LDRSHWpre:
+    case AArch64::LDRSHWui:
+    case AArch64::LDRSHXpost:
+    case AArch64::LDRSHXpre:
+    case AArch64::LDRSHXui:
+    case AArch64::LDRSpost:
+    case AArch64::LDRSpre:
+    case AArch64::LDRSui:
+    case AArch64::LDRSWpost:
+    case AArch64::LDRSWpre:
+    case AArch64::LDRSWui:
+    case AArch64::LDRWpost:
+    case AArch64::LDRWpre:
+    case AArch64::LDRWui:
+    case AArch64::LDRXpost:
+    case AArch64::LDRXpre:
+    case AArch64::LDRXui:
+    case AArch64::LDTRBi:
+    case AArch64::LDTRHi:
+    case AArch64::LDTRSBWi:
+    case AArch64::LDTRSBXi:
+    case AArch64::LDTRSHWi:
+    case AArch64::LDTRSHXi:
+    case AArch64::LDTRSWi:
+    case AArch64::LDTRWi:
+    case AArch64::LDTRXi:
+    case AArch64::LDURBBi:
+    case AArch64::LDURBi:
+    case AArch64::LDURDi:
+    case AArch64::LDURHHi:
+    case AArch64::LDURHi:
+    case AArch64::LDURQi:
+    case AArch64::LDURSBWi:
+    case AArch64::LDURSBXi:
+    case AArch64::LDURSHWi:
+    case AArch64::LDURSHXi:
+    case AArch64::LDURSi:
+    case AArch64::LDURSWi:
+    case AArch64::LDURWi:
+    case AArch64::LDURXi: {
+      return true;
+    }
+  }
+}
+
 bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
                                         bool enableNarrowLdOpt) {
   // XXX-update: Try to add a 'dmb ld' fence before a relaxed store in the form
   // of machine code.
-  for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); MBBI != E;
-       ++MBBI) {
+  for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+       MBBI != E;) {
     MachineInstr* MI = MBBI;
+    ++MBBI;
     // If this is not a atomic/volatile op, ignore it.
     if (!MI->hasOrderedMemoryRef()) {
       continue;
@@ -1591,6 +1665,11 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
         (void) DMBInst;
         DEBUG(dbgs() << "Added barrier instruction\n\t" << *DMBInst
                      << "\n\tfor " << *MI << "\n");
+        // Skip all the way till we reach the end of the basic block or a load.
+        while (MBBI != E && !isLoad(&*MBBI)) {
+          MBBI++;
+        }
+        break;
       }
       default: { break; }
     }
-- 
2.34.1