From daada81e5c15f0db4c7150e38ae7dab988a044d5 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Thu, 21 Aug 2014 13:28:02 +0000 Subject: [PATCH] DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments. PR20677 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216175 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 ++++++- test/CodeGen/X86/avx512-select.ll | 9 +++++++++ test/CodeGen/X86/vselect.ll | 9 +++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f6dc9384ee3..5fd9bf39e0e 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4689,12 +4689,17 @@ static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) { SDValue Cond = N->getOperand(0); SDValue LHS = N->getOperand(1); SDValue RHS = N->getOperand(2); - MVT VT = N->getSimpleValueType(0); + EVT VT = N->getValueType(0); int NumElems = VT.getVectorNumElements(); assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && RHS.getOpcode() == ISD::CONCAT_VECTORS && Cond.getOpcode() == ISD::BUILD_VECTOR); + // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about + // binary ones here. + if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2) + return SDValue(); + // We're sure we have an even number of elements due to the // concat_vectors we have as arguments to vselect. // Skip BV elements until we find one that's not an UNDEF diff --git a/test/CodeGen/X86/avx512-select.ll b/test/CodeGen/X86/avx512-select.ll index 83f46984781..e222113a706 100644 --- a/test/CodeGen/X86/avx512-select.ll +++ b/test/CodeGen/X86/avx512-select.ll @@ -39,3 +39,12 @@ define double @select03(double %a, double %b, double %c, double %eps) { %cond = select i1 %cmp, double %c, double %b ret double %cond } + +; CHECK-LABEL: @select04 +; CHECK: vmovaps %zmm3, %zmm1 +; CHECK-NEXT: ret +; PR20677 +define <16 x double> @select04(<16 x double> %a, <16 x double> %b) { + %sel = select <16 x i1> , <16 x double> %a, <16 x double> %b + ret <16 x double> %sel +} diff --git a/test/CodeGen/X86/vselect.ll b/test/CodeGen/X86/vselect.ll index 42cf06a4a04..ee2a96f0085 100644 --- a/test/CodeGen/X86/vselect.ll +++ b/test/CodeGen/X86/vselect.ll @@ -276,3 +276,12 @@ define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x %7 = fsub <4 x float> %3, %6 ret <4 x float> %7 } + +; CHECK-LABEL: @select_illegal +; CHECK: mov +; CHECK: ret +; PR20677 +define <16 x double> @select_illegal(<16 x double> %a, <16 x double> %b) { + %sel = select <16 x i1> , <16 x double> %a, <16 x double> %b + ret <16 x double> %sel +} -- 2.34.1