From d68eea2b6d5ff284d3c7371c4f201c25ca030747 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Wed, 19 Aug 2009 08:46:10 +0000 Subject: [PATCH] PR4737: Fix a nasty bug in load narrowing with non-power-of-two types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79415 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 ++- .../X86/2009-08-19-LoadNarrowingMiscompile.ll | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 3c4f9de1cd9..4138e98f18e 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3466,7 +3466,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { // Is the shift amount a multiple of size of VT? if ((ShAmt & (EVTBits-1)) == 0) { N0 = N0.getOperand(0); - if (N0.getValueType().getSizeInBits() <= EVTBits) + // Is the load width a multiple of size of VT? + if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) return SDValue(); } } diff --git a/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll b/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll new file mode 100644 index 00000000000..447b06483d3 --- /dev/null +++ b/test/CodeGen/X86/2009-08-19-LoadNarrowingMiscompile.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86 | FileCheck %s + +@a = external global i96, align 4 +@b = external global i64, align 8 + +define void @c() nounwind { +; CHECK: movl a+8, %eax + %srcval1 = load i96* @a, align 4 + %sroa.store.elt2 = lshr i96 %srcval1, 64 + %tmp = trunc i96 %sroa.store.elt2 to i64 +; CHECK: movl %eax, b +; CHECK: movl $0, b+4 + store i64 %tmp, i64* @b, align 8 + ret void +} -- 2.34.1