From d3af696c08923d4d376641b52c3b2cb5baa00487 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Fri, 19 Apr 2013 15:44:32 +0000 Subject: [PATCH] ARM: Permit "sp" in ARM variant of STREXD instructions Patch from Mihail Popa git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 +- test/MC/Disassembler/ARM/basic-arm-instructions.txt | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 631168b1539..32b47fba514 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -3573,7 +3573,7 @@ static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, unsigned Rn = fieldFromInstruction(Insn, 16, 4); unsigned pred = fieldFromInstruction(Insn, 28, 4); - if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 505ecad9d3a..9f63e1e914f 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -1823,12 +1823,13 @@ # CHECK: strexh r4, r2, [r5 # CHECK: strex r2, r1, [r7 # CHECK: strexd r6, r2, r3, [r8 +# CHECK: strexd sp, r0, r1, [r0] 0x93 0x1f 0xc4 0xe1 0x92 0x4f 0xe5 0xe1 0x91 0x2f 0x87 0xe1 0x92 0x6f 0xa8 0xe1 - +0x90 0xdf 0xa0 0xe1 #------------------------------------------------------------------------------ # SUB -- 2.34.1