From cfd5c26107eedcbf432d14f47042aebf9e9e8ffe Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Tue, 11 Nov 2008 19:35:15 +0000
Subject: [PATCH] fix some validation errors <it> -> <i>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59070 91177308-0d34-0410-b5e6-96231b3b80d8
---
 docs/WritingAnLLVMBackend.html | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html
index e57a2dd458b..acb5defbece 100644
--- a/docs/WritingAnLLVMBackend.html
+++ b/docs/WritingAnLLVMBackend.html
@@ -103,7 +103,7 @@ These essential documents must be read before reading this document:
 a reference manual for the LLVM assembly language
 </li>
 <li>
-<it><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM Target-Independent Code Generator </a></it> - 
+<i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM Target-Independent Code Generator </a></i> - 
 a guide to the components (classes and code generation algorithms) for translating 
 the LLVM internal representation to the machine code for a specified target. 
 Pay particular attention to the descriptions of code generation stages: 
@@ -112,24 +112,24 @@ Register Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizatio
 and Code Emission. 
 </li>
 <li>
-<it><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen Fundamentals</a></it> - 
+<i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen Fundamentals</a></i> - 
 a document that describes the TableGen (tblgen) application that manages domain-specific 
 information to support LLVM code generation. TableGen processes input from a 
 target description file (.td suffix) and generates C++ code that can be used 
 for code generation.
 </li>
 <li>
-<it><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM Pass</a></it> - 
+<i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM Pass</a></i> - 
 The assembly printer is a FunctionPass, as are several SelectionDAG processing steps.
 </li>
 </ul>
 To follow the SPARC examples in this document, have a copy of 
-<it><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture Manual, Version 8</a></it> 
+<i><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture Manual, Version 8</a></i> 
 for reference. For details about the ARM instruction set, refer to the 
-<it><a href="http://infocenter.arm.com/">ARM Architecture Reference Manual</a></it>
+<i><a href="http://infocenter.arm.com/">ARM Architecture Reference Manual</a></i>
 For more about the GNU Assembler format (GAS), see 
-<it><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></it>
-especially for the assembly printer. <it>Using As</it> contains lists of target machine dependent features. 
+<i><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></i>
+especially for the assembly printer. <i>Using As</i> contains lists of target machine dependent features. 
 </div>
 
 <div class="doc_subsection">
-- 
2.34.1