From cde587f359cb032f80ea73b84a8bf574341adeac Mon Sep 17 00:00:00 2001 From: Vladimir Medic Date: Wed, 21 Jan 2015 10:47:36 +0000 Subject: [PATCH] [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226652 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../Mips/Disassembler/MipsDisassembler.cpp | 21 +++++++++++++++++++ lib/Target/Mips/Mips32r6InstrInfo.td | 2 ++ .../Mips/mips32r6/valid-mips32r6-el.txt | 4 ++++ .../Mips/mips32r6/valid-mips32r6.txt | 4 ++++ .../Mips/mips32r6/valid-xfail-mips32r6.txt | 4 ---- .../Mips/mips64r6/valid-mips64r6-el.txt | 4 ++++ .../Mips/mips64r6/valid-mips64r6.txt | 4 ++++ .../Mips/mips64r6/valid-xfail-mips64r6.txt | 4 ---- 8 files changed, 39 insertions(+), 8 deletions(-) diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index da33f3b913c..98fc1ebba15 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -304,6 +304,10 @@ static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1354,6 +1358,23 @@ static DecodeStatus DecodeFMem3(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<11>(Insn & 0x07ff); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 185d12ec93f..baf746061be 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -561,6 +561,7 @@ class COP2LD_DESC_BASE { string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); list Pattern = []; bit mayLoad = 1; + string DecoderMethod = "DecodeFMemCop2R6"; } class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>; @@ -572,6 +573,7 @@ class COP2ST_DESC_BASE { string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); list Pattern = []; bit mayStore = 1; + string DecoderMethod = "DecodeFMemCop2R6"; } class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>; diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt index eff7abb89e5..ce6dd40b72f 100644 --- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt +++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt @@ -138,3 +138,7 @@ 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 +0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1) +0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6) +0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18) +0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16) diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt index da8a7975698..4781d0c4db8 100644 --- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt +++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt @@ -138,3 +138,7 @@ 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 +0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) +0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) +0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) +0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt index 928cd5a30db..45c5410e74f 100644 --- a/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt +++ b/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt @@ -17,7 +17,3 @@ 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) -0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) -0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) -0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) -0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt index 0aa89e66c3d..77e232aea95 100644 --- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt +++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt @@ -156,3 +156,7 @@ 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 +0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1) +0xb7 0x34 0x52 0x49 # CHECK: lwc2 $18, -841($6) +0x75 0x92 0xf4 0x49 # CHECK: sdc2 $20, 629($18) +0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16) diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index d471f82cb23..66baf5f2f1c 100644 --- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -156,3 +156,7 @@ 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885 +0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) +0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) +0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) +0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt index 3718f8a1767..400f1c75caa 100644 --- a/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt +++ b/test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt @@ -17,10 +17,6 @@ 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) -0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) -0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) -0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) -0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 -- 2.34.1