From ccafe05df13273571f6457879d73d40ce320ad60 Mon Sep 17 00:00:00 2001 From: James Y Knight Date: Mon, 18 May 2015 16:43:33 +0000 Subject: [PATCH] Sparc: support the "set" synthetic instruction. This pseudo-instruction expands into 'sethi' and 'or' instructions, or, just one of them, if the other isn't necessary for a given value. Differential Revision: http://reviews.llvm.org/D9089 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237585 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 62 ++++++++++++++++++- lib/Target/Sparc/SparcInstrAliases.td | 6 ++ lib/Target/Sparc/SparcInstrFormats.td | 8 +++ test/MC/Sparc/sparc-synthetic-instructions.s | 17 +++++ 4 files changed, 91 insertions(+), 2 deletions(-) create mode 100644 test/MC/Sparc/sparc-synthetic-instructions.s diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index a2d46b657a6..1082678171f 100644 --- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -77,6 +77,10 @@ class SparcAsmParser : public MCTargetAsmParser { bool parseDirectiveWord(unsigned Size, SMLoc L); bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); } + + void expandSET(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + public: SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, @@ -392,6 +396,49 @@ public: } // end namespace +void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOperand MCValOp = Inst.getOperand(1); + assert(MCRegOp.isReg()); + assert(MCValOp.isImm() || MCValOp.isExpr()); + + // the imm operand can be either an expression or an immediate. + bool IsImm = Inst.getOperand(1).isImm(); + uint64_t ImmValue = IsImm ? MCValOp.getImm() : 0; + const MCExpr *ValExpr; + if (IsImm) + ValExpr = MCConstantExpr::Create(ImmValue, getContext()); + else + ValExpr = MCValOp.getExpr(); + + MCOperand PrevReg = MCOperand::createReg(Sparc::G0); + + if (!IsImm || (ImmValue & ~0x1fff)) { + MCInst TmpInst; + const MCExpr *Expr = + SparcMCExpr::Create(SparcMCExpr::VK_Sparc_HI, ValExpr, getContext()); + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(SP::SETHIi); + TmpInst.addOperand(MCRegOp); + TmpInst.addOperand(MCOperand::createExpr(Expr)); + Instructions.push_back(TmpInst); + PrevReg = MCRegOp; + } + + if (!IsImm || ((ImmValue & 0x1fff) != 0 || ImmValue == 0)) { + MCInst TmpInst; + const MCExpr *Expr = + SparcMCExpr::Create(SparcMCExpr::VK_Sparc_LO, ValExpr, getContext()); + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(SP::ORri); + TmpInst.addOperand(MCRegOp); + TmpInst.addOperand(PrevReg); + TmpInst.addOperand(MCOperand::createExpr(Expr)); + Instructions.push_back(TmpInst); + } +} + bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -403,8 +450,19 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, MatchingInlineAsm); switch (MatchResult) { case Match_Success: { - Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst, STI); + switch (Inst.getOpcode()) { + default: + Inst.setLoc(IDLoc); + Instructions.push_back(Inst); + break; + case SP::SET: + expandSET(Inst, IDLoc, Instructions); + break; + } + + for (const MCInst &I : Instructions) { + Out.EmitInstruction(I, STI); + } return false; } diff --git a/lib/Target/Sparc/SparcInstrAliases.td b/lib/Target/Sparc/SparcInstrAliases.td index 9f9f57259b8..670e9e989c8 100644 --- a/lib/Target/Sparc/SparcInstrAliases.td +++ b/lib/Target/Sparc/SparcInstrAliases.td @@ -306,6 +306,11 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; // mov simm13, rd -> or %g0, simm13, rd def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; +// set value, rd +// (turns into a sequence of sethi+or, depending on the value) +// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; +def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">; + // restore -> restore %g0, %g0, %g0 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; @@ -329,3 +334,4 @@ def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1, def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>, Requires<[HasHardQuad]>; + diff --git a/lib/Target/Sparc/SparcInstrFormats.td b/lib/Target/Sparc/SparcInstrFormats.td index 4c97687b14d..74ccf551e47 100644 --- a/lib/Target/Sparc/SparcInstrFormats.td +++ b/lib/Target/Sparc/SparcInstrFormats.td @@ -331,3 +331,11 @@ class TRAPSPri op3Val, dag outs, dag ins, string asmstr, let Inst{10-8} = 0; let Inst{7-0} = imm; } + +// Pseudo-instructions for alternate assembly syntax (never used by codegen). +// These are aliases that require C++ handling to convert to the target +// instruction, while InstAliases can be handled directly by tblgen. +class AsmPseudoInst + : InstSP { + let isPseudo = 1; +} diff --git a/test/MC/Sparc/sparc-synthetic-instructions.s b/test/MC/Sparc/sparc-synthetic-instructions.s new file mode 100644 index 00000000000..5b5a1a77db9 --- /dev/null +++ b/test/MC/Sparc/sparc-synthetic-instructions.s @@ -0,0 +1,17 @@ +! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s +! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s + +! Section A.3 Synthetic Instructions + ! CHECK: sethi %hi(40000), %g1 ! encoding: [0x03,0b00AAAAAA,A,A] + ! CHECK: ! fixup A - offset: 0, value: %hi(40000), kind: fixup_sparc_hi22 + ! CHECK: or %g1, %lo(40000), %g1 ! encoding: [0x82,0x10,0b011000AA,A] + ! CHECK: ! fixup A - offset: 0, value: %lo(40000), kind: fixup_sparc_lo10 + set 40000, %g1 + ! CHECK: mov %lo(1), %g1 ! encoding: [0x82,0x10,0b001000AA,A] + ! CHECK: ! fixup A - offset: 0, value: %lo(1), kind: fixup_sparc_lo10 + set 1, %g1 + + ! CHECK: sethi %hi(32768), %g1 ! encoding: [0x03,0b00AAAAAA,A,A] + ! CHECK: ! fixup A - offset: 0, value: %hi(32768), kind: fixup_sparc_hi22 + set 32768, %g1 + -- 2.34.1