From ca795b61be6274813b7c7bd2c63b60cf60f18462 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Fri, 15 Nov 2013 11:04:16 +0000 Subject: [PATCH] [mips][msa] Build all the tests in little and big endian modes and correct an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/msa/2r.ll | 1 + test/CodeGen/Mips/msa/2r_vector_scalar.ll | 1 + test/CodeGen/Mips/msa/2rf.ll | 1 + test/CodeGen/Mips/msa/2rf_exup.ll | 1 + test/CodeGen/Mips/msa/2rf_float_int.ll | 1 + test/CodeGen/Mips/msa/2rf_fq.ll | 1 + test/CodeGen/Mips/msa/2rf_int_float.ll | 1 + test/CodeGen/Mips/msa/2rf_tq.ll | 1 + test/CodeGen/Mips/msa/3r-a.ll | 1 + test/CodeGen/Mips/msa/3r-b.ll | 2 + test/CodeGen/Mips/msa/3r-c.ll | 1 + test/CodeGen/Mips/msa/3r-d.ll | 1 + test/CodeGen/Mips/msa/3r-i.ll | 1 + test/CodeGen/Mips/msa/3r-m.ll | 1 + test/CodeGen/Mips/msa/3r-p.ll | 1 + test/CodeGen/Mips/msa/3r-s.ll | 1 + test/CodeGen/Mips/msa/3r-v.ll | 1 + test/CodeGen/Mips/msa/3r_4r.ll | 1 + test/CodeGen/Mips/msa/3r_4r_widen.ll | 1 + test/CodeGen/Mips/msa/3r_splat.ll | 2 + test/CodeGen/Mips/msa/3rf.ll | 1 + test/CodeGen/Mips/msa/3rf_4rf.ll | 1 + test/CodeGen/Mips/msa/3rf_4rf_q.ll | 1 + test/CodeGen/Mips/msa/3rf_exdo.ll | 1 + test/CodeGen/Mips/msa/3rf_float_int.ll | 1 + test/CodeGen/Mips/msa/3rf_int_float.ll | 1 + test/CodeGen/Mips/msa/3rf_q.ll | 1 + test/CodeGen/Mips/msa/arithmetic.ll | 1 + test/CodeGen/Mips/msa/arithmetic_float.ll | 1 + test/CodeGen/Mips/msa/basic_operations.ll | 4 +- .../Mips/msa/basic_operations_float.ll | 1 + .../Mips/msa/basic_operations_little.ll | 469 ++++++++++++++++++ test/CodeGen/Mips/msa/bit.ll | 5 + test/CodeGen/Mips/msa/bitcast.ll | 2 +- test/CodeGen/Mips/msa/bitwise.ll | 1 + test/CodeGen/Mips/msa/compare.ll | 1 + test/CodeGen/Mips/msa/compare_float.ll | 1 + test/CodeGen/Mips/msa/elm_copy.ll | 1 + test/CodeGen/Mips/msa/elm_cxcmsa.ll | 1 + test/CodeGen/Mips/msa/elm_insv.ll | 1 + test/CodeGen/Mips/msa/elm_move.ll | 1 + test/CodeGen/Mips/msa/elm_shift_slide.ll | 5 + test/CodeGen/Mips/msa/endian.ll | 107 ++++ test/CodeGen/Mips/msa/i10.ll | 1 + test/CodeGen/Mips/msa/i5-a.ll | 5 + test/CodeGen/Mips/msa/i5-b.ll | 2 + test/CodeGen/Mips/msa/i5-c.ll | 5 + test/CodeGen/Mips/msa/i5-m.ll | 5 + test/CodeGen/Mips/msa/i5-s.ll | 5 + test/CodeGen/Mips/msa/i5_ld_st.ll | 1 + test/CodeGen/Mips/msa/i8.ll | 1 + .../Mips/msa/llvm-stress-s1935737938.ll | 2 + .../Mips/msa/llvm-stress-s3997499501.ll | 2 + .../Mips/msa/llvm-stress-s525530439.ll | 2 + .../Mips/msa/llvm-stress-s997348632.ll | 2 + .../Mips/msa/llvm-stress-sz1-s742806235.ll | 2 + test/CodeGen/Mips/msa/shuffle.ll | 1 + test/CodeGen/Mips/msa/spill.ll | 1 + test/CodeGen/Mips/msa/vecs10.ll | 1 + 59 files changed, 666 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/Mips/msa/basic_operations_little.ll create mode 100644 test/CodeGen/Mips/msa/endian.ll diff --git a/test/CodeGen/Mips/msa/2r.ll b/test/CodeGen/Mips/msa/2r.ll index 273a2a29edf..da35ad82cad 100644 --- a/test/CodeGen/Mips/msa/2r.ll +++ b/test/CodeGen/Mips/msa/2r.ll @@ -1,6 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_nloc_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll index 83d99d71740..6f6e1b9ce2f 100644 --- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -2,6 +2,7 @@ ; convert scalars to vectors. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fill_b_ARG1 = global i32 23, align 16 @llvm_mips_fill_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/2rf.ll b/test/CodeGen/Mips/msa/2rf.ll index 4365c9eca3c..b361ef5eae2 100644 --- a/test/CodeGen/Mips/msa/2rf.ll +++ b/test/CodeGen/Mips/msa/2rf.ll @@ -1,6 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2RF instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_flog2_w_ARG1 = global <4 x float> , align 16 @llvm_mips_flog2_w_RES = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/2rf_exup.ll b/test/CodeGen/Mips/msa/2rf_exup.ll index aad008b6295..8d7cc367040 100644 --- a/test/CodeGen/Mips/msa/2rf_exup.ll +++ b/test/CodeGen/Mips/msa/2rf_exup.ll @@ -2,6 +2,7 @@ ; are encoded with the 2RF instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fexupl_w_ARG1 = global <8 x half> , align 16 @llvm_mips_fexupl_w_RES = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/2rf_float_int.ll b/test/CodeGen/Mips/msa/2rf_float_int.ll index 1dbb2288221..3b5dfda2d1e 100644 --- a/test/CodeGen/Mips/msa/2rf_float_int.ll +++ b/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -2,6 +2,7 @@ ; with the 2RF instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_ffint_s_w_RES = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/2rf_fq.ll b/test/CodeGen/Mips/msa/2rf_fq.ll index da76fdc2109..021dd937fad 100644 --- a/test/CodeGen/Mips/msa/2rf_fq.ll +++ b/test/CodeGen/Mips/msa/2rf_fq.ll @@ -2,6 +2,7 @@ ; encoded with the 2RF instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_ffql_w_ARG1 = global <8 x i16> , align 16 @llvm_mips_ffql_w_RES = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/2rf_int_float.ll b/test/CodeGen/Mips/msa/2rf_int_float.ll index 4a59a7c2ef1..4665ae066a4 100644 --- a/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -3,6 +3,7 @@ ; as fclass are also here. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fclass_w_RES = global <4 x i32> , align 16 diff --git a/test/CodeGen/Mips/msa/2rf_tq.ll b/test/CodeGen/Mips/msa/2rf_tq.ll index efd962cac86..6f3c508f5b8 100644 --- a/test/CodeGen/Mips/msa/2rf_tq.ll +++ b/test/CodeGen/Mips/msa/2rf_tq.ll @@ -2,6 +2,7 @@ ; encoded with the 2RF instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_ftq_h_ARG1 = global <4 x float> , align 16 @llvm_mips_ftq_h_ARG2 = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-a.ll b/test/CodeGen/Mips/msa/3r-a.ll index 0ad02a05c98..dab15b66b7c 100644 --- a/test/CodeGen/Mips/msa/3r-a.ll +++ b/test/CodeGen/Mips/msa/3r-a.ll @@ -2,6 +2,7 @@ ; There are lots of these so this covers those beginning with 'a' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s ; It should fail to compile without fp64. ; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ diff --git a/test/CodeGen/Mips/msa/3r-b.ll b/test/CodeGen/Mips/msa/3r-b.ll index 5677d19eb7b..7c45b2bf943 100644 --- a/test/CodeGen/Mips/msa/3r-b.ll +++ b/test/CodeGen/Mips/msa/3r-b.ll @@ -2,6 +2,8 @@ ; There are lots of these so this covers those beginning with 'b' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; XFAIL: * @llvm_mips_bclr_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-c.ll b/test/CodeGen/Mips/msa/3r-c.ll index 84d8fa29ef5..6ec92c284fe 100644 --- a/test/CodeGen/Mips/msa/3r-c.ll +++ b/test/CodeGen/Mips/msa/3r-c.ll @@ -2,6 +2,7 @@ ; There are lots of these so this covers those beginning with 'c' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_ceq_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ceq_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-d.ll b/test/CodeGen/Mips/msa/3r-d.ll index 48c83a6f23a..0099554a8ee 100644 --- a/test/CodeGen/Mips/msa/3r-d.ll +++ b/test/CodeGen/Mips/msa/3r-d.ll @@ -2,6 +2,7 @@ ; There are lots of these so this covers those beginning with 'd' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_div_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_div_s_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-i.ll b/test/CodeGen/Mips/msa/3r-i.ll index c04734d350a..2ef30471b02 100644 --- a/test/CodeGen/Mips/msa/3r-i.ll +++ b/test/CodeGen/Mips/msa/3r-i.ll @@ -2,6 +2,7 @@ ; There are lots of these so this covers those beginning with 'i' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_ilvev_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ilvev_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-m.ll b/test/CodeGen/Mips/msa/3r-m.ll index c8de6d27152..ddfd720a2f8 100644 --- a/test/CodeGen/Mips/msa/3r-m.ll +++ b/test/CodeGen/Mips/msa/3r-m.ll @@ -2,6 +2,7 @@ ; There are lots of these so this covers those beginning with 'm' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_max_a_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_max_a_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-p.ll b/test/CodeGen/Mips/msa/3r-p.ll index 4620f88f419..852023b0824 100644 --- a/test/CodeGen/Mips/msa/3r-p.ll +++ b/test/CodeGen/Mips/msa/3r-p.ll @@ -2,6 +2,7 @@ ; There are lots of these so this covers those beginning with 'p' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_pckev_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_pckev_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-s.ll b/test/CodeGen/Mips/msa/3r-s.ll index 1b894cf5a49..30cf265233e 100644 --- a/test/CodeGen/Mips/msa/3r-s.ll +++ b/test/CodeGen/Mips/msa/3r-s.ll @@ -2,6 +2,7 @@ ; There are lots of these so this covers those beginning with 's' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sld_b_ARG2 = global i32 10, align 16 diff --git a/test/CodeGen/Mips/msa/3r-v.ll b/test/CodeGen/Mips/msa/3r-v.ll index fb547cf0bf4..c9693f90d55 100644 --- a/test/CodeGen/Mips/msa/3r-v.ll +++ b/test/CodeGen/Mips/msa/3r-v.ll @@ -2,6 +2,7 @@ ; There are lots of these so this covers those beginning with 'v' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_vshf_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_vshf_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r_4r.ll b/test/CodeGen/Mips/msa/3r_4r.ll index 2e341d01ce6..b7fd7283788 100644 --- a/test/CodeGen/Mips/msa/3r_4r.ll +++ b/test/CodeGen/Mips/msa/3r_4r.ll @@ -2,6 +2,7 @@ ; use the result as a third operand. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_maddv_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_maddv_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r_4r_widen.ll b/test/CodeGen/Mips/msa/3r_4r_widen.ll index 6dd7fbcdc12..7063e4566a7 100644 --- a/test/CodeGen/Mips/msa/3r_4r_widen.ll +++ b/test/CodeGen/Mips/msa/3r_4r_widen.ll @@ -3,6 +3,7 @@ ; operands had. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r_splat.ll b/test/CodeGen/Mips/msa/3r_splat.ll index a10cf5c51a1..6b0cb26f8c8 100644 --- a/test/CodeGen/Mips/msa/3r_splat.ll +++ b/test/CodeGen/Mips/msa/3r_splat.ll @@ -3,6 +3,8 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck -check-prefix=MIPS32 %s @llvm_mips_splat_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_splat_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3rf.ll b/test/CodeGen/Mips/msa/3rf.ll index ea1291e7198..ae665afcc95 100644 --- a/test/CodeGen/Mips/msa/3rf.ll +++ b/test/CodeGen/Mips/msa/3rf.ll @@ -1,6 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fadd_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fadd_w_ARG2 = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/3rf_4rf.ll b/test/CodeGen/Mips/msa/3rf_4rf.ll index 9c446c904df..67ef7fd2bae 100644 --- a/test/CodeGen/Mips/msa/3rf_4rf.ll +++ b/test/CodeGen/Mips/msa/3rf_4rf.ll @@ -2,6 +2,7 @@ ; use the result as a third operand. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fmadd_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fmadd_w_ARG2 = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/test/CodeGen/Mips/msa/3rf_4rf_q.ll index 888a022e3d2..de28be0b1c2 100644 --- a/test/CodeGen/Mips/msa/3rf_4rf_q.ll +++ b/test/CodeGen/Mips/msa/3rf_4rf_q.ll @@ -2,6 +2,7 @@ ; use the result as a third operand and perform fixed-point operations. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_madd_q_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_madd_q_h_ARG2 = global <8 x i16> , align 16 diff --git a/test/CodeGen/Mips/msa/3rf_exdo.ll b/test/CodeGen/Mips/msa/3rf_exdo.ll index 16a3c81841f..8a7f268a506 100644 --- a/test/CodeGen/Mips/msa/3rf_exdo.ll +++ b/test/CodeGen/Mips/msa/3rf_exdo.ll @@ -2,6 +2,7 @@ ; 3RF instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fexdo_h_ARG1 = global <4 x float> , align 16 @llvm_mips_fexdo_h_ARG2 = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/3rf_float_int.ll b/test/CodeGen/Mips/msa/3rf_float_int.ll index a446ebd0b78..7b01e1721db 100644 --- a/test/CodeGen/Mips/msa/3rf_float_int.ll +++ b/test/CodeGen/Mips/msa/3rf_float_int.ll @@ -2,6 +2,7 @@ ; take an integer as an operand. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fexp2_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fexp2_w_ARG2 = global <4 x i32> , align 16 diff --git a/test/CodeGen/Mips/msa/3rf_int_float.ll b/test/CodeGen/Mips/msa/3rf_int_float.ll index 3dbcc79f4cb..5624771b835 100644 --- a/test/CodeGen/Mips/msa/3rf_int_float.ll +++ b/test/CodeGen/Mips/msa/3rf_int_float.ll @@ -2,6 +2,7 @@ ; produce an integer as a result. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_fcaf_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fcaf_w_ARG2 = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/3rf_q.ll b/test/CodeGen/Mips/msa/3rf_q.ll index 0504fe840b6..f7000ee913a 100644 --- a/test/CodeGen/Mips/msa/3rf_q.ll +++ b/test/CodeGen/Mips/msa/3rf_q.ll @@ -2,6 +2,7 @@ ; format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_mul_q_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_mul_q_h_ARG2 = global <8 x i16> , align 16 diff --git a/test/CodeGen/Mips/msa/arithmetic.ll b/test/CodeGen/Mips/msa/arithmetic.ll index 512a1c1824b..09ee5023c7b 100644 --- a/test/CodeGen/Mips/msa/arithmetic.ll +++ b/test/CodeGen/Mips/msa/arithmetic.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { ; CHECK: add_v16i8: diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll index 43a1f29fc7f..dc387212920 100644 --- a/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { ; CHECK: add_v4f32: diff --git a/test/CodeGen/Mips/msa/basic_operations.ll b/test/CodeGen/Mips/msa/basic_operations.ll index 73c17dc468b..2f153bfdfe9 100644 --- a/test/CodeGen/Mips/msa/basic_operations.ll +++ b/test/CodeGen/Mips/msa/basic_operations.ll @@ -22,8 +22,8 @@ define void @const_v16i8() nounwind { store volatile <16 x i8> , <16 x i8>*@v16i8 ; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo( - store volatile <16 x i8> , <16 x i8>*@v16i8 - ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 258 + store volatile <16 x i8> , <16 x i8>*@v16i8 + ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 256 store volatile <16 x i8> , <16 x i8>*@v16i8 ; MIPS32-DAG: lui [[R2:\$[0-9]+]], 258 diff --git a/test/CodeGen/Mips/msa/basic_operations_float.ll b/test/CodeGen/Mips/msa/basic_operations_float.ll index 7f6db85d2ac..1f538108a1f 100644 --- a/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s @v4f32 = global <4 x float> @v2f64 = global <2 x double> diff --git a/test/CodeGen/Mips/msa/basic_operations_little.ll b/test/CodeGen/Mips/msa/basic_operations_little.ll new file mode 100644 index 00000000000..e091ed8edd1 --- /dev/null +++ b/test/CodeGen/Mips/msa/basic_operations_little.ll @@ -0,0 +1,469 @@ +; This test will be merged back into basic_operations.ll once FileCheck accepts multiple prefixes. + +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s + +@v4i8 = global <4 x i8> +@v16i8 = global <16 x i8> +@v8i16 = global <8 x i16> +@v4i32 = global <4 x i32> +@v2i64 = global <2 x i64> +@i64 = global i64 0 + +define void @const_v16i8() nounwind { + ; MIPS32: const_v16i8: + + store volatile <16 x i8> , <16 x i8>*@v16i8 + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 + + store volatile <16 x i8> , <16 x i8>*@v16i8 + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 1 + + store volatile <16 x i8> , <16 x i8>*@v16i8 + ; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo( + + store volatile <16 x i8> , <16 x i8>*@v16i8 + ; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo( + + store volatile <16 x i8> , <16 x i8>*@v16i8 + ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 1 + + store volatile <16 x i8> , <16 x i8>*@v16i8 + ; MIPS32-DAG: lui [[R2:\$[0-9]+]], 1027 + ; MIPS32-DAG: ori [[R2]], [[R2]], 513 + ; MIPS32-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] + + store volatile <16 x i8> , <16 x i8>*@v16i8 + ; MIPS32: ld.b [[R1:\$w[0-9]+]], %lo( + + ret void + ; MIPS32: .size const_v16i8 +} + +define void @const_v8i16() nounwind { + ; MIPS32: const_v8i16: + + store volatile <8 x i16> , <8 x i16>*@v8i16 + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 + + store volatile <8 x i16> , <8 x i16>*@v8i16 + ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 1 + + store volatile <8 x i16> , <8 x i16>*@v8i16 + ; MIPS32: ld.h [[R1:\$w[0-9]+]], %lo( + + store volatile <8 x i16> , <8 x i16>*@v8i16 + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 4 + + store volatile <8 x i16> , <8 x i16>*@v8i16 + ; MIPS32-DAG: lui [[R2:\$[0-9]+]], 2 + ; MIPS32-DAG: ori [[R2]], [[R2]], 1 + ; MIPS32-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]] + + store volatile <8 x i16> , <8 x i16>*@v8i16 + ; MIPS32: ld.h [[R1:\$w[0-9]+]], %lo( + + ret void + ; MIPS32: .size const_v8i16 +} + +define void @const_v4i32() nounwind { + ; MIPS32: const_v4i32: + + store volatile <4 x i32> , <4 x i32>*@v4i32 + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 + + store volatile <4 x i32> , <4 x i32>*@v4i32 + ; MIPS32: ldi.w [[R1:\$w[0-9]+]], 1 + + store volatile <4 x i32> , <4 x i32>*@v4i32 + ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + + store volatile <4 x i32> , <4 x i32>*@v4i32 + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 1 + + store volatile <4 x i32> , <4 x i32>*@v4i32 + ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 1 + + store volatile <4 x i32> , <4 x i32>*@v4i32 + ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + + store volatile <4 x i32> , <4 x i32>*@v4i32 + ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + + ret void + ; MIPS32: .size const_v4i32 +} + +define void @const_v2i64() nounwind { + ; MIPS32: const_v2i64: + + store volatile <2 x i64> , <2 x i64>*@v2i64 + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0 + + store volatile <2 x i64> , <2 x i64>*@v2i64 + ; MIPS32: ldi.b [[R1:\$w[0-9]+]], 1 + + store volatile <2 x i64> , <2 x i64>*@v2i64 + ; MIPS32: ldi.h [[R1:\$w[0-9]+]], 1 + + store volatile <2 x i64> , <2 x i64>*@v2i64 + ; MIPS32: ldi.w [[R1:\$w[0-9]+]], 1 + + store volatile <2 x i64> , <2 x i64>*@v2i64 + ; MIPS32: ldi.d [[R1:\$w[0-9]+]], 1 + + store volatile <2 x i64> , <2 x i64>*@v2i64 + ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + + store volatile <2 x i64> , <2 x i64>*@v2i64 + ; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo( + + ret void + ; MIPS32: .size const_v2i64 +} + +define void @nonconst_v16i8(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g, i8 %h) nounwind { + ; MIPS32: nonconst_v16i8: + + %1 = insertelement <16 x i8> undef, i8 %a, i32 0 + %2 = insertelement <16 x i8> %1, i8 %b, i32 1 + %3 = insertelement <16 x i8> %2, i8 %c, i32 2 + %4 = insertelement <16 x i8> %3, i8 %d, i32 3 + %5 = insertelement <16 x i8> %4, i8 %e, i32 4 + %6 = insertelement <16 x i8> %5, i8 %f, i32 5 + %7 = insertelement <16 x i8> %6, i8 %g, i32 6 + %8 = insertelement <16 x i8> %7, i8 %h, i32 7 + %9 = insertelement <16 x i8> %8, i8 %h, i32 8 + %10 = insertelement <16 x i8> %9, i8 %h, i32 9 + %11 = insertelement <16 x i8> %10, i8 %h, i32 10 + %12 = insertelement <16 x i8> %11, i8 %h, i32 11 + %13 = insertelement <16 x i8> %12, i8 %h, i32 12 + %14 = insertelement <16 x i8> %13, i8 %h, i32 13 + %15 = insertelement <16 x i8> %14, i8 %h, i32 14 + %16 = insertelement <16 x i8> %15, i8 %h, i32 15 + ; MIPS32-DAG: insert.b [[R1:\$w[0-9]+]][0], $4 + ; MIPS32-DAG: insert.b [[R1]][1], $5 + ; MIPS32-DAG: insert.b [[R1]][2], $6 + ; MIPS32-DAG: insert.b [[R1]][3], $7 + ; MIPS32-DAG: lbu [[R2:\$[0-9]+]], 16($sp) + ; MIPS32-DAG: insert.b [[R1]][4], [[R2]] + ; MIPS32-DAG: lbu [[R3:\$[0-9]+]], 20($sp) + ; MIPS32-DAG: insert.b [[R1]][5], [[R3]] + ; MIPS32-DAG: lbu [[R4:\$[0-9]+]], 24($sp) + ; MIPS32-DAG: insert.b [[R1]][6], [[R4]] + ; MIPS32-DAG: lbu [[R5:\$[0-9]+]], 28($sp) + ; MIPS32-DAG: insert.b [[R1]][7], [[R5]] + ; MIPS32-DAG: insert.b [[R1]][8], [[R5]] + ; MIPS32-DAG: insert.b [[R1]][9], [[R5]] + ; MIPS32-DAG: insert.b [[R1]][10], [[R5]] + ; MIPS32-DAG: insert.b [[R1]][11], [[R5]] + ; MIPS32-DAG: insert.b [[R1]][12], [[R5]] + ; MIPS32-DAG: insert.b [[R1]][13], [[R5]] + ; MIPS32-DAG: insert.b [[R1]][14], [[R5]] + ; MIPS32-DAG: insert.b [[R1]][15], [[R5]] + + store volatile <16 x i8> %16, <16 x i8>*@v16i8 + + ret void + ; MIPS32: .size nonconst_v16i8 +} + +define void @nonconst_v8i16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h) nounwind { + ; MIPS32: nonconst_v8i16: + + %1 = insertelement <8 x i16> undef, i16 %a, i32 0 + %2 = insertelement <8 x i16> %1, i16 %b, i32 1 + %3 = insertelement <8 x i16> %2, i16 %c, i32 2 + %4 = insertelement <8 x i16> %3, i16 %d, i32 3 + %5 = insertelement <8 x i16> %4, i16 %e, i32 4 + %6 = insertelement <8 x i16> %5, i16 %f, i32 5 + %7 = insertelement <8 x i16> %6, i16 %g, i32 6 + %8 = insertelement <8 x i16> %7, i16 %h, i32 7 + ; MIPS32-DAG: insert.h [[R1:\$w[0-9]+]][0], $4 + ; MIPS32-DAG: insert.h [[R1]][1], $5 + ; MIPS32-DAG: insert.h [[R1]][2], $6 + ; MIPS32-DAG: insert.h [[R1]][3], $7 + ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 16($sp) + ; MIPS32-DAG: insert.h [[R1]][4], [[R2]] + ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 20($sp) + ; MIPS32-DAG: insert.h [[R1]][5], [[R2]] + ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 24($sp) + ; MIPS32-DAG: insert.h [[R1]][6], [[R2]] + ; MIPS32-DAG: lhu [[R2:\$[0-9]+]], 28($sp) + ; MIPS32-DAG: insert.h [[R1]][7], [[R2]] + + store volatile <8 x i16> %8, <8 x i16>*@v8i16 + + ret void + ; MIPS32: .size nonconst_v8i16 +} + +define void @nonconst_v4i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { + ; MIPS32: nonconst_v4i32: + + %1 = insertelement <4 x i32> undef, i32 %a, i32 0 + %2 = insertelement <4 x i32> %1, i32 %b, i32 1 + %3 = insertelement <4 x i32> %2, i32 %c, i32 2 + %4 = insertelement <4 x i32> %3, i32 %d, i32 3 + ; MIPS32: insert.w [[R1:\$w[0-9]+]][0], $4 + ; MIPS32: insert.w [[R1]][1], $5 + ; MIPS32: insert.w [[R1]][2], $6 + ; MIPS32: insert.w [[R1]][3], $7 + + store volatile <4 x i32> %4, <4 x i32>*@v4i32 + + ret void + ; MIPS32: .size nonconst_v4i32 +} + +define void @nonconst_v2i64(i64 %a, i64 %b) nounwind { + ; MIPS32: nonconst_v2i64: + + %1 = insertelement <2 x i64> undef, i64 %a, i32 0 + %2 = insertelement <2 x i64> %1, i64 %b, i32 1 + ; MIPS32: insert.w [[R1:\$w[0-9]+]][0], $4 + ; MIPS32: insert.w [[R1]][1], $5 + ; MIPS32: insert.w [[R1]][2], $6 + ; MIPS32: insert.w [[R1]][3], $7 + + store volatile <2 x i64> %2, <2 x i64>*@v2i64 + + ret void + ; MIPS32: .size nonconst_v2i64 +} + +define i32 @extract_sext_v16i8() nounwind { + ; MIPS32: extract_sext_v16i8: + + %1 = load <16 x i8>* @v16i8 + ; MIPS32-DAG: ld.b [[R1:\$w[0-9]+]], + + %2 = add <16 x i8> %1, %1 + ; MIPS32-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] + + %3 = extractelement <16 x i8> %2, i32 1 + %4 = sext i8 %3 to i32 + ; MIPS32-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1] + ; MIPS32-NOT: sll + ; MIPS32-NOT: sra + + ret i32 %4 + ; MIPS32: .size extract_sext_v16i8 +} + +define i32 @extract_sext_v8i16() nounwind { + ; MIPS32: extract_sext_v8i16: + + %1 = load <8 x i16>* @v8i16 + ; MIPS32-DAG: ld.h [[R1:\$w[0-9]+]], + + %2 = add <8 x i16> %1, %1 + ; MIPS32-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] + + %3 = extractelement <8 x i16> %2, i32 1 + %4 = sext i16 %3 to i32 + ; MIPS32-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1] + ; MIPS32-NOT: sll + ; MIPS32-NOT: sra + + ret i32 %4 + ; MIPS32: .size extract_sext_v8i16 +} + +define i32 @extract_sext_v4i32() nounwind { + ; MIPS32: extract_sext_v4i32: + + %1 = load <4 x i32>* @v4i32 + ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], + + %2 = add <4 x i32> %1, %1 + ; MIPS32-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + + %3 = extractelement <4 x i32> %2, i32 1 + ; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][1] + + ret i32 %3 + ; MIPS32: .size extract_sext_v4i32 +} + +define i64 @extract_sext_v2i64() nounwind { + ; MIPS32: extract_sext_v2i64: + + %1 = load <2 x i64>* @v2i64 + ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], + + %2 = add <2 x i64> %1, %1 + ; MIPS32-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] + + %3 = extractelement <2 x i64> %2, i32 1 + ; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2] + ; MIPS32-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3] + ; MIPS32-NOT: sll + ; MIPS32-NOT: sra + + ret i64 %3 + ; MIPS32: .size extract_sext_v2i64 +} + +define i32 @extract_zext_v16i8() nounwind { + ; MIPS32: extract_zext_v16i8: + + %1 = load <16 x i8>* @v16i8 + ; MIPS32-DAG: ld.b [[R1:\$w[0-9]+]], + + %2 = add <16 x i8> %1, %1 + ; MIPS32-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] + + %3 = extractelement <16 x i8> %2, i32 1 + %4 = zext i8 %3 to i32 + ; MIPS32-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1] + ; MIPS32-NOT: andi + + ret i32 %4 + ; MIPS32: .size extract_zext_v16i8 +} + +define i32 @extract_zext_v8i16() nounwind { + ; MIPS32: extract_zext_v8i16: + + %1 = load <8 x i16>* @v8i16 + ; MIPS32-DAG: ld.h [[R1:\$w[0-9]+]], + + %2 = add <8 x i16> %1, %1 + ; MIPS32-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] + + %3 = extractelement <8 x i16> %2, i32 1 + %4 = zext i16 %3 to i32 + ; MIPS32-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1] + ; MIPS32-NOT: andi + + ret i32 %4 + ; MIPS32: .size extract_zext_v8i16 +} + +define i32 @extract_zext_v4i32() nounwind { + ; MIPS32: extract_zext_v4i32: + + %1 = load <4 x i32>* @v4i32 + ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], + + %2 = add <4 x i32> %1, %1 + ; MIPS32-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] + + %3 = extractelement <4 x i32> %2, i32 1 + ; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][1] + + ret i32 %3 + ; MIPS32: .size extract_zext_v4i32 +} + +define i64 @extract_zext_v2i64() nounwind { + ; MIPS32: extract_zext_v2i64: + + %1 = load <2 x i64>* @v2i64 + ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]], + + %2 = add <2 x i64> %1, %1 + ; MIPS32-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] + + %3 = extractelement <2 x i64> %2, i32 1 + ; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2] + ; MIPS32-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3] + ; MIPS32-NOT: andi + + ret i64 %3 + ; MIPS32: .size extract_zext_v2i64 +} + +define void @insert_v16i8(i32 %a) nounwind { + ; MIPS32: insert_v16i8: + + %1 = load <16 x i8>* @v16i8 + ; MIPS32-DAG: ld.b [[R1:\$w[0-9]+]], + + %a2 = trunc i32 %a to i8 + %a3 = sext i8 %a2 to i32 + %a4 = trunc i32 %a3 to i8 + ; MIPS32-NOT: andi + ; MIPS32-NOT: sra + + %2 = insertelement <16 x i8> %1, i8 %a4, i32 1 + ; MIPS32-DAG: insert.b [[R1]][1], $4 + + store <16 x i8> %2, <16 x i8>* @v16i8 + ; MIPS32-DAG: st.b [[R1]] + + ret void + ; MIPS32: .size insert_v16i8 +} + +define void @insert_v8i16(i32 %a) nounwind { + ; MIPS32: insert_v8i16: + + %1 = load <8 x i16>* @v8i16 + ; MIPS32-DAG: ld.h [[R1:\$w[0-9]+]], + + %a2 = trunc i32 %a to i16 + %a3 = sext i16 %a2 to i32 + %a4 = trunc i32 %a3 to i16 + ; MIPS32-NOT: andi + ; MIPS32-NOT: sra + + %2 = insertelement <8 x i16> %1, i16 %a4, i32 1 + ; MIPS32-DAG: insert.h [[R1]][1], $4 + + store <8 x i16> %2, <8 x i16>* @v8i16 + ; MIPS32-DAG: st.h [[R1]] + + ret void + ; MIPS32: .size insert_v8i16 +} + +define void @insert_v4i32(i32 %a) nounwind { + ; MIPS32: insert_v4i32: + + %1 = load <4 x i32>* @v4i32 + ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], + + ; MIPS32-NOT: andi + ; MIPS32-NOT: sra + + %2 = insertelement <4 x i32> %1, i32 %a, i32 1 + ; MIPS32-DAG: insert.w [[R1]][1], $4 + + store <4 x i32> %2, <4 x i32>* @v4i32 + ; MIPS32-DAG: st.w [[R1]] + + ret void + ; MIPS32: .size insert_v4i32 +} + +define void @insert_v2i64(i64 %a) nounwind { + ; MIPS32: insert_v2i64: + + %1 = load <2 x i64>* @v2i64 + ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]], + + ; MIPS32-NOT: andi + ; MIPS32-NOT: sra + + %2 = insertelement <2 x i64> %1, i64 %a, i32 1 + ; MIPS32-DAG: insert.w [[R1]][2], $4 + ; MIPS32-DAG: insert.w [[R1]][3], $5 + + store <2 x i64> %2, <2 x i64>* @v2i64 + ; MIPS32-DAG: st.w [[R1]] + + ret void + ; MIPS32: .size insert_v2i64 +} + +define void @truncstore() nounwind { + ; MIPS32: truncstore: + + store volatile <4 x i8> , <4 x i8>*@v4i8 + ; TODO: What code should be emitted? + + ret void + ; MIPS32: .size truncstore +} diff --git a/test/CodeGen/Mips/msa/bit.ll b/test/CodeGen/Mips/msa/bit.ll index 1fdf37090ae..dc8bb8f2b6c 100644 --- a/test/CodeGen/Mips/msa/bit.ll +++ b/test/CodeGen/Mips/msa/bit.ll @@ -1,6 +1,11 @@ +; Both endians should emit the same output for immediate instructions. +; This is not currently true. +; XFAIL: * + ; Test the MSA intrinsics that are encoded with the BIT instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_sat_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sat_s_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/bitcast.ll b/test/CodeGen/Mips/msa/bitcast.ll index 12edf830242..8e880ecd9af 100644 --- a/test/CodeGen/Mips/msa/bitcast.ll +++ b/test/CodeGen/Mips/msa/bitcast.ll @@ -1,7 +1,7 @@ ; Test the bitcast operation for big-endian and little-endian. -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s define void @v16i8_to_v16i8(<16 x i8>* %src, <16 x i8>* %dst) nounwind { entry: diff --git a/test/CodeGen/Mips/msa/bitwise.ll b/test/CodeGen/Mips/msa/bitwise.ll index 5831a08d919..9a88c47b7e1 100644 --- a/test/CodeGen/Mips/msa/bitwise.ll +++ b/test/CodeGen/Mips/msa/bitwise.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s define void @and_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { ; CHECK: and_v16i8: diff --git a/test/CodeGen/Mips/msa/compare.ll b/test/CodeGen/Mips/msa/compare.ll index a7c704e450c..36569a984b3 100644 --- a/test/CodeGen/Mips/msa/compare.ll +++ b/test/CodeGen/Mips/msa/compare.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { ; CHECK: ceq_v16i8: diff --git a/test/CodeGen/Mips/msa/compare_float.ll b/test/CodeGen/Mips/msa/compare_float.ll index 4849928b86d..2fc61f89c7f 100644 --- a/test/CodeGen/Mips/msa/compare_float.ll +++ b/test/CodeGen/Mips/msa/compare_float.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind diff --git a/test/CodeGen/Mips/msa/elm_copy.ll b/test/CodeGen/Mips/msa/elm_copy.ll index 4bf041e29ea..ed3e52cbffc 100644 --- a/test/CodeGen/Mips/msa/elm_copy.ll +++ b/test/CodeGen/Mips/msa/elm_copy.ll @@ -2,6 +2,7 @@ ; are element extraction operations. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_copy_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_copy_s_b_RES = global i32 0, align 16 diff --git a/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/test/CodeGen/Mips/msa/elm_cxcmsa.ll index dc1fcf79ca4..8d6b0ee20ab 100644 --- a/test/CodeGen/Mips/msa/elm_cxcmsa.ll +++ b/test/CodeGen/Mips/msa/elm_cxcmsa.ll @@ -2,6 +2,7 @@ ; instruction format). ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s define i32 @msa_ir_cfcmsa_test() nounwind { entry: diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll index a34002a375c..fa7ceaf0c6b 100644 --- a/test/CodeGen/Mips/msa/elm_insv.ll +++ b/test/CodeGen/Mips/msa/elm_insv.ll @@ -2,6 +2,7 @@ ; instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_insert_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_insert_b_ARG3 = global i32 27, align 16 diff --git a/test/CodeGen/Mips/msa/elm_move.ll b/test/CodeGen/Mips/msa/elm_move.ll index 37fde15c3b5..98c06c732c3 100644 --- a/test/CodeGen/Mips/msa/elm_move.ll +++ b/test/CodeGen/Mips/msa/elm_move.ll @@ -2,6 +2,7 @@ ; format). ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_move_vb_ARG1 = global <16 x i8> , align 16 @llvm_mips_move_vb_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/elm_shift_slide.ll b/test/CodeGen/Mips/msa/elm_shift_slide.ll index d3863c835b0..3b3504b398c 100644 --- a/test/CodeGen/Mips/msa/elm_shift_slide.ll +++ b/test/CodeGen/Mips/msa/elm_shift_slide.ll @@ -1,7 +1,12 @@ +; Both endians should emit the same output for immediate instructions. +; This is not currently true. +; XFAIL: * + ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are either shifts or slides. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_sldi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sldi_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/endian.ll b/test/CodeGen/Mips/msa/endian.ll new file mode 100644 index 00000000000..44d1925f1cf --- /dev/null +++ b/test/CodeGen/Mips/msa/endian.ll @@ -0,0 +1,107 @@ +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s + +@v16i8 = global <16 x i8> +@v8i16 = global <8 x i16> +@v4i32 = global <4 x i32> +@v2i64 = global <2 x i64> + +define void @const_v16i8() nounwind { + ; LITENDIAN: .byte 0 + ; LITENDIAN: .byte 1 + ; LITENDIAN: .byte 2 + ; LITENDIAN: .byte 3 + ; LITENDIAN: .byte 4 + ; LITENDIAN: .byte 5 + ; LITENDIAN: .byte 6 + ; LITENDIAN: .byte 7 + ; LITENDIAN: .byte 8 + ; LITENDIAN: .byte 9 + ; LITENDIAN: .byte 10 + ; LITENDIAN: .byte 11 + ; LITENDIAN: .byte 12 + ; LITENDIAN: .byte 13 + ; LITENDIAN: .byte 14 + ; LITENDIAN: .byte 15 + ; LITENDIAN: const_v16i8: + ; BIGENDIAN: .byte 0 + ; BIGENDIAN: .byte 1 + ; BIGENDIAN: .byte 2 + ; BIGENDIAN: .byte 3 + ; BIGENDIAN: .byte 4 + ; BIGENDIAN: .byte 5 + ; BIGENDIAN: .byte 6 + ; BIGENDIAN: .byte 7 + ; BIGENDIAN: .byte 8 + ; BIGENDIAN: .byte 9 + ; BIGENDIAN: .byte 10 + ; BIGENDIAN: .byte 11 + ; BIGENDIAN: .byte 12 + ; BIGENDIAN: .byte 13 + ; BIGENDIAN: .byte 14 + ; BIGENDIAN: .byte 15 + ; BIGENDIAN: const_v16i8: + + store volatile <16 x i8> , <16 x i8>*@v16i8 + + ret void +} + +define void @const_v8i16() nounwind { + ; LITENDIAN: .2byte 0 + ; LITENDIAN: .2byte 1 + ; LITENDIAN: .2byte 2 + ; LITENDIAN: .2byte 3 + ; LITENDIAN: .2byte 4 + ; LITENDIAN: .2byte 5 + ; LITENDIAN: .2byte 6 + ; LITENDIAN: .2byte 7 + ; LITENDIAN: const_v8i16: + ; BIGENDIAN: .2byte 0 + ; BIGENDIAN: .2byte 1 + ; BIGENDIAN: .2byte 2 + ; BIGENDIAN: .2byte 3 + ; BIGENDIAN: .2byte 4 + ; BIGENDIAN: .2byte 5 + ; BIGENDIAN: .2byte 6 + ; BIGENDIAN: .2byte 7 + ; BIGENDIAN: const_v8i16: + + store volatile <8 x i16> , <8 x i16>*@v8i16 + + ret void +} + +define void @const_v4i32() nounwind { + ; LITENDIAN: .4byte 0 + ; LITENDIAN: .4byte 1 + ; LITENDIAN: .4byte 2 + ; LITENDIAN: .4byte 3 + ; LITENDIAN: const_v4i32: + ; BIGENDIAN: .4byte 0 + ; BIGENDIAN: .4byte 1 + ; BIGENDIAN: .4byte 2 + ; BIGENDIAN: .4byte 3 + ; BIGENDIAN: const_v4i32: + + store volatile <4 x i32> , <4 x i32>*@v4i32 + + ret void +} + +define void @const_v2i64() nounwind { + ; LITENDIAN: .4byte 1 + ; LITENDIAN: .4byte 0 + ; LITENDIAN: .4byte 2 + ; LITENDIAN: .4byte 0 + ; LITENDIAN: const_v2i64: + ; BIGENDIAN: .4byte 0 + ; BIGENDIAN: .4byte 1 + ; BIGENDIAN: .4byte 0 + ; BIGENDIAN: .4byte 2 + ; BIGENDIAN: const_v2i64: + + store volatile <2 x i64> , <2 x i64>*@v2i64 + + ret void +} diff --git a/test/CodeGen/Mips/msa/i10.ll b/test/CodeGen/Mips/msa/i10.ll index 5e8d2598ee5..c5a96174a73 100644 --- a/test/CodeGen/Mips/msa/i10.ll +++ b/test/CodeGen/Mips/msa/i10.ll @@ -1,6 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I10 instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_bnz_b_ARG1 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/i5-a.ll b/test/CodeGen/Mips/msa/i5-a.ll index 1fe83b39f1b..f45df07f76b 100644 --- a/test/CodeGen/Mips/msa/i5-a.ll +++ b/test/CodeGen/Mips/msa/i5-a.ll @@ -1,7 +1,12 @@ +; Both endians should emit the same output for immediate instructions. +; This is not currently true. +; XFAIL: * + ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'a' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_addvi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_addvi_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/i5-b.ll b/test/CodeGen/Mips/msa/i5-b.ll index d1df6e9db6d..f4477a0671b 100644 --- a/test/CodeGen/Mips/msa/i5-b.ll +++ b/test/CodeGen/Mips/msa/i5-b.ll @@ -2,6 +2,8 @@ ; There are lots of these so this covers those beginning with 'b' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; XFAIL: * @llvm_mips_bclri_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bclri_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/i5-c.ll b/test/CodeGen/Mips/msa/i5-c.ll index d23a2df45ff..d63b3ccf2c0 100644 --- a/test/CodeGen/Mips/msa/i5-c.ll +++ b/test/CodeGen/Mips/msa/i5-c.ll @@ -1,7 +1,12 @@ +; Both endians should emit the same output for immediate instructions. +; This is not currently true. +; XFAIL: * + ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'c' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_ceqi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_ceqi_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/i5-m.ll b/test/CodeGen/Mips/msa/i5-m.ll index 3017cd467cc..74e698b4752 100644 --- a/test/CodeGen/Mips/msa/i5-m.ll +++ b/test/CodeGen/Mips/msa/i5-m.ll @@ -1,7 +1,12 @@ +; Both endians should emit the same output for immediate instructions. +; This is not currently true. +; XFAIL: * + ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'm' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_maxi_s_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/i5-s.ll b/test/CodeGen/Mips/msa/i5-s.ll index 77f52bfb1a4..60ba8e1e34b 100644 --- a/test/CodeGen/Mips/msa/i5-s.ll +++ b/test/CodeGen/Mips/msa/i5-s.ll @@ -1,7 +1,12 @@ +; Both endians should emit the same output for immediate instructions. +; This is not currently true. +; XFAIL: * + ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 's' ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_subvi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_subvi_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/i5_ld_st.ll b/test/CodeGen/Mips/msa/i5_ld_st.ll index 7ec93261061..7cc55f2904b 100644 --- a/test/CodeGen/Mips/msa/i5_ld_st.ll +++ b/test/CodeGen/Mips/msa/i5_ld_st.ll @@ -2,6 +2,7 @@ ; are loads or stores. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_ld_b_ARG = global <16 x i8> , align 16 @llvm_mips_ld_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/i8.ll b/test/CodeGen/Mips/msa/i8.ll index f3e8dfc65b3..d2931a72fea 100644 --- a/test/CodeGen/Mips/msa/i8.ll +++ b/test/CodeGen/Mips/msa/i8.ll @@ -1,6 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I8 instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_andi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_andi_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll b/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll index 23675f50348..f9cab037e7c 100644 --- a/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll +++ b/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mips < %s ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s +; RUN: llc -march=mipsel < %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s ; This test originally failed for MSA with a ; `Opc && "Cannot copy registers"' assertion. diff --git a/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll b/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll index 65281132dc9..bef75f3645c 100644 --- a/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll +++ b/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mips < %s ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s +; RUN: llc -march=mipsel < %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s ; This test originally failed to select instructions for extract_vector_elt for ; v4f32 on MSA. diff --git a/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll b/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll index 685c407d020..697871df797 100644 --- a/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll +++ b/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mips < %s ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s +; RUN: llc -march=mipsel < %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s ; This test originally failed for MSA with a ; `Num < NumOperands && "Invalid child # of SDNode!"' assertion. diff --git a/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll b/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll index 399d3a05011..dc4200ad428 100644 --- a/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll +++ b/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mips < %s ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s +; RUN: llc -march=mipsel < %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s ; This test originally failed to select instructions for extract_vector_elt for ; v2f64 on MSA. diff --git a/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll b/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll index 36afffe7657..8c4fcbad65b 100644 --- a/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll +++ b/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mips < %s ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s +; RUN: llc -march=mipsel < %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s ; This test originally failed to select code for a truncstore of a ; build_vector. diff --git a/test/CodeGen/Mips/msa/shuffle.ll b/test/CodeGen/Mips/msa/shuffle.ll index b5df0e0ad36..316c669c3ac 100644 --- a/test/CodeGen/Mips/msa/shuffle.ll +++ b/test/CodeGen/Mips/msa/shuffle.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { ; CHECK: vshf_v16i8_0: diff --git a/test/CodeGen/Mips/msa/spill.ll b/test/CodeGen/Mips/msa/spill.ll index d73a8b59086..66f896ac468 100644 --- a/test/CodeGen/Mips/msa/spill.ll +++ b/test/CodeGen/Mips/msa/spill.ll @@ -2,6 +2,7 @@ ; to have 33 live MSA registers simultaneously ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s define i32 @test_i8(<16 x i8>* %p0, <16 x i8>* %q1) nounwind { entry: diff --git a/test/CodeGen/Mips/msa/vecs10.ll b/test/CodeGen/Mips/msa/vecs10.ll index a00a488401d..e22e0755ef0 100644 --- a/test/CodeGen/Mips/msa/vecs10.ll +++ b/test/CodeGen/Mips/msa/vecs10.ll @@ -1,6 +1,7 @@ ; Test the MSA intrinsics that are encoded with the VECS10 instruction format. ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s @llvm_mips_bnz_v_ARG1 = global <16 x i8> , align 16 -- 2.34.1