From c7139a6f0d3acd198ab9eb536ea1ec52e61ff130 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Thu, 11 Nov 2010 19:07:48 +0000 Subject: [PATCH] Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure. More tests to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMCodeEmitter.cpp | 2 + lib/Target/ARM/ARMInstrFormats.td | 1 + lib/Target/ARM/ARMMCCodeEmitter.cpp | 23 +++++ test/MC/ARM/neont2-abs-encoding.s | 33 +++++++ test/MC/ARM/neont2-add-encoding.s | 138 ++++++++++++++++++++++++++++ 5 files changed, 197 insertions(+) create mode 100644 test/MC/ARM/neont2-abs-encoding.s create mode 100644 test/MC/ARM/neont2-add-encoding.s diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index e85c7d92877..3cb0df54ab9 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -161,6 +161,8 @@ namespace { // are already handled elsewhere. They are placeholders to allow this // encoder to continue to function until the MC encoder is sufficiently // far along that this one can be eliminated entirely. + unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) + const { return 0; } unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 5c6d131125b..c6858892c48 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -1868,6 +1868,7 @@ class NDataI { let Inst{31-25} = 0b1111001; + string PostEncoderMethod = "NEONThumb2DataIPostEncoder"; } class NDataXI &Fixups) const; + unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, + unsigned EncodedValue) const; + void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; } @@ -195,6 +198,26 @@ MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM, return new ARMMCCodeEmitter(TM, Ctx); } +/// NEONThumb2PostEncoder - Post-process encoded NEON data-processing +/// instructions, and rewrite them to their Thumb2 form if we are currently in +/// Thumb2 mode. +unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, + unsigned EncodedValue) const { + const ARMSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.isThumb2()) { + // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved + // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are + // set to 1111. + unsigned Bit24 = EncodedValue & 0x01000000; + unsigned Bit28 = Bit24 << 4; + EncodedValue &= 0xEFFFFFFF; + EncodedValue |= Bit28; + EncodedValue |= 0x0F000000; + } + + return EncodedValue; +} + /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned ARMMCCodeEmitter:: diff --git a/test/MC/ARM/neont2-abs-encoding.s b/test/MC/ARM/neont2-abs-encoding.s new file mode 100644 index 00000000000..dd36133ecb8 --- /dev/null +++ b/test/MC/ARM/neont2-abs-encoding.s @@ -0,0 +1,33 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unkown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vabs.s8 d16, d16 @ encoding: [0x20,0x03,0xf1,0xff] + vabs.s8 d16, d16 +@ CHECK: vabs.s16 d16, d16 @ encoding: [0x20,0x03,0xf5,0xff] + vabs.s16 d16, d16 +@ CHECK: vabs.s32 d16, d16 @ encoding: [0x20,0x03,0xf9,0xff] + vabs.s32 d16, d16 +@ CHECK: vabs.f32 d16, d16 @ encoding: [0x20,0x07,0xf9,0xff] + vabs.f32 d16, d16 +@ CHECK: vabs.s8 q8, q8 @ encoding: [0x60,0x03,0xf1,0xff] + vabs.s8 q8, q8 +@ CHECK: vabs.s16 q8, q8 @ encoding: [0x60,0x03,0xf5,0xff] + vabs.s16 q8, q8 +@ CHECK: vabs.s32 q8, q8 @ encoding: [0x60,0x03,0xf9,0xff] + vabs.s32 q8, q8 +@ CHECK: vabs.f32 q8, q8 @ encoding: [0x60,0x07,0xf9,0xff] + vabs.f32 q8, q8 + +@ CHECK: vqabs.s8 d16, d16 @ encoding: [0x20,0x07,0xf0,0xff] + vqabs.s8 d16, d16 +@ CHECK: vqabs.s16 d16, d16 @ encoding: [0x20,0x07,0xf4,0xff] + vqabs.s16 d16, d16 +@ CHECK: vqabs.s32 d16, d16 @ encoding: [0x20,0x07,0xf8,0xff] + vqabs.s32 d16, d16 +@ CHECK: vqabs.s8 q8, q8 @ encoding: [0x60,0x07,0xf0,0xff] + vqabs.s8 q8, q8 +@ CHECK: vqabs.s16 q8, q8 @ encoding: [0x60,0x07,0xf4,0xff] + vqabs.s16 q8, q8 +@ CHECK: vqabs.s32 q8, q8 @ encoding: [0x60,0x07,0xf8,0xff] + vqabs.s32 q8, q8 diff --git a/test/MC/ARM/neont2-add-encoding.s b/test/MC/ARM/neont2-add-encoding.s new file mode 100644 index 00000000000..f7c32a71973 --- /dev/null +++ b/test/MC/ARM/neont2-add-encoding.s @@ -0,0 +1,138 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s + +.code 16 + +@ CHECK: vadd.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xef] + vadd.i8 d16, d17, d16 +@ CHECK: vadd.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xef] + vadd.i16 d16, d17, d16 +@ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xef] + vadd.i64 d16, d17, d16 +@ CHECK: vadd.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xef] + vadd.i32 d16, d17, d16 +@ CHECK: vadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xef] + vadd.f32 d16, d16, d17 +@ CHECK: vadd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x40,0xef] + vadd.f32 q8, q8, q9 + +@ CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xef] + vaddl.s8 q8, d17, d16 +@ CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xef] + vaddl.s16 q8, d17, d16 +@ CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xef] + vaddl.s32 q8, d17, d16 +@ CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xff] + vaddl.u8 q8, d17, d16 +@ CHECK: vaddl.u16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xff] + vaddl.u16 q8, d17, d16 +@ CHECK: vaddl.u32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xff] + vaddl.u32 q8, d17, d16 + +@ CHECK: vaddw.s8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xef] + vaddw.s8 q8, q8, d18 +@ CHECK: vaddw.s16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xef] + vaddw.s16 q8, q8, d18 +@ CHECK: vaddw.s32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xef] + vaddw.s32 q8, q8, d18 +@ CHECK: vaddw.u8 q8, q8, d18 @ encoding: [0xa2,0x01,0xc0,0xff] + vaddw.u8 q8, q8, d18 +@ CHECK: vaddw.u16 q8, q8, d18 @ encoding: [0xa2,0x01,0xd0,0xff] + vaddw.u16 q8, q8, d18 +@ CHECK: vaddw.u32 q8, q8, d18 @ encoding: [0xa2,0x01,0xe0,0xff] + vaddw.u32 q8, q8, d18 + +@ CHECK: vhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xef] + vhadd.s8 d16, d16, d17 +@ CHECK: vhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xef] + vhadd.s16 d16, d16, d17 +@ CHECK: vhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xef] + vhadd.s32 d16, d16, d17 +@ CHECK: vhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x00,0x40,0xff] + vhadd.u8 d16, d16, d17 +@ CHECK: vhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x00,0x50,0xff] + vhadd.u16 d16, d16, d17 +@ CHECK: vhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x00,0x60,0xff] + vhadd.u32 d16, d16, d17 +@ CHECK: vhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xef] + vhadd.s8 q8, q8, q9 +@ CHECK: vhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xef] + vhadd.s16 q8, q8, q9 +@ CHECK: vhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xef] + vhadd.s32 q8, q8, q9 + @ CHECK: vhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x00,0x40,0xff] + vhadd.u8 q8, q8, q9 +@ CHECK: vhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x00,0x50,0xff] + vhadd.u16 q8, q8, q9 +@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xff] + vhadd.u32 q8, q8, q9 + +@ CHECK: vrhadd.s8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xef] + vrhadd.s8 d16, d16, d17 +@ CHECK: vrhadd.s16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xef] + vrhadd.s16 d16, d16, d17 +@ CHECK: vrhadd.s32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xef] + vrhadd.s32 d16, d16, d17 +@ CHECK: vrhadd.u8 d16, d16, d17 @ encoding: [0xa1,0x01,0x40,0xff] + vrhadd.u8 d16, d16, d17 +@ CHECK: vrhadd.u16 d16, d16, d17 @ encoding: [0xa1,0x01,0x50,0xff] + vrhadd.u16 d16, d16, d17 +@ CHECK: vrhadd.u32 d16, d16, d17 @ encoding: [0xa1,0x01,0x60,0xff] + vrhadd.u32 d16, d16, d17 +@ CHECK: vrhadd.s8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xef] + vrhadd.s8 q8, q8, q9 +@ CHECK: vrhadd.s16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xef] + vrhadd.s16 q8, q8, q9 +@ CHECK: vrhadd.s32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xef] + vrhadd.s32 q8, q8, q9 +@ CHECK: vrhadd.u8 q8, q8, q9 @ encoding: [0xe2,0x01,0x40,0xff] + vrhadd.u8 q8, q8, q9 +@ CHECK: vrhadd.u16 q8, q8, q9 @ encoding: [0xe2,0x01,0x50,0xff] + vrhadd.u16 q8, q8, q9 +@ CHECK: vrhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x01,0x60,0xff] + vrhadd.u32 q8, q8, q9 + +@ CHECK: vqadd.s8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xef] + vqadd.s8 d16, d16, d17 +@ CHECK: vqadd.s16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xef] + vqadd.s16 d16, d16, d17 +@ CHECK: vqadd.s32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xef] + vqadd.s32 d16, d16, d17 +@ CHECK: vqadd.s64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xef] + vqadd.s64 d16, d16, d17 +@ CHECK: vqadd.u8 d16, d16, d17 @ encoding: [0xb1,0x00,0x40,0xff] + vqadd.u8 d16, d16, d17 +@ CHECK: vqadd.u16 d16, d16, d17 @ encoding: [0xb1,0x00,0x50,0xff] + vqadd.u16 d16, d16, d17 +@ CHECK: vqadd.u32 d16, d16, d17 @ encoding: [0xb1,0x00,0x60,0xff] + vqadd.u32 d16, d16, d17 +@ CHECK: vqadd.u64 d16, d16, d17 @ encoding: [0xb1,0x00,0x70,0xff] + vqadd.u64 d16, d16, d17 +@ CHECK: vqadd.s8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xef] + vqadd.s8 q8, q8, q9 +@ CHECK: vqadd.s16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xef] + vqadd.s16 q8, q8, q9 +@ CHECK: vqadd.s32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xef] + vqadd.s32 q8, q8, q9 +@ CHECK: vqadd.s64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xef] + vqadd.s64 q8, q8, q9 +@ CHECK: vqadd.u8 q8, q8, q9 @ encoding: [0xf2,0x00,0x40,0xff] + vqadd.u8 q8, q8, q9 +@ CHECK: vqadd.u16 q8, q8, q9 @ encoding: [0xf2,0x00,0x50,0xff] + vqadd.u16 q8, q8, q9 +@ CHECK: vqadd.u32 q8, q8, q9 @ encoding: [0xf2,0x00,0x60,0xff] + vqadd.u32 q8, q8, q9 +@ CHECK: vqadd.u64 q8, q8, q9 @ encoding: [0xf2,0x00,0x70,0xff] + vqadd.u64 q8, q8, q9 + +@ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xef] + vaddhn.i16 d16, q8, q9 +@ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xef] + vaddhn.i32 d16, q8, q9 +@ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xef] + vaddhn.i64 d16, q8, q9 +@ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xff] + vraddhn.i16 d16, q8, q9 +@ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xff] + vraddhn.i32 d16, q8, q9 +@ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xff] + vraddhn.i64 d16, q8, q9 -- 2.34.1